Smartpin Diagram (now with %P..P bit mode table)

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  • evanh wrote: »
    Doh, got that one wrong. So R1 will be for 600 ohms and R1 + R2 for 75 ohms?

    I don't remember, exactly, but I think that's how it works.
  • evanh wrote: »
    Oh, how slow is the "Slow DAC" in the comparator? I'd assumed there was an analogue link from the Fast DAC. EDIT: Does it latch on low on ENA?

    The slow DAC doesn't latch, at all. It just uses M[7:0]. Is is an R-2R DAC where R = 300K ohms.
  • Cool. Not so slow at all, just the nature of R-C charging with parasitic capacitance.

  • What is the box on the right hand side labeled "PAD DRIVER" doing? The thing with inputs DIR, OUT, H2..H0, L2..L0, and outputs GP, GN, PA?
  • whicker wrote: »
    What is the box on the right hand side labeled "PAD DRIVER" doing? The thing with inputs DIR, OUT, H2..H0, L2..L0, and outputs GP, GN, PA?

    It drives the resistance and current modes, plus the main output transistors on the pad, based on the HHH and LLL fields.
  • evanhevanh Posts: 9,970
    edited 2020-04-14 - 03:29:31
    Final stage pin drive for OUT+DIR, ie: Not the DAC.

    EDIT: Ah, the full strength transistors are controlled by GP/GN, whereas the lower strength ones are located internal to the PAD DRIVER block. That's why PA is there too.

  • evanhevanh Posts: 9,970
    edited 2020-04-14 - 03:45:16
    I've placed a red X showing the cut for Rev C change:
    prop2-revC-mod.png
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  • evanhevanh Posts: 9,970
    edited 2020-04-14 - 04:11:20
    Oh, penny dropped! The thirteen Mxx mode bits are the same ones as the "Code" in the old Pin_Modes.png file from way back.

    EDIT: Interesting. I think I've been reading an out-of-date version of the pin modes. Found another one, called PAD_IO_modes.png, that appears to have corrections. Not entirely sure.

    EDIT2: Ah, the prop2 main doc has the second one.
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  • Yeah, pad_io_modes.png is correct, except the PinB ADC mode now floats.
  • cgracey wrote: »
    evanh wrote: »
    Oh bother, I just noticed that "Other" and OUT also enables the ADC is some situations. That's definitely more than I had counted on.
    That's just kind of incidental to the design. Not really useful, but needed documenting.
    True, it's also a mode select rather than data path.

  • Okay, I've updated my most recent edition - https://forums.parallax.com/discussion/comment/1494126/#Comment_1494126

    Notable changes, correcting my guesses:
    - DAC drive is independent of logic drive
    - Comparator has its own DAC
  • What's a good name for this box?
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  • Rayman wrote: »
    What's a good name for this box?

    I don't know, but on the right side, it would be good to show OUT and ACK going into the box.
  • A Smartcell.
  • Evanh has out going into another box to the left, should it go there instead?
    Here's a screenshot with ack added...
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  • @evanh: Did you intend to remove the inverter on the lower other input?
  • Rayman wrote: »
    @evanh: Did you intend to remove the inverter on the lower other input?
    Yep, I chopped back and forth a couple times actually. In the end I decided that showing it didn't matter because the diagram has no logic functions otherwise ... and at this stage I'm not entirely sure that "Other" is always inverted there anyway.

  • RaymanRayman Posts: 11,364
    edited 2020-04-15 - 00:08:22
    Here's an updated image. Calling red box a "Smart Cell".
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  • RaymanRayman Posts: 11,364
    edited 2020-04-15 - 00:10:05
    It appears to show that DAC and logic can both drive pin at the same time. Is that possible?
    Does the Flash DAC also have an enable signal?
  • cgracey wrote: »
    Rayman wrote: »
    What's a good name for this box?
    I don't know, but on the right side, it would be good to show OUT and ACK going into the box.
    I've named the smartpin's OUT SmartOUT because it's independent of the cog's OUT. For example, SmartOUT can be driving the pin output while, at the same time, OUT is an A/B input source at the F block.

    ACK I had kind of ignored as that's part of WRPIN. Raymans addition looks good to me though.

  • Slight formatting tweak.
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  • Rayman wrote: »
    It appears to show that DAC and logic can both drive pin at the same time. Is that possible?
    Does the Flash DAC also have an enable signal?
    Yep but, in practise no, they are exclusive by the custom control logic.

  • evanhevanh Posts: 9,970
    edited 2020-04-15 - 00:24:13
    Rayman wrote: »
    What's a good name for this box?
    I see it as the whole smartpin, hense why I put the name where I did. It runs as its own little processor. The rest is just plain I/O config like any other microcontroller.

  • I wonder if WXPIN, WYPIN, and RDPIN actually share the same bus with 2 or 3 control signals...

    I guess there should be a WRPIN if we are putting these in...
  • Rayman wrote: »
    I wonder if WXPIN, WYPIN, and RDPIN actually share the same bus with 2 or 3 control signals...
    Maybe but is way outside the scope of this diagram.

    I guess there should be a WRPIN if we are putting these in...
    No, that's not data path. I made that mistake myself earlier.

  • Ok, I see we have the various (%MMM...) etc. showing WRPIN effects.

    What does BitDAC do?

    I think COMP_DAC means it goes to both comparator and DAC, right?
    Maybe could be called Comp&DAC ?
  • Rayman wrote: »
    What does BitDAC do?
    BitDAC is the signal path specific to the BItDAC pin mode. It can come from OUT/Other/SmartOUT.

    I think COMP_DAC means it goes to both comparator and DAC, right?
    Maybe could be called Comp&DAC ?
    Good idea. CompDAC was intended to refer to the CompDAC pin mode though. That's why I also had "DACmode" there earlier.

  • Ok, I have to read what BitDAC pin mode is... Guess it turns single bit into 8 bits at two different levels or something...

    The other thing I need to figure out is SMART_DAC. Not sure what that is...
  • Rayman wrote: »
    Ok, I have to read what BitDAC pin mode is... Guess it turns single bit into 8 bits at two different levels or something...
    Spot on. That's the whole function of that pin mode.
    The other thing I need to figure out is SMART_DAC. Not sure what that is...
    It's simply the data path from the smartpin to the DAC.

  • Do you think what I called “smart cell” as “smartpin”?

    I guess I think of the whole thing as the smartpin...
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