Crazy...
IMHO, the only really crazy thing I can think of would be an FPGA P1 board with Open Verilog code.
I mean, why give the opposition the keys to the factory???
If I understand correctly Chip lives on a walnut farm. I think Parallax should put a few bags of walnuts in the web store occasionally. Just for amusement. Or offer them as prizes in little competitions.
After all, if Chip doesn't get the P2 out fairly soon many people around here are going to want some of his nuts on a plate.
If I understand correctly Chip lives on a walnut farm. I think Parallax should put a few bags of walnuts in the web store occasionally. Just for amusement. Or offer them as prizes in little competitions.
After all, if Chip doesn't get the P2 out fairly soon many people around here are going to want some of his nuts on a plate.
Haha that's the funniest thing I've seen on here in a while.
I hope it's P1 Verilog code, judging by what Chip said OBC thinks, it must be surely!
If it is then it's a brave step and one I hope pays dividends for Chip and Ken.
Do you suggest I start studying Verilog overnight!?!?!?
It's just another programming language. A warning though, it looks a lot like C! :-)
Seriously, it's very interesting learning to think of your code always running in parallel. No need to launch code in a COG to get parallelism. Every statement in a Verilog program runs in parallel with every other one (mostly).
I wish they had used VHDL instead of Verilog. I find the former much easier which is strange as I have used C, which Verilog resembles, for many years. VHDL is a lot more verbose, however.
I wish they had used VHDL instead of Verilog. I find the former much easier which is strange as I have used C, which Verilog resembles, for many years. VHDL is a lot more verbose, however.
I guess I don't know for sure that the P1 will be in Verilog but the P2 code that Chip has shared is.
Maybe it could be interesting for projects with deep pockets. Perhaps you could make it 64 I/O with extra HUB ram and maybe even 160 MHz.
You could switch out the ROM with a C interpreter or something...
I imagine the FPGA chip costs ~$100 or so, but maybe that would be OK sometimes.
Maybe it could be interesting for projects with deep pockets. Perhaps you could make it 64 I/O with extra HUB ram and maybe even 160 MHz.
You could switch out the ROM with a C interpreter or something...
I imagine the FPGA chip costs ~$100 or so, but maybe that would be OK sometimes.
It might just be for learning about core design in Verilog. In fact, I was wondering if Parallax might decide to offer an educational package with FPGA and P1 in Verilog and course materials talking about extending the core or other parts of the P1. They are very strong in education so this might be a good fit. I'd love to take a Parallax course on processor design!
I was sworn to keep it to myself since I'm on the distributor's list..
But since the cat's partway out of the bag, I never said "crazy".. I said, "shocked".
I did question the decision, because it's a VERY bold move. Sorry, you won't get more than that out of me.
Well, if it's what we have been talking about here I guess I'm not that surprised. I think Chip and maybe Ken as well once said that they would release P1 RTL after P2 was in production. This is just a shift in the timeline.
Maybe I'm being dumb (won't be first or last time) or stating the obvious which seems like a big deal to me but not the smarter folks around here.
If you have a P1 FPGA and start adding features and changing things, to use any of your new features effectively, you need to update the tools to recognize and generate code for them. This requires some rather involved and sophisticated programming skills to pull it off. It sounds like fun and neat stuff to learn and work with but how practical is it for 99% of Propeller users?
My guess...the p2 will live only as a FPGA image...and parallax will produce fpga boards that include the image...but then again it is just a guess:)
I hope that's not the case because an FPGA big enough to contain P2 would be a very expensive component. Using an FPGA during development makes sense but not as a delivery vehicle.
Maybe I'm being dumb (won't be first or last time) or stating the obvious which seems like a big deal to me but not the smarter folks around here.
If you have a P1 FPGA and start adding features and changing things, to use any of your new features effectively, you need to update the tools to recognize and generate code for them. This requires some rather involved and sophisticated programming skills to pull it off. It sounds like fun and neat stuff to learn and work with but how practical is it for 99% of Propeller users?
That is only true if you change the instruction set or something very basic about the architecture. If you're just playing with different ways to hook up COGs or adding more hardware assist for peripherals then the toolchain wouldn't have to change. Also, there are at least a few of us who could at least tweak the toolchain to take advantage of new COG features. You're right though, probably not that many people will feel comfortable doing that.
My guess is that the new FPGA boards intended for the P2 are ready, but the P2 isn't ready, so they are going to release the new boards with a P1 image to get them "in the wild" so they will be in place as P2 images become available.
That leaves the question of if there will be a P1 image for the DE0-nano and/or DE2-115? I can see only releasing it for the new board to drive those into the field, but that has the risk of alienating those that invested in the previously used boards.
I don't have time or money to play along right now, but it will be fun to see what others do.
My guess is that the new FPGA boards intended for the P2 are ready, but the P2 isn't ready, so they are going to release the new boards with a P1 image to get them "in the wild" so they will be in place as P2 images become available.
That leaves the question of if there will be a P1 image for the DE0-nano and/or DE2-115? I can see only releasing it for the new board to drive those into the field, but that has the risk of alienating those that invested in the previously used boards.
C.W.
But a P1 binary image on an FPGA won't be all that interesting. May as well wait for the P2 image to be available before buying the board. I think it has to be more than that.
Comments
We could just be patient, or we could work on OBC in the mean time. OBC, on a scale of 0 to 11, exactly how crazy do you rate this?
IMHO, the only really crazy thing I can think of would be an FPGA P1 board with Open Verilog code.
I mean, why give the opposition the keys to the factory???
Ha ha, I got it now!
It's a WEB page. Parallax is going to put up a new WEB page. Awesome!
Nuts? Peanuts? Walnuts? Next? Coconuts!
I think it's a good move honestly, and I'm looking forward to the hacking possibilities. People here will go nuts on it.
After all, if Chip doesn't get the P2 out fairly soon many people around here are going to want some of his nuts on a plate.
Haha that's the funniest thing I've seen on here in a while.
I hope it's P1 Verilog code, judging by what Chip said OBC thinks, it must be surely!
If it is then it's a brave step and one I hope pays dividends for Chip and Ken.
Coley
Just for you, heater, because you're British
ok thanks Chip ,
I had a sleep and could only think that the announcement will be a FPGA board and the only crazy thing would be to open source the P1 code.
Seriously, it's very interesting learning to think of your code always running in parallel. No need to launch code in a COG to get parallelism. Every statement in a Verilog program runs in parallel with every other one (mostly).
If it isn't anybody want to buy a barely used DE2 with a Parallax expansion card?? (Maybe it is a collector's item??)
Icarus Verilog: http://iverilog.icarus.com
Maybe it could be interesting for projects with deep pockets. Perhaps you could make it 64 I/O with extra HUB ram and maybe even 160 MHz.
You could switch out the ROM with a C interpreter or something...
I imagine the FPGA chip costs ~$100 or so, but maybe that would be OK sometimes.
I was sworn to keep it to myself since I'm on the distributor's list.. (Distributors have known since Monday/Tuesday)
But since the cat's partway out of the bag, I never said "crazy".. I said, "shocked".
I did question the decision, because it's a VERY bold move. Sorry, you won't get more than that out of me.
If you have a P1 FPGA and start adding features and changing things, to use any of your new features effectively, you need to update the tools to recognize and generate code for them. This requires some rather involved and sophisticated programming skills to pull it off. It sounds like fun and neat stuff to learn and work with but how practical is it for 99% of Propeller users?
That leaves the question of if there will be a P1 image for the DE0-nano and/or DE2-115? I can see only releasing it for the new board to drive those into the field, but that has the risk of alienating those that invested in the previously used boards.
I don't have time or money to play along right now, but it will be fun to see what others do.
C.W.