Q: What is the fastest ADC input sampling rate, at how many bits?
@Chip: That shifter sounds awesome!
@Bill Henning: assuming an external ADC, I'd guess the max sampling rate for bursts will be the chip clock frequency or half the chip clock frequency. Bit depth, would be set by the external chip, but I'd guess up to 32-bits per capture by the shifter. Makes me tempted to design a 100Msps oscilloscope with the prop 2.
You can get a private license. That's absolutely allowed, and GPL 3 has the patent clause in it, which I think is important in this case, given Chip's position on them.
As for "not going to happen", I wouldn't be so sure.
You can get a private license. That's absolutely allowed, and GPL 3 has the patent clause in it, which I think is important in this case, given Chip's position on them.
As for "not going to happen", I wouldn't be so sure.
Of course someone could violate the license but if someone produces something that looks like the COG instruction set and Propeller architecture then I suppose Parallax could sue them. Somehow, I can't imagine them doing that though.
WOW!!! I did not expect that, I don't know if it's a good thing or not though. I just hope it doesn't hurt Parallax financially.
There is only a very small overlap of projects that could 'go either way' - ie where the Chip, or a FPGA does not 'self select'. and that will be MORE than compensated by the increase in 'eco system'.
Companies will be more likely to consider investing in P1 expertise, if they have a larger design spread than a single chip.
The BEmicroCV is showing at Verical again @ $42.0350
There is also the Lattice and Altera CPLDs that could be targets for this.
This is fantastic news for us. However I remain concerned for Parallax.
Link anyone?
Who will be first with a 64KB hub RAM and 16 cogs?
Probably not me because I've only written a hundred lines of Verilog or less in my life. I'm interested to look at Chip's code though and I may try some simple modifications. It will be a while before I try anything major though.
It was like a massive headache which went on for days and then suddenly abated when things abruptly snapped into place.
We've got one simple state machine to handle shifting hub data in and out through pins and DACs. It also handles the Goertzel NCO and summation. It's good for video, fast analog output, fast pin I/O, SDRAM interfacing, and DSP.
Sounds great Is this still at 200MHz Silicon and ?? (160MHz?) on FPGA. ?
Any speed-build specs on Cyclone V devices yet ?
@David: I didn't mean in a nefarious way. The chance of that happening is fairly low, IMHO. Props are differentiated enough for that kind of thing to stick out, and whoever does it won't have the ecosystem associated with the chip.
That's us, and I sure won't support anybody doing that.
No, I meant other open code variants of the P1. I think that may well happen once people get their heads wrapped around the design. Those are a good thing. Let's say a few happen, and the community centers in on one of them. It's compelling. Parallax could manufacture it, or the author of the design could seek a license to kickstart it, or have it fabbed, whatever.
The other compelling scenario exists on a larger FPGA. Package an entire solution onto one, get a license from Parallax, and now you have a code protected, embedded Propeller, with potential extras, just the sort of extras one needs to meet requirements. Put some routines you need in ROM, ditch the stuff you don't need, encrypt, and just have the FPGA contain it all. Spiffy!
In fact, I would envision somebody offering this as a service, once the core competency is out there. If it happens that way, it's good for nearly everybody, including Parallax.
The first variant I see is a reduced ROM version. All the parts are there. Strip it to the loader only, and have SPIN loaded into high RAM, and fire it off from there. Now it's a 50K ?? Prop.
Depending on how fast a Nano can be a P1, maybe just getting a faster clock would make sense for some people too. That's super easy.
This is really cool! Parallax really does put their money where their mouth is when it comes to open source hardware/software.
Just a random thought: What if some time in the future a contest is held for best code modification (i.e. in terms of additional or upgraded feature set), and then a kickstarter campaign is held to raise funds to produce an ASIC? Of course, the ASIC would still be property of Parallax and sold/supported appropriately.
Can one of you guys please get this on Hackaday for us, as you see it?
Some of the questions you are asking will be clarified when all pages are up. The main P1 Open Source page isn't up yet - just give our team a bit of time. There's a number of links back and forth between pages. And I'm hoping that some of these pages will arrive before the forums have misinformation that sticks out in Google forever.
This state machine is not useful for tallying ADC feedback bitstreams. That is handled by the pin, itself. You configure the pin and then poll it for samples of whatever size you wanted.
The pin takes 256 clocks to gather an 8-bit sample or, generally, 2^n clocks for an n-bit sample. You can have it do 1,000 clocks for a 0..1000 result, if you want, or any other sample size. No need to stick with powers of two.
@Bill Henning: assuming an external ADC, I'd guess the max sampling rate for bursts will be the chip clock frequency or half the chip clock frequency. Bit depth, would be set by the external chip, but I'd guess up to 32-bits per capture by the shifter. Makes me tempted to design a 100Msps oscilloscope with the prop 2.
@Ken: Let's abandon this thread right now for this subject, and P2 ruminations can continue unabated.
Maybe people can delete posts. Or our moderators can just hide a few things in the interest of everybody landing in the right place. I sure don't mind. Do others? This should be solid. It's a bold move, and it needs to be clear.
Start another one in the P1 Forum, and put the text of what you do know right now, and if you've got them, the links to the release pages to appear soon. Several of us can comment there, and we can make submissions to various places. I'll do Hackaday, though somebody like OBC might have more cred there, and Slashdot for sure. Others can drop things in tip lines, and a few of us doing that today will get the word out.
I'll do Twitter, FB as well as write a few posts in places I hang out. That can get done later today.
I won't post on this thread again. Looking forward to additional chatter on the new one. IMHO, that's the best way to avoid Google sticking on the early discussion. Those links from other sites will bury whatever bits you are concerned about here, if it's not cleaned up a little in the interim.
I suggest we all use whatever post you make Ken as the basis for our submissions to various places. You can update it as the web team finalizes things.
I second Bill's suggestion below. And now I have to drive some... catch up with you guys a bit later today.
Very possible. We will first start with an Open Propeller Project for this purpose so there's simply a thread to post your work, but where it goes from there is mostly up to the community. We want to play, to facilitate, and contribute as you can see.
Comments
OBC is right, you guys are crazy!
Thank you.
@Chip: That shifter sounds awesome!
@Bill Henning: assuming an external ADC, I'd guess the max sampling rate for bursts will be the chip clock frequency or half the chip clock frequency. Bit depth, would be set by the external chip, but I'd guess up to 32-bits per capture by the shifter. Makes me tempted to design a 100Msps oscilloscope with the prop 2.
Marty
Hope this is usable with the DE2-115 board also. Given the source, it's likely usable with many moderate sized FPGAs.
I assume that you could negotiate a private license with Parallax.
I wasn't even looking for a DE0 I just stumbled upon it ;-)
As for "not going to happen", I wouldn't be so sure.
LOL,
Link anyone?
Who will be first with a 64KB hub RAM and 16 cogs?
There is only a very small overlap of projects that could 'go either way' - ie where the Chip, or a FPGA does not 'self select'. and that will be MORE than compensated by the increase in 'eco system'.
Companies will be more likely to consider investing in P1 expertise, if they have a larger design spread than a single chip.
The BEmicroCV is showing at Verical again @ $42.0350
There is also the Lattice and Altera CPLDs that could be targets for this.
Link please
Dave
Yes, there's a full P1 Verilog file for the DE2-115.
Ken Gracey
Of course you can, if needed. Such a case would be a commercial use where the developer does not want to share the Verilog.
Ken Gracey
Sounds great
Any speed-build specs on Cyclone V devices yet ?
I consider it a supplemental addition to what we offer our customers, rather than a new focus on business direction.
Ken Gracey
@David: I didn't mean in a nefarious way. The chance of that happening is fairly low, IMHO. Props are differentiated enough for that kind of thing to stick out, and whoever does it won't have the ecosystem associated with the chip.
That's us, and I sure won't support anybody doing that.
No, I meant other open code variants of the P1. I think that may well happen once people get their heads wrapped around the design. Those are a good thing. Let's say a few happen, and the community centers in on one of them. It's compelling. Parallax could manufacture it, or the author of the design could seek a license to kickstart it, or have it fabbed, whatever.
The other compelling scenario exists on a larger FPGA. Package an entire solution onto one, get a license from Parallax, and now you have a code protected, embedded Propeller, with potential extras, just the sort of extras one needs to meet requirements. Put some routines you need in ROM, ditch the stuff you don't need, encrypt, and just have the FPGA contain it all. Spiffy!
In fact, I would envision somebody offering this as a service, once the core competency is out there. If it happens that way, it's good for nearly everybody, including Parallax.
The first variant I see is a reduced ROM version.
Depending on how fast a Nano can be a P1, maybe just getting a faster clock would make sense for some people too. That's super easy.
I think it's a very smart move and proves that Parallax are indeed innovators.
The NANO has 22K LE's, or thereabouts...
Just a random thought: What if some time in the future a contest is held for best code modification (i.e. in terms of additional or upgraded feature set), and then a kickstarter campaign is held to raise funds to produce an ASIC? Of course, the ASIC would still be property of Parallax and sold/supported appropriately.
Some of the questions you are asking will be clarified when all pages are up. The main P1 Open Source page isn't up yet - just give our team a bit of time. There's a number of links back and forth between pages. And I'm hoping that some of these pages will arrive before the forums have misinformation that sticks out in Google forever.
Ken Gracey
0-100: 2Msps
0-1000: 200Ksps
0-10000: 20Ksps
0-1M:200sps
Dial-a-resolution
ON EVERY PIN!!!!
Love it!
I was actually curious about he internal pin adc's, and they sound great
Maybe people can delete posts. Or our moderators can just hide a few things in the interest of everybody landing in the right place. I sure don't mind. Do others? This should be solid. It's a bold move, and it needs to be clear.
Start another one in the P1 Forum, and put the text of what you do know right now, and if you've got them, the links to the release pages to appear soon. Several of us can comment there, and we can make submissions to various places. I'll do Hackaday, though somebody like OBC might have more cred there, and Slashdot for sure. Others can drop things in tip lines, and a few of us doing that today will get the word out.
I'll do Twitter, FB as well as write a few posts in places I hang out. That can get done later today.
I won't post on this thread again. Looking forward to additional chatter on the new one. IMHO, that's the best way to avoid Google sticking on the early discussion. Those links from other sites will bury whatever bits you are concerned about here, if it's not cleaned up a little in the interim.
I suggest we all use whatever post you make Ken as the basis for our submissions to various places. You can update it as the web team finalizes things.
I second Bill's suggestion below. And now I have to drive some... catch up with you guys a bit later today.
I know what I'll be loading onto one of my DE0's soon...
Ken, get this up on opencores.org facebook and tweet it!