I can see it being a P1 FPGA edition maybe, but what I can't understand there, is why would Ken take Chip off the P2 dev to do this P1 thing so close to P2's completion, unless it was something as quick as his P1 (as it is) FPGA image.
Ken has briefly mentioned (possibly on 2 occasions) selling 1,000 FPGA development boards. How does Parallax have a solid launch of those dev boards without some kind of an image to load them up with? Aren't they fashionably late (assuming the plan wasn't canceled)? So, a P1-based image and dev boards was the first thing that came to mind. Plus, Chip used the word "innovate" which could very well imply extending/customizing the P1, perhaps more so than designing with a new silicon variant from a fab. I wonder what's the cheapest FPGA chip that could handle a P1 image, 'cause without something reasonably inexpensive, it would seem to reduce interest. I guess the cost of such chips continues to drop. Also, Ken seems to be out of the prediction biz for new silicon when such silicon is potentially months away. Having said that, I'd love to be wrong...and have some enhanced P1's raining down on us. That would be fab-ulous! Anyway, a P1-based image could be quite interesting in the hands of you folks that know how to wrangle with it.
Ken has briefly mentioned (possibly on 2 occasions) selling 1,000 FPGA development boards. How does Parallax have a solid launch of those dev boards without some kind of an image to load them up with? Aren't they fashionably late (assuming the plan wasn't canceled)? So, a P1-based image and dev boards was the first thing that came to mind. Plus, Chip used the word "innovate" which could very well imply extending/customizing the P1, perhaps more so than designing with a new silicon variant from a fab. I wonder what's the cheapest FPGA chip that could handle a P1 image, 'cause without something reasonably inexpensive, it would seem to reduce interest. I guess the cost of such chips continues to drop. Also, Ken seems to be out of the prediction biz for new silicon when such silicon is potentially months away. Having said that, I'd love to be wrong...and have some enhanced P1's raining down on us. That would be fab-ulous! Anyway, a P1-based image could be quite interesting in the hands of you folks that know how to wrangle with it.
The DE0-Nano only costs $99 or less and it can run one of the old P2 COGs. I would guess that it could easily run several P1 COGs.
This is fun to think about anyway...
Seems the most likely thing is some kind of software tool or a FPGA tool.
Still, I can dream about a super P1 for one more day
The DE0-Nano only costs $99 or less and it can run one of the old P2 COGs. I would guess that it could easily run several P1 COGs.
Although I was thinking of the cost of the chips themselves, for P1-based work there's probably no compelling reason that the dev boards would have to be made by Parallax (although it might be good if wanting to experiment with the P2 in the future). Moreover, even if selling their own, Parallax could (continue to) sell another company's board(s), hopefully with images available. Any info about how many logic elements the P1 would take? Say in the range of 6-8,000, perhaps with some headroom for changes (the DE0-Nano has in excess of 22K)? See, I was thinking of P1 users actually wanting to manufacture around a revamped P1 design, hence the relevance of the cost of the chips (rather than dev boards), elsewise how would a P1 image (if that's what this is) "open doors"? But maybe I'm offbase thinking about FPGA chips. By the way, in checking the number of LE's in the Cyclone IV of the DE0-Nano, I came across a price of US$79 on the dev board (the "or less" that David mentioned).
There should be an award for whoever guesses this right. Maybe an automatic increase of post count or something. I wish someone could take about 10K of my post count away ... maybe that's a possible award too, LOL. There is always the possibility of free hardware ....
There should be an award for whoever guesses this right. Maybe an automatic increase of post count or something. I wish someone could take about 10K of my post count away ... maybe that's a possible award too, LOL. There is always the possibility of free hardware ....
Oh boy! An award! I'm sure I'm going to get it. Here is my guess:
What would take Chip only a couple of weeks for P1?
P1 board with FPGA on it? This is a way to bridge the gap between P1 and P2. Perhaps some verilog done to add capability to the P1 with the FPGA?
Couple that with some clever SPIN+PASM code, and maybe it's a nice system ready to handle some tasks people have been asking for.
Or, maybe it's something simple, like a RAM interface of some kind, where larger programs are more possible, not too many pins, and there is nice software support for it, maybe LMM in PASM with assembler support, kind of a HUBEX for P1.
Oh boy! An award! I'm sure I'm going to get it. Here is my guess:
A version of P1 with a Lisp interpreter in ROM!
Personally, I'd like to see a ROM-less P1 where all the ROM was replaced with SRAM (except for a tiny bootloader not in the 64KB space), but I doubt that would ever happen because mask rom is tiny compared to SRAM.
Personally, I'd like to see a ROM-less P1 where all the ROM was replaced with SRAM (except for a tiny bootloader not in the 64KB space), but I doubt that would ever happen because mask rom is tiny compared to SRAM.
Yes, that would be the best plan if it were possible to replace the ROM at all. I was just kidding about Lisp of course. I'm not clever enough to guess what Chip and Parallax are really up to!
Totally. Thought it was fun to put a guess or two out there.
One more:
Improved SPIN, capable of running code from external storage. The vast majority of commercial products are SPIN+PASM, and somebody somewhere wants a bigger program space.
Improved SPIN, capable of running code from external storage. The vast majority of commercial products are SPIN+PASM, and somebody somewhere wants a bigger program space.
I'm not a very prolific programmer but good an optimization. The other half of http://madmenwithaprop.com is a very prolific programmer but at the time of our last project was only 6 weeks or so into the language.
He would write reams of code amazing code and email it to me with the comment "MORE LONGS". I would optimize the code with SPIN and ASM idioms and send it back. This cycle went on for days and we crammed an amazing amount of functionality into 32k - we were really proud.
More longs would be amazing and may actually be doable at the compiler / toolchain level which would make Chip's involvement make a lot of sense.
Hmmm... potatohead, you may be on to something.
My money is on a single-cog singing voice synth. Why? because it's fun (and Chip has a history of sound synth).
However, this is what we know.
0) I don't believe in coincidences and Wednesday / Thursday is a very specific date.
1) There are at least 3 other threads referencing this date.
2) 1o57's tweet warning people not to get dizzy while SPINning.
I'm currently on a plane to this Mecca so will hopefully be at ground-zero when the announcements hit. I have 95% of my electronics gear with me (Logic Analyzer, Oscilloscope, SMT station, random "cool" components to integrate.
Whatever the announcements are, whatever the product is, whatever the badge looks like - I'm ready to do everything I can to build something amazing with it in the days that I'm there.
Totally. Thought it was fun to put a guess or two out there.
One more:
Improved SPIN, capable of running code from external storage. The vast majority of commercial products are SPIN+PASM, and somebody somewhere wants a bigger program space.
I thought about working on a Spin compiler but then I read some threads (a long time ago) talking about how people demanded that BST generate identical code to the Propeller Tool. The same is true of OpenSpin. I suspect that anything that deviates at all from the reference implementation would not be widely accepted. In particular, generating identical code puts too much of a constraint on compiler design.
Originally I said it would be either some software for the P1 (as in tools) or more info on the P1.
I firmly believe it will not be a new P1 but it was fun to play with ideas.
But here is my latest prediction...
A much more detailed specification of the counters/vga circuitry. Perhaps a logic block diagram. Perhaps some programs exploiting some features.
Some have done some pretty amazing things with these features. But, there is so much we don't know about these parts of the P1.
I believe there is plenty yet to explore here.
Whatever the announcements are, whatever the product is, whatever the badge looks like - I'm ready to do everything I can to build something amazing with it in the days that I'm there.
Me too, Redvers! I'll certainly see ya at the 'CON and Chip will be there too.
But could there be more news this week? Nah, there's nothing to discuss. . .nothing to see, everybody move along.
By the way, in checking the number of LE's in the Cyclone IV of the DE0-Nano, I came across a price of US$79 on the dev board (the "or less" that David mentioned).
When I bought mine it was $99. I knew they had lowered the price but I couldn't remember by how much. That's why I said "or less". I thought it looked like a nice board to play with FPGA processor designs. The Chip came out with the P2 bit file and that's what I ended up using it for. I never got back to processor design.
I like to think BIG, or in this case small. I think the P2 was completed in the "smaller" (28nm) manufacturing process, and first productions chips are back. The last six months was a smoke screen.
Comments
Ken has briefly mentioned (possibly on 2 occasions) selling 1,000 FPGA development boards. How does Parallax have a solid launch of those dev boards without some kind of an image to load them up with? Aren't they fashionably late (assuming the plan wasn't canceled)? So, a P1-based image and dev boards was the first thing that came to mind. Plus, Chip used the word "innovate" which could very well imply extending/customizing the P1, perhaps more so than designing with a new silicon variant from a fab. I wonder what's the cheapest FPGA chip that could handle a P1 image, 'cause without something reasonably inexpensive, it would seem to reduce interest. I guess the cost of such chips continues to drop. Also, Ken seems to be out of the prediction biz for new silicon when such silicon is potentially months away. Having said that, I'd love to be wrong...and have some enhanced P1's raining down on us. That would be fab-ulous! Anyway, a P1-based image could be quite interesting in the hands of you folks that know how to wrangle with it.
Seems the most likely thing is some kind of software tool or a FPGA tool.
Still, I can dream about a super P1 for one more day
That's an interesting statement however, some of you are doing way more chatting than innovating so it may not matter to you. LOL
I'll take a guess that it's something to do with FPGA's and a prop1 :cool:
Although I was thinking of the cost of the chips themselves, for P1-based work there's probably no compelling reason that the dev boards would have to be made by Parallax (although it might be good if wanting to experiment with the P2 in the future). Moreover, even if selling their own, Parallax could (continue to) sell another company's board(s), hopefully with images available. Any info about how many logic elements the P1 would take? Say in the range of 6-8,000, perhaps with some headroom for changes (the DE0-Nano has in excess of 22K)? See, I was thinking of P1 users actually wanting to manufacture around a revamped P1 design, hence the relevance of the cost of the chips (rather than dev boards), elsewise how would a P1 image (if that's what this is) "open doors"? But maybe I'm offbase thinking about FPGA chips. By the way, in checking the number of LE's in the Cyclone IV of the DE0-Nano, I came across a price of US$79 on the dev board (the "or less" that David mentioned).
Mr. Lawrence: I have asked you before and now I'm kindly asking you again: please stopping tapping into my webcam and watching me!
A version of P1 with a Lisp interpreter in ROM!
P1 board with FPGA on it? This is a way to bridge the gap between P1 and P2. Perhaps some verilog done to add capability to the P1 with the FPGA?
Couple that with some clever SPIN+PASM code, and maybe it's a nice system ready to handle some tasks people have been asking for.
Or, maybe it's something simple, like a RAM interface of some kind, where larger programs are more possible, not too many pins, and there is nice software support for it, maybe LMM in PASM with assembler support, kind of a HUBEX for P1.
Personally, I'd like to see a ROM-less P1 where all the ROM was replaced with SRAM (except for a tiny bootloader not in the 64KB space), but I doubt that would ever happen because mask rom is tiny compared to SRAM.
One more:
Improved SPIN, capable of running code from external storage. The vast majority of commercial products are SPIN+PASM, and somebody somewhere wants a bigger program space.
I'm not a very prolific programmer but good an optimization. The other half of http://madmenwithaprop.com is a very prolific programmer but at the time of our last project was only 6 weeks or so into the language.
He would write reams of code amazing code and email it to me with the comment "MORE LONGS". I would optimize the code with SPIN and ASM idioms and send it back. This cycle went on for days and we crammed an amazing amount of functionality into 32k - we were really proud.
More longs would be amazing and may actually be doable at the compiler / toolchain level which would make Chip's involvement make a lot of sense.
Hmmm... potatohead, you may be on to something.
My money is on a single-cog singing voice synth. Why? because it's fun (and Chip has a history of sound synth).
However, this is what we know.
0) I don't believe in coincidences and Wednesday / Thursday is a very specific date.
1) There are at least 3 other threads referencing this date.
2) 1o57's tweet warning people not to get dizzy while SPINning.
I'm currently on a plane to this Mecca so will hopefully be at ground-zero when the announcements hit. I have 95% of my electronics gear with me (Logic Analyzer, Oscilloscope, SMT station, random "cool" components to integrate.
Whatever the announcements are, whatever the product is, whatever the badge looks like - I'm ready to do everything I can to build something amazing with it in the days that I'm there.
I firmly believe it will not be a new P1 but it was fun to play with ideas.
But here is my latest prediction...
A much more detailed specification of the counters/vga circuitry. Perhaps a logic block diagram. Perhaps some programs exploiting some features.
Some have done some pretty amazing things with these features. But, there is so much we don't know about these parts of the P1.
I believe there is plenty yet to explore here.
This is like the iPhone 6 speculation
Me too, Redvers! I'll certainly see ya at the 'CON and Chip will be there too.
But could there be more news this week? Nah, there's nothing to discuss. . .nothing to see, everybody move along.
Ken Gracey
I like to think BIG, or in this case small. I think the P2 was completed in the "smaller" (28nm) manufacturing process, and first productions chips are back. The last six months was a smoke screen.
Don't you just wish !!
Yes! We wish for the same thing, but I'm sure this isn't going to happen
Ken Gracey
Could it be a defcon badge with extendable fpga based P1 on board?
because this is a FPGA thread, many are keen to morph fpga into the mix, but Ken has also said things here
http://forums.parallax.com/showthread.php/156640-Prop-2-Paradox?p=1283206&viewfull=1#post1283206
- which sounds less like FPGA.-based.
OldBitCollector already knows about it and he told Ken that he thinks we are crazy.
If there is not at least one person saying you are crazy, it means you are not doing enough pushing of the envelope !!
ok it's already 2;15 am my time so lets have it.
We have to wait for the web people to come into the office in the morning to put up some new pages. It could be Thursday in some parts by then.