I'm not sure if document size is the issue in this case, but spliting it up might be a good idea.
I was hoping to make a template for the new instruction description format and populate it very quickly using VBA, but pasting the tables back from Word 2010 doesn't get the formatting correct.
I tried saving the Google Docs document to HTML and opening the HTML in Chrome, then cutting and pasting from that document back to Google Docs, the formatting gets messed up that way as well.
Other than plain text Google Docs seems to like to only cut/paste with itself...
If I have time this weekend I though I might see if making tables using very simple HTML with inline styles might work as a way to build content and then paste it in.
I loath manual typing when it's something where I should be able to let the computer do the work.
Could part of the problem be that our document has become too large for google to work efficiently???
Maybe we need to split the document???
I was thinking it wouldn't hurt to split it, at least move the detailed assembly language reference to another section. The table of contents would not be so cluttered then and the the assembly section can have it's own heading styles. I use Chrome for Google docs but sometimes as the docs become sluggish I just need to restart the program, so Google docs is certainly not perfect, there are limitations but it provides that interactive environment where we can see, comment, edit, even as we type.
I'm not sure if document size is the issue in this case, but spliting it up might be a good idea.
I was hoping to make a template for the new instruction description format and populate it very quickly using VBA, but pasting the tables back from Word 2010 doesn't get the formatting correct.
I tried saving the Google Docs document to HTML and opening the HTML in Chrome, then cutting and pasting from that document back to Google Docs, the formatting gets messed up that way as well.
Other than plain text Google Docs seems to like to only cut/paste with itself...
If I have time this weekend I though I might see if making tables using very simple HTML with inline styles might work as a way to build content and then paste it in.
I loath manual typing when it's something where I should be able to let the computer do the work.
C.W.
I agree - I did the reformatting and dividing into columns using Excel formulae, and then copying the resultant values.
I think the new instruction format you have devised should also be a separate document, so maybe again, do it offline. If anyone volunteers to help you can send them the template in word and discuss what instructions they will do.
It is my private version of Instructions PDF.
Only first 2 pages are end coloured as I still work on base text to it so no need every time colour Test.pdf
Look in attachment
Ps. For my eyes it is simpler to distingush what is important
I agree - I did the reformatting and dividing into columns using Excel formulae, and then copying the resultant values.
I think the new instruction format you have devised should also be a separate document, so maybe again, do it offline. If anyone volunteers to help you can send them the template in word and discuss what instructions they will do.
Here is the latest spreadsheet with the P2 instruction summary. There are a few that still need a proper description and the Z/C/R?/Clocks/Delayed are not correct yet. ANd of course I have not verified the bit patterns that I copied. However, it is getting there as I have spent quite a bit of time on it.
Here is the latest spreadsheet with the P2 instruction summary. There are a few that still need a proper description and the Z/C/R?/Clocks/Delayed are not correct yet. ANd of course I have not verified the bit patterns that I copied. However, it is getting there as I have spent quite a bit of time on it.
Thanks Peter. For now it is easier to edit in Excel as there is still a bit to do.
BTW I noticed it did leading zero supression.
I opened up the xlsx spreadsheet in LibreOffice on my Linux computer which must do something to the zeros I guess, at least it has conversion utilities from one format to another. The whole world has not yet been assimilated by the proprietary MSO with their free 60 day trial.
EDIT: Looks like a Google docs thing, there is no where I can tell it to keep leading zeros so I just went and put a % sign in front plus the zeros so it would always treat it as text.
In another thread (I can't find it right now), Chip said that he got REPS/REPD to work with multi-tasking. But only a single task can use it at a time.
In another thread (I can't find it right now), Chip said that he got REPS/REPD to work with multi-tasking. But only a single task can use it at a time.
From Chip "I got the REPS/REPD working with multitasking now. Any task can use it, but only one task at a time."
Bean
Thanks Bean, well that makes sense I guess and we can work that into the docs, especially the assembler reference doc which looks like Seairth is taking a break from at the moment but hopefully he will come back to continue chipping away at it soon
If anyone feels competent to add a few more instructions in the same style then have a practice in the training doc perhaps and if it looks good we can include it in the main document.
The only thing new in it is the field mover description:
BYTE/WORD FIELD MOVER
---------------------
Each cog has a field mover that can move a byteorwordfrom any field in S into any field in D. To use
the field mover, you must first configure it using SETF. Then, you can use MOVF to perform the moves.
SETF uses a 9-bit value to configure the field mover:
%W_DDdd_SSss
W = 1 for word mode, 0 for byte mode
DD = D field mode: %00 = D field pointer stays same after MOVF
%01 = D field pointer stays same after MOVF, D rotates left by byte/word%10 = D field pointer increments after MOVF
%11 = D field pointer decrements after MOVF
dd = D field pointer: %00 = byte0 / word0%01 = byte1 / word0%10 = byte2 / word1%11 = byte3 / word1
SS = S field mode: %0x = S field pointer stays same after MOVF
%10 = S field pointer increments after MOVF
%11 = S field pointer decrements after MOVF
ss = S field pointer: %00 = byte0 / word0%01 = byte1 / word0%10 = byte2 / word1%11 = byte3 / word1
On cog startup, SETF is initialized to%0_0100_0000, so that MOVF will rotate D left by 8 bits and
then fill the bottom byte with the lower byte in S.
instructions clocks
-------------------------------------------------------------------------------------------------
0000110001 CCCC DDDDDDDDD 011001010 SETF D 'Configure field mover with D 10000110011 CCCC nnnnnnnnn 011001010 SETF #n 'Configure field mover with 0..511 10001010000 CCCC DDDDDDDDD SSSSSSSSS MOVF D,S 'Move field from S into D 10001010001 CCCC DDDDDDDDD nnnnnnnnn MOVF D,#n 'Move field from 0..511 into D 1
-------------------------------------------------------------------------------------------------
The only thing new in it is the field mover description:
BYTE/WORD FIELD MOVER
---------------------
Each cog has a field mover that can move a byteorwordfrom any field in S into any field in D. To use
the field mover, you must first configure it using SETF. Then, you can use MOVF to perform the moves.
SETF uses a 9-bit value to configure the field mover:
%W_DDdd_SSss
W = 1 for word mode, 0 for byte mode
DD = D field mode: %00 = D field pointer stays same after MOVF
%01 = D field pointer stays same after MOVF, D rotates left by byte/word%10 = D field pointer increments after MOVF
%11 = D field pointer decrements after MOVF
dd = D field pointer: %00 = byte0 / word0%01 = byte1 / word0%10 = byte2 / word1%11 = byte3 / word1
SS = S field mode: %0x = S field pointer stays same after MOVF
%10 = S field pointer increments after MOVF
%11 = S field pointer decrements after MOVF
ss = S field pointer: %00 = byte0 / word0%01 = byte1 / word0%10 = byte2 / word1%11 = byte3 / word1
On cog startup, SETF is initialized to%0_0100_0000, so that MOVF will rotate D left by 8 bits and
then fill the bottom byte with the lower byte in S.
instructions clocks
-------------------------------------------------------------------------------------------------
0000110001 CCCC DDDDDDDDD 011001010 SETF D 'Configure field mover with D 10000110011 CCCC nnnnnnnnn 011001010 SETF #n 'Configure field mover with 0..511 10001010000 CCCC DDDDDDDDD SSSSSSSSS MOVF D,S 'Move field from S into D 10001010001 CCCC DDDDDDDDD nnnnnnnnn MOVF D,#n 'Move field from 0..511 into D 1
-------------------------------------------------------------------------------------------------
The only thing new in it is the field mover description:
BYTE/WORD FIELD MOVER
---------------------
Each cog has a field mover that can move a byteorwordfrom any field in S into any field in D. To use
the field mover, you must first configure it using SETF. Then, you can use MOVF to perform the moves.
SETF uses a 9-bit value to configure the field mover:
%W_DDdd_SSss
W = 1 for word mode, 0 for byte mode
DD = D field mode: %00 = D field pointer stays same after MOVF
%01 = D field pointer stays same after MOVF, D rotates left by byte/word%10 = D field pointer increments after MOVF
%11 = D field pointer decrements after MOVF
dd = D field pointer: %00 = byte0 / word0%01 = byte1 / word0%10 = byte2 / word1%11 = byte3 / word1
SS = S field mode: %0x = S field pointer stays same after MOVF
%10 = S field pointer increments after MOVF
%11 = S field pointer decrements after MOVF
ss = S field pointer: %00 = byte0 / word0%01 = byte1 / word0%10 = byte2 / word1%11 = byte3 / word1
On cog startup, SETF is initialized to%0_0100_0000, so that MOVF will rotate D left by 8 bits and
then fill the bottom byte with the lower byte in S.
instructions clocks
-------------------------------------------------------------------------------------------------
0000110001 CCCC DDDDDDDDD 011001010 SETF D 'Configure field mover with D 10000110011 CCCC nnnnnnnnn 011001010 SETF #n 'Configure field mover with 0..511 10001010000 CCCC DDDDDDDDD SSSSSSSSS MOVF D,S 'Move field from S into D 10001010001 CCCC DDDDDDDDD nnnnnnnnn MOVF D,#n 'Move field from 0..511 into D 1
-------------------------------------------------------------------------------------------------
I've updated the document and put the configurations bits and instructions into tables. Here's a forum preview which looks similar to the document except the lines don't seem to show up.
Byte/Word Field Mover
<forum> Each cog has a field mover that can move a byte or word from any field in S into any field in D. To use the field mover, you must first configure it using SETF. Then, you can use MOVF to perform the moves.
SETF uses a 9-bit value %W_DDdd_SSss to configure the field mover: Table: Field mover configuration bits
W word/byte DD D field mode dd D field pointer SS S field mode ss S field pointer
0 byte mode %00 D field pointer stays same after MOVF %00 byte 0 / word 0 %00 S field pointer stays same after MOVF %00 byte 0 / word 0
1 word mode %01 D field pointer stays same after MOVF, D rotates left by byte/word %01 byte 1 / word 0 %01 S field pointer stays same after MOVF %01 byte 1 / word 0
%10 byte 2 / word 1 %10 S field pointer increments after MOVF %10 byte 2 / word 1
%11 byte 3 / word 1 %11 S field pointer deccrements after MOVF %11 byte 3 / word 1
On cog startup, SETF is initialized to %0_0100_0000, so that MOVF will rotate D left by 8 bits and then fill the bottom byte with the lower byte in S.
Yes, these registers are not part of the cog memory registers but hidden like SPA and PTR etc that are only accessed via their special instruction.
BTW Chip, well thought out relegating all these registers plus the new ones to special instructions which frees up the precious cog memory.
Yes, these registers are not part of the cog memory registers but hidden like SPA and PTR etc that are only accessed via their special instruction.
BTW Chip, well thought out relegating all these registers plus the new ones to special instructions which frees up the precious cog memory.
It became apparent early on that if every special function register were mapped into register space, they would eat way too many registers. Only the pin registers have crucial need to be addressable.
INSTRUCTION-BLOCK REPEATING
---------------------------
Each cog has an instruction-block repeater that can variably repeat up to64 instructions without
any clock-cycle overhead.
REPD and REPS are used to initiate block repeats. These instructions specify how many times the
trailing instruction block will be executed and how many instructions are in the block:
REPD #i - execute 1..64 instructions infinitely, requires 3 spacer instructions *
REPD D,#i - execute 1..64 instructions D+1 times, requires 3 spacer instructions *
REPD #n,#i - execute 1..64 instructions 1..512 times, requires 3 spacer instructions *
REPS #n,#i - execute 1..64 instructions 1..16384 times, requires 1 spacer instruction *
REPS differs from REPD by executing at the 2nd stage of the pipeline, instead of the 4th. By
executing two stages early, it needs only one spacer instruction *. Because of its earliness,
no conditional execution is possible, so it always executes, allowing the CCCC bits to be
repurposed, along with Z, to provide a 14-bit constant for the repeat count.
The instruction-block repeater will quit repeating the block if a branch instruction executes
within the block. This rule does not currently apply to a JMPTASK which affects the task using the
repeater - this will be fixed at the earliest opportunity.
* Spacer instructions are required in 1-task applications to allow the pipeline to prime before
repeating can commence. If REPD is used by a task that uses no more than every 4th time slot, no
spacers are needed, as three intervening instructions will be provided by the other task(s). If
REPS is used by a task that uses no more than every 2nd time slot, no spacers are needed.
Example (1-task):
REPD D,#1'execute 1 instruction D+1 timesNOP'3 spacer instructions needed (could do something useful)NOPNOP
NOTP #0'toggle P0, block repeats every 1 clock
Example (1-task):
REPS #20_000,#4'execute 4 instructions 20,000 timesNOP'1 spacer instruction needed (make the most of it)
NOTP #0'toggle P0
NOTP #1'toggle P1
NOTP #2'toggle P2
NOTP #3'toggle P3, block repeats every 4 clocks
Example (4-task, SETTASK #%%3210 timing):
task0 REPD #1'task0 will own the block repeater (no need for spacers)
NOTP #0'toggle P0 every 4 clocks
task1 NOTP #1'toggle P1 every 8 clocksJMP #task1
task2 NOTP #2'toggle P2 every 8 clocksJMP #task2
task3 NOTP #3'toggle P3 every 8 clocksJMP #task3
instructions (iiiiii = #i-1, nnnnnnnnn/n___nnnn_nnnnnnnnn = #n-1) clocks
-------------------------------------------------------------------------------------------------
0000110001 CCCC 111111111 001iiiiii REPD #i 'execute 1..64 inst's infintely 10000110001 CCCC nnnnnnnnn 001iiiiii REPD D,#i 'execute 1..64 inst's D+1 times 10000110011 CCCC nnnnnnnnn 001iiiiii REPD #n,#i 'execute 1..64 inst's 1x..512x 1000011 n11 1 nnnn nnnnnnnnn 001iiiiii REPS #n,#i 'execute 1..64 inst's 1x..16384x 1
-------------------------------------------------------------------------------------------------
Note that the %iiiiii field represents 1..64 instructions, not the encoded 0..63. The %nnnnnnnnn/
%n___nnnn_nnnnnnnnn fields are +1-based, too.
At this time, 'REPD #i' must be typed as 'REPD $1FF,#i', since the assembler in PNUT isn't handling this shorthand syntax yet. I'll have it added in a day, or two.
Thanks Chip, the REP instruction was one piece of information that I was looking for a bit more information on myself. So slowly but inexorably the documentation progresses as I proceed to add this bit of information as well. I would rather spend time with my DE2 testing my code but alas, there is only so much time in a day. Now if only I could employ the REP instruction to get through some things faster....
Comments
Maybe we need to split the document???
I'm not sure if document size is the issue in this case, but spliting it up might be a good idea.
I was hoping to make a template for the new instruction description format and populate it very quickly using VBA, but pasting the tables back from Word 2010 doesn't get the formatting correct.
I tried saving the Google Docs document to HTML and opening the HTML in Chrome, then cutting and pasting from that document back to Google Docs, the formatting gets messed up that way as well.
Other than plain text Google Docs seems to like to only cut/paste with itself...
If I have time this weekend I though I might see if making tables using very simple HTML with inline styles might work as a way to build content and then paste it in.
I loath manual typing when it's something where I should be able to let the computer do the work.
C.W.
I think the new instruction format you have devised should also be a separate document, so maybe again, do it offline. If anyone volunteers to help you can send them the template in word and discuss what instructions they will do.
It is my private version of Instructions PDF.
Only first 2 pages are end coloured as I still work on base text to it so no need every time colour Test.pdf
Look in attachment
Ps. For my eyes it is simpler to distingush what is important
The main section still has all the other assembler instruction tables.
P2_Instructions(5).zip
In section
[h=3]Table: Pin Definitions.[/h]
PWR name
shall be
Core PWR
BTW I noticed it did leading zero supression.
EDIT: Looks like a Google docs thing, there is no where I can tell it to keep leading zeros so I just went and put a % sign in front plus the zeros so it would always treat it as text.
P.S. Found it ! Post #150 in this thread http://forums.parallax.com/showthread.php?144478-LMM2-Propeller-2-LMM-experiments-(50-80-LMM2-MIPS-160MHz)/page8
From Chip "I got the REPS/REPD working with multitasking now. Any task can use it, but only one task at a time."
Bean
If anyone feels competent to add a few more instructions in the same style then have a practice in the training doc perhaps and if it looks good we can include it in the main document.
Prop2_Docs.txt
The only thing new in it is the field mover description:
BYTE/WORD FIELD MOVER --------------------- Each cog has a field mover that can move a byte or word from any field in S into any field in D. To use the field mover, you must first configure it using SETF. Then, you can use MOVF to perform the moves. SETF uses a 9-bit value to configure the field mover: %W_DDdd_SSss W = 1 for word mode, 0 for byte mode DD = D field mode: %00 = D field pointer stays same after MOVF %01 = D field pointer stays same after MOVF, D rotates left by byte/word %10 = D field pointer increments after MOVF %11 = D field pointer decrements after MOVF dd = D field pointer: %00 = byte 0 / word 0 %01 = byte 1 / word 0 %10 = byte 2 / word 1 %11 = byte 3 / word 1 SS = S field mode: %0x = S field pointer stays same after MOVF %10 = S field pointer increments after MOVF %11 = S field pointer decrements after MOVF ss = S field pointer: %00 = byte 0 / word 0 %01 = byte 1 / word 0 %10 = byte 2 / word 1 %11 = byte 3 / word 1 On cog startup, SETF is initialized to %0_0100_0000, so that MOVF will rotate D left by 8 bits and then fill the bottom byte with the lower byte in S. instructions clocks ------------------------------------------------------------------------------------------------- 000011 000 1 CCCC DDDDDDDDD 011001010 SETF D 'Configure field mover with D 1 000011 001 1 CCCC nnnnnnnnn 011001010 SETF #n 'Configure field mover with 0..511 1 000101 000 0 CCCC DDDDDDDDD SSSSSSSSS MOVF D,S 'Move field from S into D 1 000101 000 1 CCCC DDDDDDDDD nnnnnnnnn MOVF D,#n 'Move field from 0..511 into D 1 -------------------------------------------------------------------------------------------------
Exactly what I needed for an experiment tomorrow - MUCH appreciated.
Thanks for that instructions
BTW, does this mean that each cog has a field pointer register as well that I can include in the diagram?
P2_Instructions(6).zip
Every cog has its own SETF/MOVF mechanism.
Byte/Word Field Mover
<forum>
Each cog has a field mover that can move a byte or word from any field in S into any field in D. To use the field mover, you must first configure it using SETF. Then, you can use MOVF to perform the moves.
SETF uses a 9-bit value %W_DDdd_SSss to configure the field mover:
Table: Field mover configuration bits
W
word/byte
DD
D field mode
dd
D field pointer
SS
S field mode
ss
S field pointer
0
byte mode
%00
D field pointer stays same after MOVF
%00
byte 0 / word 0
%00
S field pointer stays same after MOVF
%00
byte 0 / word 0
1
word mode
%01
D field pointer stays same after MOVF,
D rotates left by byte/word
%01
byte 1 / word 0
%01
S field pointer stays same after MOVF
%01
byte 1 / word 0
%10
byte 2 / word 1
%10
S field pointer increments after MOVF
%10
byte 2 / word 1
%11
byte 3 / word 1
%11
S field pointer deccrements after MOVF
%11
byte 3 / word 1
On cog startup, SETF is initialized to %0_0100_0000, so that MOVF will rotate D left by 8 bits and then fill the bottom byte with the lower byte in S.
Table: Byte/Word Field Mover Instructions
Machine Code
Mnemonic
Operand
Operation
Clocks
00011 000 1 CCCC DDDDDDDDD 011001010
SETF
Configure field mover with D
1
000011 001 1 CCCC nnnnnnnnn 011001010
SETF
Configure field mover with 0..511
1
000101 000 0 CCCC DDDDDDDDD SSSSSSSSS
MOVF
Move field from S into D
1
000101 000 1 CCCC DDDDDDDDD nnnnnnnnn
MOVF
Move field from 0..511 into D
1
The only way to set them is via SETF. MOVF might inc or dec either pointer, depending on what was set up with SETF.
BTW Chip, well thought out relegating all these registers plus the new ones to special instructions which frees up the precious cog memory.
It became apparent early on that if every special function register were mapped into register space, they would eat way too many registers. Only the pin registers have crucial need to be addressable.
Prop2_Docs.txt
Here's the new part:
INSTRUCTION-BLOCK REPEATING --------------------------- Each cog has an instruction-block repeater that can variably repeat up to 64 instructions without any clock-cycle overhead. REPD and REPS are used to initiate block repeats. These instructions specify how many times the trailing instruction block will be executed and how many instructions are in the block: REPD #i - execute 1..64 instructions infinitely, requires 3 spacer instructions * REPD D,#i - execute 1..64 instructions D+1 times, requires 3 spacer instructions * REPD #n,#i - execute 1..64 instructions 1..512 times, requires 3 spacer instructions * REPS #n,#i - execute 1..64 instructions 1..16384 times, requires 1 spacer instruction * REPS differs from REPD by executing at the 2nd stage of the pipeline, instead of the 4th. By executing two stages early, it needs only one spacer instruction *. Because of its earliness, no conditional execution is possible, so it always executes, allowing the CCCC bits to be repurposed, along with Z, to provide a 14-bit constant for the repeat count. The instruction-block repeater will quit repeating the block if a branch instruction executes within the block. This rule does not currently apply to a JMPTASK which affects the task using the repeater - this will be fixed at the earliest opportunity. * Spacer instructions are required in 1-task applications to allow the pipeline to prime before repeating can commence. If REPD is used by a task that uses no more than every 4th time slot, no spacers are needed, as three intervening instructions will be provided by the other task(s). If REPS is used by a task that uses no more than every 2nd time slot, no spacers are needed. Example (1-task): REPD D,#1 'execute 1 instruction D+1 times NOP '3 spacer instructions needed (could do something useful) NOP NOP NOTP #0 'toggle P0, block repeats every 1 clock Example (1-task): REPS #20_000,#4 'execute 4 instructions 20,000 times NOP '1 spacer instruction needed (make the most of it) NOTP #0 'toggle P0 NOTP #1 'toggle P1 NOTP #2 'toggle P2 NOTP #3 'toggle P3, block repeats every 4 clocks Example (4-task, SETTASK #%%3210 timing): task0 REPD #1 'task0 will own the block repeater (no need for spacers) NOTP #0 'toggle P0 every 4 clocks task1 NOTP #1 'toggle P1 every 8 clocks JMP #task1 task2 NOTP #2 'toggle P2 every 8 clocks JMP #task2 task3 NOTP #3 'toggle P3 every 8 clocks JMP #task3 instructions (iiiiii = #i-1, nnnnnnnnn/n___nnnn_nnnnnnnnn = #n-1) clocks ------------------------------------------------------------------------------------------------- 000011 000 1 CCCC 111111111 001iiiiii REPD #i 'execute 1..64 inst's infintely 1 000011 000 1 CCCC nnnnnnnnn 001iiiiii REPD D,#i 'execute 1..64 inst's D+1 times 1 000011 001 1 CCCC nnnnnnnnn 001iiiiii REPD #n,#i 'execute 1..64 inst's 1x..512x 1 000011 n11 1 nnnn nnnnnnnnn 001iiiiii REPS #n,#i 'execute 1..64 inst's 1x..16384x 1 ------------------------------------------------------------------------------------------------- Note that the %iiiiii field represents 1..64 instructions, not the encoded 0..63. The %nnnnnnnnn/ %n___nnnn_nnnnnnnnn fields are +1-based, too.
At this time, 'REPD #i' must be typed as 'REPD $1FF,#i', since the assembler in PNUT isn't handling this shorthand syntax yet. I'll have it added in a day, or two.
See http://forums.parallax.com/showthread.php?144478-LMM2-Propeller-2-LMM-experiments-(50-80-LMM2-MIPS-160MHz)&p=1150320&viewfull=1#post1150320
BTW what is the op code bits for SETCOG? I cannot find it in the google docs.
Here's the current instruction set:
instruction mnem operand ------------------------------------------------------------------------------------------------- 000000 ZC0 I CCCC DDDDDDDDD SUPIIIIII WRBYTE D,S/PTR (waits for hub) 000000 Z01 I CCCC DDDDDDDDD SUPIIIIII RDBYTE D,S/PTR (waits for hub) 000000 Z11 I CCCC DDDDDDDDD SUPIIIIII RDBYTEC D,S/PTR (waits for hub if cache miss) 000001 ZC0 I CCCC DDDDDDDDD SUPIIIIII WRWORD D,S/PTR (waits for hub) 000001 Z01 I CCCC DDDDDDDDD SUPIIIIII RDWORD D,S/PTR (waits for hub) 000001 Z11 I CCCC DDDDDDDDD SUPIIIIII RDWORDC D,S/PTR (waits for hub if cache miss) 000010 ZC0 I CCCC DDDDDDDDD SUPIIIIII WRLONG D,S/PTR (waits for hub) 000010 Z01 I CCCC DDDDDDDDD SUPIIIIII RDLONG D,S/PTR (waits for hub) 000010 Z11 I CCCC DDDDDDDDD SUPIIIIII RDLONGC D,S/PTR (waits for hub if cache miss) 000011 ZCR 0 CCCC DDDDDDDDD SSSSSSSSS COGINIT D,S (waits for hub) 000011 ZCR 1 CCCC DDDDDDDDD 000000000 CLKSET D (waits for hub) 000011 ZCR 1 CCCC DDDDDDDDD 000000001 COGID D (waits for hub) 000011 ZCR 1 CCCC DDDDDDDDD 000000010 ( COGINIT D ) (waits for hub) 000011 ZCR 1 CCCC DDDDDDDDD 000000011 COGSTOP D (waits for hub) 000011 ZCR 1 CCCC DDDDDDDDD 000000100 LOCKNEW D (waits for hub) 000011 ZCR 1 CCCC DDDDDDDDD 000000101 LOCKRET D (waits for hub) 000011 ZCR 1 CCCC DDDDDDDDD 000000110 LOCKSET D (waits for hub) 000011 ZCR 1 CCCC DDDDDDDDD 000000111 LOCKCLR D (waits for hub) 000011 ZCR 1 CCCC 000000000 000001000 CACHEX 000011 ZCR 1 CCCC 000000001 000001000 CLRACCA 000011 ZCR 1 CCCC 000000010 000001000 CLRACCB 000011 ZCR 1 CCCC 000000011 000001000 CLRACCS 000011 ZCR 1 CCCC 000000101 000001000 FITACCA (waits for mac) 000011 ZCR 1 CCCC 000000110 000001000 FITACCB (waits for mac) 000011 ZCR 1 CCCC 000000111 000001000 FITACCS (waits for mac) 000011 ZC0 1 CCCC DDDDDDDDD 000001001 SNDSER D (waits for tx if !wc) 000011 ZC1 1 CCCC DDDDDDDDD 000001001 RCVSER D (waits for rx if !wc) 000011 ZCR 1 CCCC DDDDDDDDD 000001010 PUSHZC D 000011 ZCR 1 CCCC DDDDDDDDD 000001011 POPZC D 000011 ZCR 1 CCCC DDDDDDDDD 000001100 SUBCNT D (subtracts D from cnt[31:0], then cntl if same thread) 000011 ZC0 1 CCCC DDDDDDDDD 000001101 PASSCNT D (loops if (cnt[31:0] - D) msb set) 000011 ZC1 1 CCCC DDDDDDDDD 000001101 GETCNT D (gets cnt[31:0], then cntl if same thread) 000011 ZCR 1 CCCC DDDDDDDDD 000001110 GETACCA D (gets acca[31:0], then acca[63:32], waits for mac) 000011 ZCR 1 CCCC DDDDDDDDD 000001111 GETACCB D (gets accb[31:0], then accb[63:32], waits for mac) 000011 ZCR 1 CCCC DDDDDDDDD 000010000 GETLFSR D 000011 ZCR 1 CCCC DDDDDDDDD 000010001 GETTOPS D (GETTOPS wc,nr = POLVID wc) 000011 ZCR 1 CCCC DDDDDDDDD 000010010 GETPTRA D 000011 ZCR 1 CCCC DDDDDDDDD 000010011 GETPTRB D 000011 ZCR 1 CCCC DDDDDDDDD 000010100 GETPIX D (waits two clocks) 000011 ZCR 1 CCCC DDDDDDDDD 000010101 GETSPD D 000011 ZCR 1 CCCC DDDDDDDDD 000010110 GETSPA D 000011 ZCR 1 CCCC DDDDDDDDD 000010111 GETSPB D 000011 ZCR 1 CCCC DDDDDDDDD 000011000 POPAR D 000011 ZCR 1 CCCC DDDDDDDDD 000011001 POPBR D 000011 ZCR 1 CCCC DDDDDDDDD 000011010 POPA D 000011 ZCR 1 CCCC DDDDDDDDD 000011011 POPB D 000011 ZCR 1 CCCC 000000000 000011100 RETA 000011 ZCR 1 CCCC 000000000 000011101 RETB 000011 ZCR 1 CCCC 000000000 000011110 RETAD 000011 ZCR 1 CCCC 000000000 000011111 RETBD 000011 ZCR 1 CCCC DDDDDDDDD 000100000 DECOD2 D 000011 ZCR 1 CCCC DDDDDDDDD 000100001 DECOD3 D 000011 ZCR 1 CCCC DDDDDDDDD 000100010 DECOD4 D 000011 ZCR 1 CCCC DDDDDDDDD 000100011 DECOD5 D 000011 ZCR 1 CCCC DDDDDDDDD 000100100 BLMASK D 000011 ZCR 1 CCCC DDDDDDDDD 000100101 NOT D 000011 ZCR 1 CCCC DDDDDDDDD 000100110 ONECNT D (waits one clock) 000011 ZCR 1 CCCC DDDDDDDDD 000100111 ZERCNT D (waits one clock) 000011 ZCR 1 CCCC DDDDDDDDD 000101000 INCPAT D (waits three clocks) 000011 ZCR 1 CCCC DDDDDDDDD 000101001 DECPAT D (waits three clocks) 000011 ZCR 1 CCCC DDDDDDDDD 000101010 BINGRY D 000011 ZCR 1 CCCC DDDDDDDDD 000101011 GRYBIN D (waits one clock) 000011 ZCR 1 CCCC DDDDDDDDD 000101100 MERGEW D 000011 ZCR 1 CCCC DDDDDDDDD 000101101 SPLITW D 000011 ZCR 1 CCCC DDDDDDDDD 000101110 SEUSSF D 000011 ZCR 1 CCCC DDDDDDDDD 000101111 SEUSSR D 000011 ZCR 1 CCCC DDDDDDDDD 000110000 GETMULL D (waits for mul if !wc) 000011 ZCR 1 CCCC DDDDDDDDD 000110001 GETMULH D (waits for mul if !wc) 000011 ZCR 1 CCCC DDDDDDDDD 000110010 GETDIVQ D (waits for div if !wc) 000011 ZCR 1 CCCC DDDDDDDDD 000110011 GETDIVR D (waits for div if !wc) 000011 ZCR 1 CCCC DDDDDDDDD 000110100 GETSQRT D (waits for sqrt if !wc) 000011 ZCR 1 CCCC DDDDDDDDD 000110101 GETQX D (waits for cordic if !wc) 000011 ZCR 1 CCCC DDDDDDDDD 000110110 GETQY D (waits for cordic if !wc) 000011 ZCR 1 CCCC DDDDDDDDD 000110111 GETQZ D (waits for cordic if !wc) 000011 ZCR 1 CCCC DDDDDDDDD 000111000 GETPHSA D (GETPHSA wc,nr = POLCTRA wc) 000011 ZCR 1 CCCC DDDDDDDDD 000111001 GETPHZA D (clears phsa) 000011 ZCR 1 CCCC DDDDDDDDD 000111010 GETCOSA D 000011 ZCR 1 CCCC DDDDDDDDD 000111011 GETSINA D 000011 ZCR 1 CCCC DDDDDDDDD 000111100 GETPHSB D (GETPHSB wc,nr = POLCTRB wc) 000011 ZCR 1 CCCC DDDDDDDDD 000111101 GETPHZB D (clears phsb) 000011 ZCR 1 CCCC DDDDDDDDD 000111110 GETCOSB D 000011 ZCR 1 CCCC DDDDDDDDD 000111111 GETSINB D 000011 Z00 1 CCCC 111111111 001iiiiii REPD #i (infinite repeat) 000011 Z0N 1 CCCC nnnnnnnnn 001iiiiii REPD D/#n,#i 000011 n11 1 nnnn nnnnnnnnn 001iiiiii REPS #n,#i 000011 ZCN 1 CCCC nnnnnnnnn 01000---- <empty> 000011 ZCN 1 CCCC nnnnnnnnn 01001tttt JMPTASK D/#n,#t 000011 ZCN 1 CCCC nnnnnnnnn 010100000 NOPX D/#n (waits) 000011 ZCN 1 CCCC nnnnnnnnn 010100001 SETZC D/#n (d[1:0] into z/c via wz/wc) 000011 ZCN 1 CCCC Dnnnnnnnn 010100010 SETSPA D/#n 000011 ZCN 1 CCCC Dnnnnnnnn 010100011 SETSPB D/#n 000011 ZCN 1 CCCC Dnnnnnnnn 010100100 ADDSPA D/#n 000011 ZCN 1 CCCC Dnnnnnnnn 010100101 ADDSPB D/#n 000011 ZCN 1 CCCC Dnnnnnnnn 010100110 SUBSPA D/#n 000011 ZCN 1 CCCC Dnnnnnnnn 010100111 SUBSPB D/#n 000011 ZCN 1 CCCC nnnnnnnnn 010101000 PUSHAR D/#n 000011 ZCN 1 CCCC nnnnnnnnn 010101001 PUSHBR D/#n 000011 ZCN 1 CCCC nnnnnnnnn 010101010 PUSHA D/#n 000011 ZCN 1 CCCC nnnnnnnnn 010101011 PUSHB D/#n 000011 ZCN 1 CCCC nnnnnnnnn 010101100 CALLA D/#n 000011 ZCN 1 CCCC nnnnnnnnn 010101101 CALLB D/#n 000011 ZCN 1 CCCC nnnnnnnnn 010101110 CALLAD D/#n 000011 ZCN 1 CCCC nnnnnnnnn 010101111 CALLBD D/#n 000011 ZCN 1 CCCC SUPIIIIII 010110000 WRQUAD D/PTR (waits for hub) 000011 Z0N 1 CCCC SUPIIIIII 010110001 RDQUAD D/PTR (waits for hub) 000011 Z1N 1 CCCC SUPIIIIII 010110001 RDQUADC D/PTR (waits for hub if cache miss) 000011 ZCN 1 CCCC nnnnnnnnn 010110010 SETPTRA D/#n 000011 ZCN 1 CCCC nnnnnnnnn 010110011 SETPTRB D/#n 000011 ZCN 1 CCCC nnnnnnnnn 010110100 ADDPTRA D/#n 000011 ZCN 1 CCCC nnnnnnnnn 010110101 ADDPTRB D/#n 000011 ZCN 1 CCCC nnnnnnnnn 010110110 SUBPTRA D/#n 000011 ZCN 1 CCCC nnnnnnnnn 010110111 SUBPTRB D/#n 000011 ZCN 1 CCCC nnnnnnnnn 010111000 SETPIX D/#n 000011 ZCN 1 CCCC nnnnnnnnn 010111001 SETPIXU D/#n 000011 ZCN 1 CCCC nnnnnnnnn 010111010 SETPIXV D/#n 000011 ZCN 1 CCCC nnnnnnnnn 010111011 SETPIXZ D/#n 000011 ZCN 1 CCCC nnnnnnnnn 010111100 SETPIXA D/#n 000011 ZCN 1 CCCC nnnnnnnnn 010111101 SETPIXR D/#n 000011 ZCN 1 CCCC nnnnnnnnn 010111110 SETPIXG D/#n 000011 ZCN 1 CCCC nnnnnnnnn 010111111 SETPIXB D/#n 000011 Z0N 1 CCCC nnnnnnnnn 011000000 SETMULU D/#n 000011 Z1N 1 CCCC nnnnnnnnn 011000000 SETMULA D/#n 000011 ZCN 1 CCCC nnnnnnnnn 011000001 SETMULB D/#n 000011 Z0N 1 CCCC nnnnnnnnn 011000010 SETDIVU D/#n (loads [31:0], then [63:32]) 000011 Z1N 1 CCCC nnnnnnnnn 011000010 SETDIVA D/#n (loads [31:0], then [63:32]) 000011 ZCN 1 CCCC nnnnnnnnn 011000011 SETDIVB D/#n 000011 ZCN 1 CCCC nnnnnnnnn 011000100 SETSQRH D/#n 000011 ZCN 1 CCCC nnnnnnnnn 011000101 SETSQRL D/#n 000011 ZCN 1 CCCC nnnnnnnnn 011000110 SETQI D/#n 000011 ZCN 1 CCCC nnnnnnnnn 011000111 SETQZ D/#n 000011 ZCN 1 CCCC nnnnnnnnn 011001000 QLOG D/#n 000011 ZCN 1 CCCC nnnnnnnnn 011001001 QEXP D/#n 000011 ZCN 1 CCCC nnnnnnnnn 011001010 SETF D/#n 000011 ZCN 1 CCCC nnnnnnnnn 011001011 SETTASK D/#n 000011 ZCN 1 CCCC DDDDDDDnn 011001100 CFGDAC0 D/#n 000011 ZCN 1 CCCC DDDDDDDnn 011001101 CFGDAC1 D/#n 000011 ZCN 1 CCCC DDDDDDDnn 011001110 CFGDAC2 D/#n 000011 ZCN 1 CCCC DDDDDDDnn 011001111 CFGDAC3 D/#n 000011 ZCN 1 CCCC nnnnnnnnn 011010000 SETDAC0 D/#n 000011 ZCN 1 CCCC nnnnnnnnn 011010001 SETDAC1 D/#n 000011 ZCN 1 CCCC nnnnnnnnn 011010010 SETDAC2 D/#n 000011 ZCN 1 CCCC nnnnnnnnn 011010011 SETDAC3 D/#n 000011 ZCN 1 CCCC Dnnnnnnnn 011010100 CFGDACS D/#n 000011 ZCN 1 CCCC nnnnnnnnn 011010101 SETDACS D/#n 000011 ZCN 1 CCCC DDnnnnnnn 011010110 GETP D/#n (pin into !z/c via wz/wc) 000011 ZCN 1 CCCC DDnnnnnnn 011010111 GETNP D/#n (pin into z/!c via wz/wc) 000011 ZCN 1 CCCC DDnnnnnnn 011011000 OFFP D/#n 000011 ZCN 1 CCCC DDnnnnnnn 011011001 NOTP D/#n 000011 ZCN 1 CCCC DDnnnnnnn 011011010 CLRP D/#n 000011 ZCN 1 CCCC DDnnnnnnn 011011011 SETP D/#n 000011 ZCN 1 CCCC DDnnnnnnn 011011100 SETPC D/#n 000011 ZCN 1 CCCC DDnnnnnnn 011011101 SETPNC D/#n 000011 ZCN 1 CCCC DDnnnnnnn 011011110 SETPZ D/#n 000011 ZCN 1 CCCC DDnnnnnnn 011011111 SETPNZ D/#n 000011 ZCN 1 CCCC DDDDDnnnn 011100000 SETCOG D/#n 000011 ZCN 1 CCCC DDDnnnnnn 011100001 SETMAP D/#n 000011 Z0N 1 CCCC nnnnnnnnn 011100010 SETQUAD D/#n 000011 Z1N 1 CCCC nnnnnnnnn 011100010 SETQUAZ D/#n 000011 ZCN 1 CCCC DDnnDDDDD 011100011 SETPORT D/#n 000011 ZCN 1 CCCC DDnnDDDDD 011100100 SETPORA D/#n 000011 ZCN 1 CCCC DDnnDDDDD 011100101 SETPORB D/#n 000011 ZCN 1 CCCC DDnnDDDDD 011100110 SETPORC D/#n 000011 ZCN 1 CCCC DDnnDDDDD 011100111 SETPORD D/#n 000011 ZCN 1 CCCC nnnnnnnnn 011101000 SETXCH D/#n 000011 ZCN 1 CCCC DDDnnnnnn 011101001 SETXFR D/#n 000011 ZCN 1 CCCC DDDDDDDDD 011101010 SETSER D/#n 000011 ZCN 1 CCCC DDDnnnnnn 011101011 SETSKIP D/#n 000011 ZCN 1 CCCC nnnnnnnnn 011101100 SETVID D/#n 000011 ZCN 1 CCCC nnnnnnnnn 011101101 SETVIDY D/#n 000011 ZCN 1 CCCC nnnnnnnnn 011101110 SETVIDI D/#n 000011 ZCN 1 CCCC nnnnnnnnn 011101111 SETVIDQ D/#n 000011 ZCN 1 CCCC nnnnnnnnn 011110000 SETCTRA D/#n 000011 ZCN 1 CCCC nnnnnnnnn 011110001 SETWAVA D/#n 000011 ZCN 1 CCCC nnnnnnnnn 011110010 SETFRQA D/#n 000011 ZCN 1 CCCC nnnnnnnnn 011110011 SETPHSA D/#n 000011 ZCN 1 CCCC nnnnnnnnn 011110100 ADDPHSA D/#n 000011 ZCN 1 CCCC nnnnnnnnn 011110101 SUBPHSA D/#n 000011 ZCN 1 CCCC nnnnnnnnn 011110110 SYNCTRA (waits for ctra) 000011 ZCN 1 CCCC nnnnnnnnn 011110111 CAPCTRA 000011 ZCN 1 CCCC nnnnnnnnn 011111000 SETCTRB D/#n 000011 ZCN 1 CCCC nnnnnnnnn 011111001 SETWAVB D/#n 000011 ZCN 1 CCCC nnnnnnnnn 011111010 SETFRQB D/#n 000011 ZCN 1 CCCC nnnnnnnnn 011111011 SETPHSB D/#n 000011 ZCN 1 CCCC nnnnnnnnn 011111100 ADDPHSB D/#n 000011 ZCN 1 CCCC nnnnnnnnn 011111101 SUBPHSB D/#n 000011 ZCN 1 CCCC nnnnnnnnn 011111110 SYNCTRB (waits for ctrb) 000011 ZCN 1 CCCC nnnnnnnnn 011111111 CAPCTRB 000011 ZCR 1 CCCC DDDDDDDDD 1000bbbbb ISOB D,b 000011 ZCR 1 CCCC DDDDDDDDD 1001bbbbb NOTB D,b 000011 ZCR 1 CCCC DDDDDDDDD 1010bbbbb CLRB D,b 000011 ZCR 1 CCCC DDDDDDDDD 1011bbbbb SETB D,b 000011 ZCR 1 CCCC DDDDDDDDD 1100bbbbb SETBC D,b 000011 ZCR 1 CCCC DDDDDDDDD 1101bbbbb SETBNC D,b 000011 ZCR 1 CCCC DDDDDDDDD 1110bbbbb SETBZ D,b 000011 ZCR 1 CCCC DDDDDDDDD 1111bbbbb SETBNZ D,b 000100 000 I CCCC DDDDDDDDD SSSSSSSSS SETACCA D,S 000100 010 I CCCC DDDDDDDDD SSSSSSSSS SETACCB D,S 000100 100 I CCCC DDDDDDDDD SSSSSSSSS MACA D,S 000100 110 I CCCC DDDDDDDDD SSSSSSSSS MACB D,S 000100 ZC1 I CCCC DDDDDDDDD SSSSSSSSS MUL D,S (waits one clock) 000101 000 I CCCC DDDDDDDDD SSSSSSSSS MOVF D,S 000101 010 I CCCC DDDDDDDDD SSSSSSSSS QSINCOS D,S 000101 100 I CCCC DDDDDDDDD SSSSSSSSS QARCTAN D,S 000101 110 I CCCC DDDDDDDDD SSSSSSSSS QROTATE D,S 000101 ZC1 I CCCC DDDDDDDDD SSSSSSSSS SCL D,S (waits one clock) 000110 ZCR I CCCC DDDDDDDDD SSSSSSSSS ENC D,S 000111 ZCR I CCCC DDDDDDDDD SSSSSSSSS JMPRET D,S 001000 ZCR I CCCC DDDDDDDDD SSSSSSSSS ROR D,S 001001 ZCR I CCCC DDDDDDDDD SSSSSSSSS ROL D,S 001010 ZCR I CCCC DDDDDDDDD SSSSSSSSS SHR D,S 001011 ZCR I CCCC DDDDDDDDD SSSSSSSSS SHL D,S 001100 ZCR I CCCC DDDDDDDDD SSSSSSSSS RCR D,S 001101 ZCR I CCCC DDDDDDDDD SSSSSSSSS RCL D,S 001110 ZCR I CCCC DDDDDDDDD SSSSSSSSS SAR D,S 001111 ZCR I CCCC DDDDDDDDD SSSSSSSSS REV D,S 010000 ZCR I CCCC DDDDDDDDD SSSSSSSSS MINS D,S 010001 ZCR I CCCC DDDDDDDDD SSSSSSSSS MAXS D,S 010010 ZCR I CCCC DDDDDDDDD SSSSSSSSS MIN D,S 010011 ZCR I CCCC DDDDDDDDD SSSSSSSSS MAX D,S 010100 ZCR I CCCC DDDDDDDDD SSSSSSSSS MOVS D,S 010101 ZCR I CCCC DDDDDDDDD SSSSSSSSS MOVD D,S 010110 ZCR I CCCC DDDDDDDDD SSSSSSSSS MOVI D,S 010111 ZCR I CCCC DDDDDDDDD SSSSSSSSS JMPRETD D,S 011000 ZCR I CCCC DDDDDDDDD SSSSSSSSS AND D,S 011001 ZCR I CCCC DDDDDDDDD SSSSSSSSS ANDN D,S 011010 ZCR I CCCC DDDDDDDDD SSSSSSSSS OR D,S 011011 ZCR I CCCC DDDDDDDDD SSSSSSSSS XOR D,S 011100 ZCR I CCCC DDDDDDDDD SSSSSSSSS MUXC D,S 011101 ZCR I CCCC DDDDDDDDD SSSSSSSSS MUXNC D,S 011110 ZCR I CCCC DDDDDDDDD SSSSSSSSS MUXZ D,S 011111 ZCR I CCCC DDDDDDDDD SSSSSSSSS MUXNZ D,S 100000 ZCR I CCCC DDDDDDDDD SSSSSSSSS ADD D,S 100001 ZCR I CCCC DDDDDDDDD SSSSSSSSS SUB D,S 100010 ZCR I CCCC DDDDDDDDD SSSSSSSSS ADDABS D,S 100011 ZCR I CCCC DDDDDDDDD SSSSSSSSS SUBABS D,S 100100 ZCR I CCCC DDDDDDDDD SSSSSSSSS SUMC D,S 100101 ZCR I CCCC DDDDDDDDD SSSSSSSSS SUMNC D,S 100110 ZCR I CCCC DDDDDDDDD SSSSSSSSS SUMZ D,S 100111 ZCR I CCCC DDDDDDDDD SSSSSSSSS SUMNZ D,S 101000 ZCR I CCCC DDDDDDDDD SSSSSSSSS MOV D,S 101001 ZCR I CCCC DDDDDDDDD SSSSSSSSS NEG D,S 101010 ZCR I CCCC DDDDDDDDD SSSSSSSSS ABS D,S 101011 ZCR I CCCC DDDDDDDDD SSSSSSSSS ABSNEG D,S 101100 ZCR I CCCC DDDDDDDDD SSSSSSSSS NEGC D,S 101101 ZCR I CCCC DDDDDDDDD SSSSSSSSS NEGNC D,S 101110 ZCR I CCCC DDDDDDDDD SSSSSSSSS NEGZ D,S 101111 ZCR I CCCC DDDDDDDDD SSSSSSSSS NEGNZ D,S 110000 ZCR I CCCC DDDDDDDDD SSSSSSSSS CMPS D,S 110001 ZCR I CCCC DDDDDDDDD SSSSSSSSS CMPSX D,S 110010 ZCR I CCCC DDDDDDDDD SSSSSSSSS ADDX D,S 110011 ZCR I CCCC DDDDDDDDD SSSSSSSSS SUBX D,S 110100 ZCR I CCCC DDDDDDDDD SSSSSSSSS ADDS D,S 110101 ZCR I CCCC DDDDDDDDD SSSSSSSSS SUBS D,S 110110 ZCR I CCCC DDDDDDDDD SSSSSSSSS ADDSX D,S 110111 ZCR I CCCC DDDDDDDDD SSSSSSSSS SUBSX D,S 111000 ZCR I CCCC DDDDDDDDD SSSSSSSSS SUBR D,S 111001 ZCR I CCCC DDDDDDDDD SSSSSSSSS CMPSUB D,S 111010 ZCR I CCCC DDDDDDDDD SSSSSSSSS INCMOD D,S 111011 ZCR I CCCC DDDDDDDDD SSSSSSSSS DECMOD D,S 111000 000 I BBAA DDDDDDDDD SSSSSSSSS SETINDx D,S (SETINDA S / SETINDB D / SETINDS D,S) 111001 000 I 0B0A DDDDDDDDD SSSSSSSSS FIXINDx D,S (FIXINDA D,S / FIXINDB D,S / FIXINDS D,S) 111010 000 I CCCC DDDDDDDDD SSSSSSSSS CFGPINS D,S (waits for alt) 111011 000 I CCCC DDDDDDDDD SSSSSSSSS WAITVID D,S (waits for vid) 111100 00R I CCCC DDDDDDDDD SSSSSSSSS IJZ D,S 111100 01R I CCCC DDDDDDDDD SSSSSSSSS IJZD D,S 111100 10R I CCCC DDDDDDDDD SSSSSSSSS IJNZ D,S 111100 11R I CCCC DDDDDDDDD SSSSSSSSS IJNZD D,S 111101 00R I CCCC DDDDDDDDD SSSSSSSSS DJZ D,S 111101 01R I CCCC DDDDDDDDD SSSSSSSSS DJZD D,S 111101 10R I CCCC DDDDDDDDD SSSSSSSSS DJNZ D,S 111101 11R I CCCC DDDDDDDDD SSSSSSSSS DJNZD D,S 111110 000 I CCCC DDDDDDDDD SSSSSSSSS TJZ D,S 111110 010 I CCCC DDDDDDDDD SSSSSSSSS TJZD D,S 111110 100 I CCCC DDDDDDDDD SSSSSSSSS TJNZ D,S 111110 110 I CCCC DDDDDDDDD SSSSSSSSS TJNZD D,S 111110 001 I CCCC DDDDDDDDD SSSSSSSSS JP D,S 111110 011 I CCCC DDDDDDDDD SSSSSSSSS JPD D,S 111110 101 I CCCC DDDDDDDDD SSSSSSSSS JNP D,S 111110 111 I CCCC DDDDDDDDD SSSSSSSSS JNPD D,S 111111 0CR I CCCC DDDDDDDDD SSSSSSSSS WAITCNT D,S (waits for cnt32, +cnt64 if wc) 111111 1C0 I CCCC DDDDDDDDD SSSSSSSSS WAITPEQ D,S (waits for pins, +cnt32 if wc) 111111 1C1 I CCCC DDDDDDDDD SSSSSSSSS WAITPNE D,S (waits for pins, +cnt32 if wc) ------------------------------------------------------------------------------------------------- ZCR effects ------------------------------------------------------------------------------------------------- 000 nz, nc, nr 001 nz, nc, wr 010 nz, wc, nr 011 nz, wc, wr 100 wz, nc, nr 101 wz, nc, wr 110 wz, wc, nr 111 wz, wc, wr CCCC condition (easier-to-read list) ------------------------------------------------------------------------------------------------- 0000 never 1111 always (default) 0001 nc & nz 1100 if_c if_b 0010 nc & z 0011 if_nc if_ae 0011 nc 1010 if_z if_e 0100 c & nz 0101 if_nz if_ne 0101 nz 1000 if_c_and_z if_z_and_c 0110 c <> z 0100 if_c_and_nz if_nz_and_c 0111 nc | nz 0010 if_nc_and_z if_z_and_nc 1000 c & z 0001 if_nc_and_nz if_nz_and_nc if_a 1001 c = z 1110 if_c_or_z if_z_or_c if_be 1010 z 1101 if_c_or_nz if_nz_or_c 1011 nc | z 1011 if_nc_or_z if_z_or_nc 1100 c 0111 if_nc_or_nz if_nz_or_nc 1101 c | nz 1001 if_c_eq_z if_z_eq_c 1110 c | z 0110 if_c_ne_z if_z_ne_c 1111 always 0000 never CCCC inda/indb - CCCC=1111 after first stage of pipeline if inda/indb used (indx=inda/indb) ------------------------------------------------------------------------------------------------- xx00 source indx xx01 source indx++ xx10 source indx-- xx11 source ++indx 00xx destination indx 01xx destination indx++ 10xx destination indx-- 11xx destination ++indx I SSSSSSSSS source operand ------------------------------------------------------------------------------------------------- 0 SSSSSSSSS register 1 #SSSSSSSSS immediate, zero-extended DDDDDDDDD destination operand ------------------------------------------------------------------------------------------------- DDDDDDDDD register