The unofficial P2 documentation project
Peter Jakacki
Posts: 10,193
I've started up a Google document with the text from Chip's latest posts for documenting the P2 and I have been dressing these up as best I can in the meantime along with tables and diagrams. seairth has also contributed to this and slowly we are not only dressing it up but adding in more stuff from posts etc.
The web-page version of the document is viewable without any signing in required
If you want to contribute then go to the Google document and request sharing.
Now if only we could get Chip to add stuff to this page instead of that plain text that's embedded in one of the posts.
EDIT: A training copy of the document is available for anyone to edit without signing in. You can try out editing the document and if you are happy with the result then you can copy and paste into the main document if you have permissions. Obviously it's not meant for trashing intentionally but more of a trainer or even as a safe way to try something special or major. Of course you can copy the document into a Google document of your own to play with.
Here's the link to the training copy http://goo.gl/QKXgH
The web-page version of the document is viewable without any signing in required
If you want to contribute then go to the Google document and request sharing.
Now if only we could get Chip to add stuff to this page instead of that plain text that's embedded in one of the posts.
EDIT: A training copy of the document is available for anyone to edit without signing in. You can try out editing the document and if you are happy with the result then you can copy and paste into the main document if you have permissions. Obviously it's not meant for trashing intentionally but more of a trainer or even as a safe way to try something special or major. Of course you can copy the document into a Google document of your own to play with.
Here's the link to the training copy http://goo.gl/QKXgH
Comments
Well you can download the editable document in different formats including pdf but the formatting of it is really suited for web viewing. So at the moment this is the form it is in but I will experiment to see which is the best way for making it into a pdf.
I've become really frustrated with the poor to practically non-existent documentation of both commercial and open source software/hardware lately.
I know there a some on this forum that pretty much won't use anything that isn't open source, I'm getting to the point where I won't use anything that isn't well documented.
So at least it looks like I'll be safe using the P2. :-)
C.W.
That's a fair observation. The documentation is primarily verbatim of what Chip has posted, with the exception of formatting. There will be quite a lot of gaps to start with due to the implied knowledge of P1. We are, however, starting to fill in the gaps. If you see other things like this, make sure to mention them.
I learned a couple things by reading it.
Keep up the good work...
Bean
But the only complaint I have is the badly "shopped" picture of the non-existent "P8FX128" on the front page with the deprecated beanie logo and the associated kitschy parenthetical.
Also the cog memory map has an error. It states 512 longs but the address labels indicate 502 longs of RAM.
Updated. I replaced it with the generic graphic from http://www.parallaxsemiconductor.com/sites/default/files/parallax/Propeller2DetailedPreliminaryFeatureList-v2.0.pdf
Yeah, there's a comment to that effect on the document. I went ahead and updated the diagram to fill out all of the reserved registers. See if that's more clear now.
(T)QFP-128, .4mm pin spacing, overall size (14mm?).
The PLL multiplier bit fields are a little vague. does 0001...1111 mean "1 to 15" or
0001 = x2
0011 = x4
0111 = x8
1111 = x16
IIRC the 256 long stack/fifo can also be accessed indirectly as well as push/pop instructions. Seeing these now, its a shame we dont have 2 special move instructions to move a long into/out of the fifo by using an immediate fifo address (best not tell Chip as we dont want to delay P2 any more).
BTW I can understand Chip just wants/needs to churn out the info at this point in time He doesn't have the time to pretty it up like you have done. Others can do that - lets just get the info from him.
I absolutely agree. In fact, he *shouldn't* be doing the pretty bits right now. That's not where the real value is. If he post the information (in whatever form), we'll make sure it gets integrated.
This would be clear if you were conversant with the P1 PASM instruction set. At this stage Chip isn't going to have the time to assemble a beginner's tutorial and I expect everything given to us to be addressed in terms of how it differs from P1. D and S are 9-bit subfields of the 32-bit PASM instruction which point to the destination and source in either Cog RAM or, according to another bit, possibly a literal 9-bit value in S. P2 obviously has more options.
Don't mention it. I'm glad to do what I can to help. Between the FPGA efforts and documentation efforts, we'll help get the P2 into production as quickly as possible. And with an active development community already in place, to boot! How many chip makers can boast that?
BTW, despite the criticism about the "chip" image this was done to help make it come alive but I didn't want anyone to think for a minute that it was real while I was playing around with what this document could be. A project can be fun at the time as being useful.
I've added some bullets to the side for this information. I wasn't able to find an official mention of the package size, but 14mm seems standard for a QFP-128 with 0.4mm pitch. So I put that down for the moment.
That bit was directly from Chip's documentation. However, I have expanded it to make it a bit more explicit. I interpreted the bit pattern to indicate a linear range from 2x to 16x, based on the fact that Chip tends to use the ellipses in other parts of his documentation to indicate linear range. Further, since the enumerated all of the other bit fields, i would have expected him to enumerate this one as well if there were only four possible values.
Hopefully, Chip is following this thread and will correct me (us) when we are wrong.
Peter,
I'd like to start by thanking you for your efforts in putting the document together. I wish I had the time and knowledge to help with the writing of the documentation but if you don't mind comments from someone limited knowledge of pasm I'll be happy to take on the role of noob trying to make sense of all of this (not at all a stretch since I've never written a program in pasm
BTW, you may need to sign in or create a Google identity but I will have to try this on a clean browser or system to remember how it works.
In Chapter:
COG MEMORY (8 instances)
Can You revise Colored Picture of COG information with that small BOX with arows.
_____________________________________ xxxxxx xxx x xxxx DDDDDDDDD SSSSSSSSS | S Source field in instruction D Destination field in instruction [B]PTRA [/B]and [B]PTRB [/B]are only for pointing to [B]HUB [/B]memory . [B]INDA [/B]and [B]INDB [/B]are for pointing to [B]COG [/B]memory . ------> Missing in picture [B]SPA [/B]and [B]SPB [/B]are for pointing to [B]CLUT/stack[/B] memory . 'If you want to read longs quickly into registers, it's simplest to just do [B]'RDLONGC INDA++,PTRA++'.[/B] ' Less stuff to think about that way.Would you be up to handling this yourself perhaps? Just sign-in or sign-up and request to be a collaborator.
Sorry if I say that way.
My English semantic is not so good -- so be nice if You edit it.
Thanks
BTW, make sure you refresh your page because the PTR registers point to the hub, they were changed very early in the edit.
And:
INDA and INDB are for pointing to COG memory .
> Mising in Picture
Need point in like box to Yelow area of COG space.
Maybe cosmetics for us that understand it --- But for that ones that start with Propeller II -- Can be valuable.
Thanks