I see. So your Ts is the total time to convert a new value of N bits
and the Fclk is the rate at which the output pin is pulsed (oversample frequency).
Rayman,
I made a document with 5 steps to calculate the component values.
If you find any errors in these calculations, let me know.
The calculations include shift levels.
I'm skeptical about the calculation of input bandwidth, F2 in Raymond's, which uses the input resistor R2 only, and step 4 in Peter's, which uses the Rp combination of all three resistors. The problem is similar to the summing node of an op amp, in the sense that due to feedback, the voltage on the capacitor does not have to change (or the change is the output change divided by the open loop gain). The same thing may be true here in the limit of high oversampling. That is to say, to first order, choosing 200k resistors instead of 100k resistors does not imply 1/2 the bandwidth per the formulas. Or, the choice of capacitor does not have as strong effect on bandwidth as implied by the formulas. The references cited do not address this issue. One thing that is quite different for an op amp is that hanging a capacitor from the summing node to ground raises the gain at high frequencies and leads to instability, depending on phase delays in the op amp itself. In the Prop, the sampling phase delay is always precisely one cycle, far higher in frequency than an input one would expect to appy.
I also have problems with the formulas relating RC to the bit rate (F1 or step 5). I understand the mechanics of the math. There is more to it though, as the actual feedback frequency (the details of the bit pattern) is strongly dependent on the instantaneous signal magnitude. I'm not saying my skepticism is justified, I'm just saying I'm not convinced and haven't had time or insight to think it through to prove something one way or another. It's the justification for the math that eludes me.
The one thing that is certain is that it takes Ts = 2^N clock cycles to acquire an N bit sample, and traditional oversampling starts from there. 2 / (2pi*Ts) to reach Nyquist, and much more to really connect the dots at the chosen resolution. There is no problem with the analysis at DC, for choosing the resistor values based on range. Everyone agrees with that, and the addition of the two extra resistors to set the range is very useful too.
I'm skeptical of my F1&F2 calculations also! I'm starting to think it is very much like an opamp in a feedback circuit though. In this case, maybe there's a Gain-Bandwidth product that matters. I'll have to check if this is what Peter is calculating...
I am even more surprised that Rp drops out totally.
Summarizing:
Given the design parameters Uinmin and Uinmax, and selecting a value for R1,
we can calculate R2, R3 and R4. This leaves C to be determined.
Fs > 2*Fin· (Nyquist)
Fs*Tc = 2^N
C = Tc/(4*R2)
So there are 3 more design parameters: Fs, Tc and N
two of which you can select, the 3rd is then set.
Often Fs is determined by the program and the used oscillator frequency
so you can either select Tc or N.
Edit:
Since the realtime conversion time is in fact given by the actual used Fs and N,
it may be better to leave Tc out of the calculation until Fs and N are set.
Fs*Tc = 2^N· with Tc = 4*C*R2 becomes
Fs*4*C*R2 = 2^N
C = (2^N)/(4*R2*Fs)
So select N·and Fs and calculate C
Select the larger standard C value that is nearest to the calculated value.
(larger to keep the ripple at the summing node within 1 LSB)
Tc = (2^N)/Fs
If·Tc is too large, either decrease N or increase Fs and recalculate C.
regards peter
Post Edited (Peter Verkaik) : 10/20/2007 5:03:44 AM GMT
·································· R2····················R2
This gives a new condition: x =
< 1··· ---->··· -- < 2^N ······························· (2^N)*Rp·················Rp
···················· R2
Assuming that x =
is much smaller than 1, then ln(1+x)-ln(1-x) = 2x ················· (2^N)*Rp
I'm still trying to get a grip on this... I'm currently thinking that the value of the resistor between measured voltage input and C only affects input voltage range and doesn't affect the frequency response at all. This is because it's really the input current that matters and this is the same for a big voltage with big resistor as it is for some small voltage and a small resistor.
Also, I'm think that the RC time on the prop side of C only matters because of imperfections and noise in the quantizer. With larger values of RC, the input pin voltage hovers closer to the Vdd/2 threshold and is more susceptible to noise. On the other side, you can't have RC to small or the voltage there will be often very close to Vdd or Vss and also be susceptible to noise (because a small change in voltage can dramatically change the information stored).
So, I would think you'd want the RC time on the prop side to be a few times the clock period. This way, both the input voltage and feedback voltage can substantially change the capacitor voltage. But, the feedback can keep it away from the Vdd/Vss rails.
So, the one degree of freedom left is absolute value of R (or C) on the prop side. This decides how much current comes out of the Prop output pin. There is a hard upper limit of a few mA. The lower limit is probably also determined by noise. But, more basically, this R determines the R on the input side because we already know the voltage range we want to measure. And, the R on the input side is the input impedance to the ADC. I think this is a more important parameter.
So, here would be the proceedure:
1. Decide on input voltage range to ADC, Vrange.
2. Decide on input impedance to ADC, Zin.
3. Decide on clock frequency of Prop, Fclk.
4. Calculate R1 (prop side) and R2 from Vrange and Zin.
5. Calculate a good C from R1 and Fclk such that R1*C is N times 1/Fclk. (maybe N should be ~8 or so?)
Peter, I'm just getting a chance to look at your recent derivation. Thanks for your efforts!
I was initially stuck on the first equation, because I didn't realize that Ut is the voltage at the summing junction and that the components are otherwise the same as in the pdf that you posted about 10 messages back, sigmadeltaadc.pdf? The equation is from KCL. Okay.
Peter Verkaik said...
Here are my latest calculations.
The outcome is indeed different for Fs.
Charge: voltage at outpin = Vdd
Uin Vdd Vdd Ut Ut Ut Ut dUt
--- + --- + --- - -- - -- - -- - -- - 2C*--- = 0
R1 R2 R3 R1 R2 R3 R4 dt
I'm still l puzzled by the steps that use the equation from KCL. Okay, the solution is a decreasing exponential when the outpin is low and an increasing exponential when the outpin is high. Time constant is k=1/RC in either case, and there is an initial condition. But I'm lost on the the significance of the initial condition parameters A and Umin. I need a picture. The shape of that curve is going to be very dependent on how long the output spends high and low and as in the reference cited by deSilva. The initial conditions can change in a complicated pattern. How do the results of these calculations relate to "conversion time"? Changes of Uin are not even considered.
Tracy,
I assumed Uin is at the middle of the input range, Uin = (Uinmax+Uinmin)/2
so Ut hoovers around Vdd/2 each Ts.
Then·the generated digital pulses should have pattern ...10101010...
hence the charge/discharge curves.
regards peter
Post Edited (Peter Verkaik) : 10/21/2007 4:59:03 AM GMT
(a) There is not really a "static" case: current is flowing all the time between signal source and cap, except in the case of a signal voltage of exactly 1.65 V. To compensate for this, the feed-back pattern is generally very different from 10101, even for a DC signal.
When the signal path draws "Is" through "Rs", the feed-back will deliver "If = 3V/Rf" for as long as it takes to fill-up
the cap again. So:
Is = If*dutycycle
Note that a sequence of 110 110 110 will effectively deliver If/3 per clock, as 0 is not "nothing" but draws the same amount of charge fed before.
However the voltage at the cap will never change for more than:
dU/dt = If/C = 3V/(Rf*C)
per clock tick.
And so there is no dependency on "C" whatsoever, but only on "Rf*C"
(b) This is a DC analysis, what happens for "changing" signals, a sine wave with frequency "fs"?
Well not much else, as the feed-back compensates each rise along the sine wave as soon as it happens, because it is so much faster ("1/clock >> fs")
But what, if it is not? This is part of Peter's analysis: A higher frequency part in the input signal will be noise or even lead to an unstable feed-back. But when starts "higher"?
As a sine changes most at its zero crossover, the worst case input current per time is "2*pi*fs*mean(Is)"
If this can be compensated for during one or a few clock ticks it would be perfect, if not there will be a noticable "instability" of the cap voltage.
The condition is:
If/clock >= 2*pi*fs*mean(Is)
To care already for even the static case, we always need "If >= mean(Is)" so a sufficient condition for a stable operation should be:
1/clock >= 2*pi*fs
Thus an oversampling of 6 wrt to the highest frequeny part should suffice for a stable operation. Unstability will occur when higher frequency parts occur with high ampitiude, the analysis of which is not trivial....
Of course it will improve the worst case situation to put an additional low pass before the delta sigma, but a much more useful device is a second order delta-sigma modulator. I think there is an example for it in the link I gave...
Attached is an updated document with component calculations.
DeSilva,
Actually, I am only looking at the situation that the generated pulse
output is ...01010101...
Uin drops out of the equations when I calculate Uripple at the junction node.
Uripple must comply to
Uripple = Vdd/(2^N) where N is the bit resolution
R3 and R4 only have a limited effect on the calculation for C.
But C does depend on Fs, R2·and bit resolution N.
I also found that R2 must comply to
R2/Rp < 2^N where Rp = R1//R2//R3//R4
Usually R2/Rp << 2^N and that's why R3 and R4 have no big effect on the calculated C.
But it does have an effect on allowable input range. (Step 3 in attached document).
Very small input ranges require a larger N if the input range is shifted up or down,
especially beyond Vdd or when Uinmin < 0.
Peter Verkaik said...
DeSilva,
Actually, I am only looking at the situation that the generated pulse output is ...01010101...
There is never such a situation [noparse]:)[/noparse] much more often occurs
1111111111
or
00000000
said...
Uripple = Vdd/(2^N) where N is the bit resolution
This should be no surprise, as it is the LEAST POSSIBLE (quantization) noise for a perfect situation
said...
But C does depend on Fs, R2 and bit resolution N.
This is obvious, as you named all degrees of freedom before
said...
Very small input ranges require a larger N if the input range is shifted up or down,
especially beyond Vdd or when Uinmin < 0.
This is a scaling effect only; the delta-sigma is always oriented towards 0 and Vdd.
Only this range gives the full resolution. When you - say - use just 12.5% of it you have to multiply your N
to get the same resolution again, otherwise you loose 3 bits...
I don't quite understand your last remark. The minimal required N that follows
from step 3 is to keep the ADC working in its lineair area, not to compensate for lost bits.
Even a small input range has full resolution (0 represents Uinmin, (2^N)-1 represents Uinmax).
This N can also be calculated from R2/Rp < 2^N
If R2/Rp >= 2^N then the voltage at the junction cannot be corrected to Vdd/2.
The physical effect is perhaps clearer from
(Uinmax - Uinmin)/2 > Vdd/(2^N)
which leads to the same minimal N.
In words: Half the input range must be greater than 1 LSB
It would be neat to measure a thermocouple voltage, however, without amplification it might fall below the noise threshold. Even full scale changes are only on the order of millivolts. Assuming a best case resolution of 14 bits on a full scale span of 3 volts, the least significant bit is 183 microvolts.
Peter, and don't know why I get the impression you have it all upside down
When designing an ADC you have to Parameters:
(a) The bandwidth "fs" you want to use: You know from Shannon and Nyquest that you have to sample with a clock tqise as high "1/(2*fs)". There is no way out - this is true and basic mathematics.
(b) The resolution (or granularity) of the amplitude. Due to the character of the delta-sigma process you add small and constant packages of charge to hold the balance. So it takes some TIME; when you count time with a clock you need 2^N clocks to guarantee a stable measurement on an equidistant scale. This in fact is CURRENT you measure.
You say: "Ah, in this period T I send P packages of 2 uCoulomb each, so I fed a current of P/T* 2uCoulomb."
As the pin voltage is constant, the current during the "sent-package-time" is determined by the resistor R2. So there is maximum current, issued when you send the maximum of 2^N packages during T.
Now, as you want to catch some dynamic in the signal, you have to adjust T so that it meets the Shannon/ Nyquest condition.
There are complex noise considerations for highly dynamic signals when 2^N is very small; in one posting above I estimated you can run into problems with 2^N<6.
The only important condition is the current equilibrium, which can be expressed through resistor values when the involved voltages are known. The cap then has to be determined by the Nyquist formula.
Tracy: I'm going to change the voltage range using pull-up/down resistors by changing the R1/R2 ratio... But, I admit it might not work. I'm going to try it tomorrow if I have time though (just for fun).
Rayman,
It will be interesting to see those thermocouple results. The question of the accuracy attainable with the Prop sigma-delta is still open. We already know that the layout makes a terrific difference, and Chip has even suggested which pin combinations are likely to have the best results, based on the interior layout of the mask. http://forums.parallax.com/showthread.php?p=677970
The range is decreased when the value of R1 (the input resistor) is small relative to R2 (the feedback resistor). There is a question of where to bias the other side of the thermocouple. It could be biased at or near Vdd/2, so that the output would be centered on 50%. Adding a pullup resistor R3=R1 could push the mid-point down to Vss, but it seems to me that that option would upset the balance, in terms of noise coupled from Vdd. Worth a try though.
An external option is to input the thermocouple into a CAZ op amp (e.g. LTC2054), configured with a transistor as a voltage controlled current source with gain to drive the ADC.
I just got it working! Using R1=100k, R2=390, and using a 1K trim pot to pull up to Vdd, I can read a type-K thermocouple voltage. At least, I get about what I think I should...
Basic test was to adjust trim pot so that reading is close to 50%. Then, dipped TC in boiling water to read 18%. Then dipped TC in ice water to read 45%. This is a 27% change...
I looked at a table earlier that said the difference should be 4 mV between 0 and 100 degrees C, which should mean a 31% change. I got a 27% change, which is pretty good (I think) considering how basic this setup is...
Of course, you'd need a look-up table to convert to actual temperature...
That's encouraging! Whatever the DC stability may turn out to be, it shows that one can detect millivolt level changes. What is the hardware setup, I mean, what board layout and pins, and where is the other side of the TC connected?
Nice applet by the way. (note to other readers: R1 and R2 designations in the applet are reversed from the ones in Peter's PDF)
Im just getting started on·the ADC part for my·"rigg from hell"...
On my debug screen i just get the same value whatever i do...
@12 bits samplin rate i get "2200-3000" values on the screen going up and down in a fairly slow rate not in anyway linked to the voltage im sending in, im using the standard ADC Appnote hookup to the prop.
Comments
as given by the C*R equation.
regards peter
The Ts there (maybe I should rename it) is just the time it takes the Prop to take a sample....
and the Fclk is the rate at which the output pin is pulsed (oversample frequency).
regards peter
I made a document with 5 steps to calculate the component values.
If you find any errors in these calculations, let me know.
The calculations include shift levels.
regards peter
Thanks. Looks good. I still have to think some more about "Step 5"!
I also have problems with the formulas relating RC to the bit rate (F1 or step 5). I understand the mechanics of the math. There is more to it though, as the actual feedback frequency (the details of the bit pattern) is strongly dependent on the instantaneous signal magnitude. I'm not saying my skepticism is justified, I'm just saying I'm not convinced and haven't had time or insight to think it through to prove something one way or another. It's the justification for the math that eludes me.
The one thing that is certain is that it takes Ts = 2^N clock cycles to acquire an N bit sample, and traditional oversampling starts from there. 2 / (2pi*Ts) to reach Nyquist, and much more to really connect the dots at the chosen resolution. There is no problem with the analysis at DC, for choosing the resistor values based on range. Everyone agrees with that, and the addition of the two extra resistors to set the range is very useful too.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Tracy Allen
www.emesystems.com
The outcome is indeed different for Fs.
Charge: voltage at outpin = Vdd
Uin·· Vdd·· Vdd·· Ut·· Ut·· Ut·· Ut····· dUt
--- + --- + --- - -- - -- - -- - -- - 2C*--- = 0
R1··· R2··· R3··· R1·· R2·· R3·· R4····· dt
Let Rp = R1//R2//R3//R4 and Cp = 2C then
Uin··· Vdd···· Ut····· dUt
--- +
- -- - Cp*--- = 0
R1··· R2//R3·· Rp····· dt
Let Ut = Umin*e^(-kt) + A - A*e^(-kt)
dUt
--- = -k*Umin*e^(-kt) + k*A*e^(-kt)
dt
Substituting Ut and dUt/dt
Uin··· Vdd···· Umin·········· A··· A
--- +
- ----*e^(-kt) - -- + --*e^(-kt) + Cp*k*Umin*e^(-kt) - Cp*k*A*e^(-kt) = 0
R1··· R2//R3··· Rp··········· Rp·· Rp
Substituting t=infinity
Uin··· Vdd···· A······························ Uin··· Vdd
--- +
- -- = 0·····
>····· A = Rp*(--- +
)
R1··· R2//R3·· Rp····························· R1··· R2//R3
Substituting t=0
Uin··· Vdd···· Umin
--- +
- ---- + Cp*k*Umin - Cp*k*A = 0
R1··· R2//R3··· Rp
··· Uin··· Vdd···· Umin
··· --- +
- ----
··· R1··· R2//R3··· Rp································ 1
k =
··· Substituting A yields k =
······ Cp*(A - Umin)································ Cp*Rp
Discharge: voltage at outpin = 0
Uin·· Vdd·· Ut·· Ut·· Ut·· Ut····· dUt
--- + --- - -- - -- - -- - -- - 2C*--- = 0
R1··· R3··· R1·· R2·· R3·· R4····· dt
Let Rp = R1//R2//R3//R4 and Cp = 2C then
Uin·· Vdd·· Ut····· dUt
--- + --- - -- - Cp*--- = 0
R1··· R3··· Rp····· dt
Let Ut = Umax*e^(-kt) + B - B*e^(-kt)
dUt
--- = -k*Umax*e^(-kt) + k*B*e^(-kt)
dt
Substituting Ut and dUt/dt
Uin·· Vdd·· Umax·········· B··· B
--- + --- - ----*e^(-kt) - -- + --*e^(-kt) + Cp*k*Umax*e^(-kt) - Cp*k*B*e^(-kt) = 0
R1··· R3···· Rp··········· Rp·· Rp
Substituting t=infinity
Uin·· Vdd·· B······························ Uin·· Vdd
--- + --- - -- = 0·····
>····· B = Rp*(--- + ---)
R1··· R3··· Rp····························· R1··· R3
Substituting t=0
Uin·· Vdd·· Umax
--- + --- - ---- + Cp*k*Umax - Cp*k*B = 0
R1··· R3···· Rp
··· Uin·· Vdd·· Umax
··· --- + --- - ----
··· R1··· R3···· Rp································ 1
k =
··· Substituting B yields k =
···· Cp*(B - Umax)······························· Cp*Rp
Charge: at t=Ts
Ut(Ts) = Umin*e^(-kTs) + A - A*e^(-kTs) = Umax
Discharge: at t=Ts
Ut(Ts) = Umax*e^(-kTs) + B - B*e^(-kTs) = Umin
Subtracting:
-(Umax-Umin)*e^(-kTs) + (A-B) - (A-B)*e^(-kTs) = Umax-Umin
·······································································Vdd
(A-B)*(1-e^(-kTs)) = (Umax-Umin)*(1+e^(-kTs)) = Uripple*(1+e^(-kTs)) = ---*(1+e^(-kTs))
·······································································2^N
·········· Vdd···· Vdd···· ······· 1··· 1··· 1··· Rp
A-B = Rp*(
- ---) = Rp*Vdd*(-- + -- - --) = --*Vdd
··········R2//R3·· R3··· ········ R2·· R3·· R3··· R2
Rp····················· Vdd
--*Vdd*(1 - e^(-kTs)) = ---*(1 + e^(-kTs))
R2····················· 2^N
Removing Vdd and writing out:
Rp·· Rp············ 1···· 1
-- - --*e^(-kTs) - --- - ---*e^(-kTs) = 0
R2·· R2··········· 2^N·· 2^N
·········· Rp··· 1···························· Rp··· 1··· (2^N)*Rp
·········· -- - ---··························· -- + ---··
+ 1
·········· R2·· 2^N··························· R2·· 2^N····· R2
e^(-kTs) =
·····
>····· e^(kTs) =
=
·········· Rp··· 1···························· Rp··· 1··· (2^N)*Rp
·········· -- + ---··························· -- - ---··
- 1
·········· R2·· 2^N··························· R2·· 2^N····· R2
······· Ts······· (2^N)*Rp·········· (2^N)*Rp
k*Ts =
= ln(
+ 1) - ln(
- 1)
······ Cp*Rp········ R2················ R2
Using approximations ln(x+1) = ln(x) + (1/x) and ln(x-1) = ln(x) - (1/x)
·Ts······ 2*R2············································ 2^(N-1)·· 2^(N-1)·· 2^(N-2)
=
·
>· (2^N)*Ts = 2*Cp*R2·
>· Fs =
=
=
Cp*Rp·· (2^N)*Rp··········································· Cp*R2···· 2C*R2···· C*R2
Total conversion time Tc = (2^N)*Ts = 2*Cp*R2 = 4*C*R2
I think I got it right now. Comments please.
regards peter
Post Edited (Peter Verkaik) : 10/19/2007 9:30:24 PM GMT
I'm surprised it doesn't depend on R1. I would have thought it would go with R2/R1
Summarizing:
Given the design parameters Uinmin and Uinmax, and selecting a value for R1,
we can calculate R2, R3 and R4. This leaves C to be determined.
Fs > 2*Fin· (Nyquist)
Fs*Tc = 2^N
C = Tc/(4*R2)
So there are 3 more design parameters: Fs, Tc and N
two of which you can select, the 3rd is then set.
Often Fs is determined by the program and the used oscillator frequency
so you can either select Tc or N.
Edit:
Since the realtime conversion time is in fact given by the actual used Fs and N,
it may be better to leave Tc out of the calculation until Fs and N are set.
Fs*Tc = 2^N· with Tc = 4*C*R2 becomes
Fs*4*C*R2 = 2^N
C = (2^N)/(4*R2*Fs)
So select N·and Fs and calculate C
Select the larger standard C value that is nearest to the calculated value.
(larger to keep the ripple at the summing node within 1 LSB)
Tc = (2^N)/Fs
If·Tc is too large, either decrease N or increase Fs and recalculate C.
regards peter
Post Edited (Peter Verkaik) : 10/20/2007 5:03:44 AM GMT
and found a new condition!
Note on the approximation:
······· Ts······· (2^N)*Rp·········· (2^N)*Rp
k*Ts =
= ln(
+ 1) - ln(
- 1) can be rewritten as
······ Cp*Rp········ R2················ R2
······· Ts·············· R2················ R2
k*Ts =
= ln(1 +
) - ln(1 -
)
······ Cp*Rp········· (2^N)*Rp·········· (2^N)*Rp
Taylor:
ln(1+x)········ = ln(1+(+x)) =· x - (x^2)/2 + (x^3)/3 - (x^4)/4 + ....
ln(1-x)········ = ln(1+(-x)) = -x - (x^2)/2 - (x^3)/3 - (x^4)/4 - ....
ln(1+x)-ln(1-x) = 2x + 2*(x^3)/3 + 2*(x^5)/5 + ....
··············· = 2x * (1 + (x^2)/3 + (x^4)/5 + ....)· where 0 < x < 1
·································· R2····················R2
This gives a new condition: x =
< 1··· ---->··· -- < 2^N
······························· (2^N)*Rp·················Rp
···················· R2
Assuming that x =
is much smaller than 1, then ln(1+x)-ln(1-x) = 2x
················· (2^N)*Rp
·Ts······ 2*R2······················· 2^N
=
····
>···· C =
Cp*Rp·· (2^N)*Rp··················· 4*R2*Fs
If using the approximation ln(1+x)-ln(1-x) = 2x + 2*(x^3)/3 = 2x*(1 + (x^2)/3) then
····· 2^N···· 1············ 1···· R2········ R2
C =
*
· with K = -*(
)*(
)
··· 4*R2*Fs 1 + K·········· 3· (2^N)*Rp·· (2^N)*Rp
From the condition (R2/Rp) < (2^N) follows that when using a small input range
(R1 << R2, and thus Rp << R2) that the minimum N must be increased.
regards peter
Post Edited (Peter Verkaik) : 10/20/2007 12:27:46 PM GMT
Also, I'm think that the RC time on the prop side of C only matters because of imperfections and noise in the quantizer. With larger values of RC, the input pin voltage hovers closer to the Vdd/2 threshold and is more susceptible to noise. On the other side, you can't have RC to small or the voltage there will be often very close to Vdd or Vss and also be susceptible to noise (because a small change in voltage can dramatically change the information stored).
So, I would think you'd want the RC time on the prop side to be a few times the clock period. This way, both the input voltage and feedback voltage can substantially change the capacitor voltage. But, the feedback can keep it away from the Vdd/Vss rails.
So, the one degree of freedom left is absolute value of R (or C) on the prop side. This decides how much current comes out of the Prop output pin. There is a hard upper limit of a few mA. The lower limit is probably also determined by noise. But, more basically, this R determines the R on the input side because we already know the voltage range we want to measure. And, the R on the input side is the input impedance to the ADC. I think this is a more important parameter.
So, here would be the proceedure:
1. Decide on input voltage range to ADC, Vrange.
2. Decide on input impedance to ADC, Zin.
3. Decide on clock frequency of Prop, Fclk.
4. Calculate R1 (prop side) and R2 from Vrange and Zin.
5. Calculate a good C from R1 and Fclk such that R1*C is N times 1/Fclk. (maybe N should be ~8 or so?)
http://www.pulsedpower.net/Applets/Electronics/SigmaDeltaADC/SigmaDeltab.html
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Tracy Allen
www.emesystems.com
I was initially stuck on the first equation, because I didn't realize that Ut is the voltage at the summing junction and that the components are otherwise the same as in the pdf that you posted about 10 messages back, sigmadeltaadc.pdf? The equation is from KCL. Okay.
I'm still l puzzled by the steps that use the equation from KCL. Okay, the solution is a decreasing exponential when the outpin is low and an increasing exponential when the outpin is high. Time constant is k=1/RC in either case, and there is an initial condition. But I'm lost on the the significance of the initial condition parameters A and Umin. I need a picture. The shape of that curve is going to be very dependent on how long the output spends high and low and as in the reference cited by deSilva. The initial conditions can change in a complicated pattern. How do the results of these calculations relate to "conversion time"? Changes of Uin are not even considered.
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Tracy Allen
www.emesystems.com
Post Edited (Tracy Allen) : 10/22/2007 3:49:07 AM GMT
I assumed Uin is at the middle of the input range, Uin = (Uinmax+Uinmin)/2
so Ut hoovers around Vdd/2 each Ts.
Then·the generated digital pulses should have pattern ...10101010...
hence the charge/discharge curves.
regards peter
Post Edited (Peter Verkaik) : 10/21/2007 4:59:03 AM GMT
When the signal path draws "Is" through "Rs", the feed-back will deliver "If = 3V/Rf" for as long as it takes to fill-up
the cap again. So:
Is = If*dutycycle
Note that a sequence of 110 110 110 will effectively deliver If/3 per clock, as 0 is not "nothing" but draws the same amount of charge fed before.
However the voltage at the cap will never change for more than:
dU/dt = If/C = 3V/(Rf*C)
per clock tick.
And so there is no dependency on "C" whatsoever, but only on "Rf*C"
(b) This is a DC analysis, what happens for "changing" signals, a sine wave with frequency "fs"?
Well not much else, as the feed-back compensates each rise along the sine wave as soon as it happens, because it is so much faster ("1/clock >> fs")
But what, if it is not? This is part of Peter's analysis: A higher frequency part in the input signal will be noise or even lead to an unstable feed-back. But when starts "higher"?
As a sine changes most at its zero crossover, the worst case input current per time is "2*pi*fs*mean(Is)"
If this can be compensated for during one or a few clock ticks it would be perfect, if not there will be a noticable "instability" of the cap voltage.
The condition is:
If/clock >= 2*pi*fs*mean(Is)
To care already for even the static case, we always need "If >= mean(Is)" so a sufficient condition for a stable operation should be:
1/clock >= 2*pi*fs
Thus an oversampling of 6 wrt to the highest frequeny part should suffice for a stable operation. Unstability will occur when higher frequency parts occur with high ampitiude, the analysis of which is not trivial....
Of course it will improve the worst case situation to put an additional low pass before the delta sigma, but a much more useful device is a second order delta-sigma modulator. I think there is an example for it in the link I gave...
Post Edited (deSilva) : 10/21/2007 9:46:41 AM GMT
DeSilva,
Actually, I am only looking at the situation that the generated pulse
output is ...01010101...
Uin drops out of the equations when I calculate Uripple at the junction node.
Uripple must comply to
Uripple = Vdd/(2^N) where N is the bit resolution
R3 and R4 only have a limited effect on the calculation for C.
But C does depend on Fs, R2·and bit resolution N.
I also found that R2 must comply to
R2/Rp < 2^N where Rp = R1//R2//R3//R4
Usually R2/Rp << 2^N and that's why R3 and R4 have no big effect on the calculated C.
But it does have an effect on allowable input range. (Step 3 in attached document).
Very small input ranges require a larger N if the input range is shifted up or down,
especially beyond Vdd or when Uinmin < 0.
regards peter
There is never such a situation [noparse]:)[/noparse] much more often occurs
1111111111
or
00000000 This should be no surprise, as it is the LEAST POSSIBLE (quantization) noise for a perfect situation
This is obvious, as you named all degrees of freedom before
Only this range gives the full resolution. When you - say - use just 12.5% of it you have to multiply your N
to get the same resolution again, otherwise you loose 3 bits...
I don't quite understand your last remark. The minimal required N that follows
from step 3 is to keep the ADC working in its lineair area, not to compensate for lost bits.
Even a small input range has full resolution (0 represents Uinmin, (2^N)-1 represents Uinmax).
This N can also be calculated from R2/Rp < 2^N
If R2/Rp >= 2^N then the voltage at the junction cannot be corrected to Vdd/2.
The physical effect is perhaps clearer from
(Uinmax - Uinmin)/2 > Vdd/(2^N)
which leads to the same minimal N.
In words: Half the input range must be greater than 1 LSB
regards peter
It would be neat to measure a thermocouple voltage, however, without amplification it might fall below the noise threshold. Even full scale changes are only on the order of millivolts. Assuming a best case resolution of 14 bits on a full scale span of 3 volts, the least significant bit is 183 microvolts.
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Tracy Allen
www.emesystems.com
When designing an ADC you have to Parameters:
(a) The bandwidth "fs" you want to use: You know from Shannon and Nyquest that you have to sample with a clock tqise as high "1/(2*fs)". There is no way out - this is true and basic mathematics.
(b) The resolution (or granularity) of the amplitude. Due to the character of the delta-sigma process you add small and constant packages of charge to hold the balance. So it takes some TIME; when you count time with a clock you need 2^N clocks to guarantee a stable measurement on an equidistant scale. This in fact is CURRENT you measure.
You say: "Ah, in this period T I send P packages of 2 uCoulomb each, so I fed a current of P/T* 2uCoulomb."
As the pin voltage is constant, the current during the "sent-package-time" is determined by the resistor R2. So there is maximum current, issued when you send the maximum of 2^N packages during T.
Now, as you want to catch some dynamic in the signal, you have to adjust T so that it meets the Shannon/ Nyquest condition.
There are complex noise considerations for highly dynamic signals when 2^N is very small; in one posting above I estimated you can run into problems with 2^N<6.
The only important condition is the current equilibrium, which can be expressed through resistor values when the involved voltages are known. The cap then has to be determined by the Nyquist formula.
There is no relation with N to any of them.
Post Edited (Rayman) : 10/22/2007 12:18:02 PM GMT
It will be interesting to see those thermocouple results. The question of the accuracy attainable with the Prop sigma-delta is still open. We already know that the layout makes a terrific difference, and Chip has even suggested which pin combinations are likely to have the best results, based on the interior layout of the mask.
http://forums.parallax.com/showthread.php?p=677970
The range is decreased when the value of R1 (the input resistor) is small relative to R2 (the feedback resistor). There is a question of where to bias the other side of the thermocouple. It could be biased at or near Vdd/2, so that the output would be centered on 50%. Adding a pullup resistor R3=R1 could push the mid-point down to Vss, but it seems to me that that option would upset the balance, in terms of noise coupled from Vdd. Worth a try though.
An external option is to input the thermocouple into a CAZ op amp (e.g. LTC2054), configured with a transistor as a voltage controlled current source with gain to drive the ADC.
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Tracy Allen
www.emesystems.com
Post Edited (Tracy Allen) : 10/22/2007 7:25:29 PM GMT
I just got it working! Using R1=100k, R2=390, and using a 1K trim pot to pull up to Vdd, I can read a type-K thermocouple voltage. At least, I get about what I think I should...
My little applet (http://www.pulsedpower.net/Applets/Electronics/SigmaDeltaADC/SigmaDeltab.html) tells me I should get a 12.9 mV range with R1=100k,R2=390, and R3=390.
Basic test was to adjust trim pot so that reading is close to 50%. Then, dipped TC in boiling water to read 18%. Then dipped TC in ice water to read 45%. This is a 27% change...
I looked at a table earlier that said the difference should be 4 mV between 0 and 100 degrees C, which should mean a 31% change. I got a 27% change, which is pretty good (I think) considering how basic this setup is...
Of course, you'd need a look-up table to convert to actual temperature...
Nice applet by the way. (note to other readers: R1 and R2 designations in the applet are reversed from the ones in Peter's PDF)
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Tracy Allen
www.emesystems.com
(you can see both ends of the ~1 meter long Type-K thermocouple wire in the photo...)
On my debug screen i just get the same value whatever i do...
@12 bits samplin rate i get "2200-3000" values on the screen going up and down in a fairly slow rate not in anyway linked to the voltage im sending in, im using the standard ADC Appnote hookup to the prop.
Any thoughts?
http://www.rayslogic.com/propeller/Programming/ADC.htm
and see if it gives the same answer...