deSilva: You're speaking in general terms about things I already know... I'm looking for equations for capacitor values based on clock speed, #bits, etc...
So you understand all the elements - why do you ask then? Put them all together!
What do you think the clock speed can have to do with it?
Aha, there is another low pass filter at the Prop feed back pin But do we need to care?
So let's put is this way:
You need a certain charge to change the voltage at a cap:
Q = C * V
The feedback current just tries to do this. It is of no concern in what way: Charge is charge!
So when you want to compensate for a voltage change per time you must not use a capacity that need more current for it than you can deliver:
dQ/dt >= C * dV/dt
approximately:
C <= I/(V * f)
So if your current is limited by a (feed back) resistor R, this is
C <= 1/( f R)
which should not astonish you
Values: f = 10 kHz, R = 100k --> C <= 1nF
On the other hand you have some "latency" or reaction time, before you start your current feed-back business...
This is the "clock". If the source gets a chance to fill up (or empty) the cap before you can intervene, you have lost... However this cannot happen when the clock is much faster than the bandwidth limited signal. Note that the cap C is working as part of this low pass filter, so everything is quite "automatical"
But it is important to adapt the feed back resistor to the input current... When the involved voltages are similar, a current limiting resistor around R will be fine.
The tricky things are to consider parasitary capacities and inductancies...
Post Edited (deSilva) : 10/17/2007 10:03:20 AM GMT
DeSilva: Yes, it's the RC between the prop and the cap that I wondering about...
Let's say R1 is from prop to caps and R2 is from caps to input...
The desired voltage range fixes the ratio of R1 to R2.
The desired frequency response fixes the ratio of R2 to C.
But, what to use for optimal values? R1 is limited on the low end by the rated drive ability of the chip... But, I think there must be a fundamental relationship for optimal R1*C time relative to the Prop sampling rate. It appears that in the Microphone2Vga example and the demo board, they are using an R1*C time equal to the sampling rate.
But, I don't know if this is a good "rule of thumb", or how much it really matters...
I think Rayman put the problem to the point: There is still one degre of freedom you can work with. R*C will be fine, but why not use 100 Ohms and 1 uF?
Indeed, why not?
The only reason I can think of is to generally keep any flow of current as low as noise will allow. But is that not just one of the problems: noise? All right, so shun megohms! But higher currents generate magnetic fields, and inductance is something a hobby electronicist shuns even more
Many considerations go beyond "theory". We need a very "good" cap: Fast switching (80 MHz), little inductance. This costs at higher values...
Parasitic effects are in the order of 10 pF, so we should stay right above 100pF
So I think you could scale C between 10 nF and 100pF, changing the resistors accordingly to 1M or 10k.
Most important is the low pass effect to the signal source!
I am not aware of any impact of the clock. As I said: charge is charge!
So 80MHz worstcase through 100k to 1 nF looks like a NO-OP But it IS loading the cap! This is whats it's all about with low pass filters...
But, I think maybe this degree of freedom is not so free... I've read a little theory that leads me to believe that the RC time on the Prop side is an additional low pass filter on the response (I guess I'm going to have to test this...).
The clock and bits determine the sampling rate, which is a third low pass filter on the response. Generally, one oversamples and then digitally filters to reduce quantization noise.
Sampling rate determines bandwidth because of nyquist (sampling rate must be twice highest frequency component) but for a specific sampling rate I can't see why there would be further low pass filtering effects. Perhaps I'm missing your point.
I tried to make clear that there is no "analogue" low-pass effect to be considered by the feed-back signal. I don't know how to explain it - I tried it twice and Rayman keeps ignoring this
I like the following article.. I must confess I didn't understand it at the first reading some months ago, but after some experience with delta-sigma it makes much sense to me... www.beis.de/Elektronik/DeltaSigma/DeltaSigma.html
I've heard that the choice of RC time constant for the feedback is made so that the voltage at the input will change less than or equal to one bit during one clock period. One bit is equivalent to Vdd/Nbits. E.g., Vdd/4096 for 12 bits. The change during that time is,
(Vdd * clkperiod) / (2 * R * C).
Equating the two makes Vdd drop out and Nbits = 2 * R * C / clkperiod. For example, the demo board uses R=100k and C=1nf, and clkperiod=12.5ns, so Nbits=16000 or about 14 bits. Of course, external noise sources are a separate issue. One could rearrange that formula to calculate the RC required given the number of bits. R is chosen to be large relative to the output resistance of the mosfets.
Now, the thing is, I don't remember where I heard that and I don't see a quick theoretical or rule of thumb explanation for it. In particular, what are the consequences of making it much less or much larger, in terms of speed of transient or frequency response, vs accuracy? I started out on a gedanken experiment, imagining the extremes of zero capacitance and infinite capacitance. In the first case, it turns into a comparator with three possible states (always high, always low, or oscillating at clkfreq), and you have to wait three clock periods (two transitions) to get the first level of confidence in the current state. On the other hand, with infinite capacitance, you have to wait forever to get any information at all. There is a lot of territory between the extremes, and there may be an optimum in there somewhere. Maybe a pretty wide optimum.
One sort of counterintuitive notion is that the step response of the sigma-delta is instantaneous, in the sense that if the input current takes a sudden step, the modulator pattern immediately alters to the new one appropriate to the new current, however, it takes time for the observer of the bit stream to realize that the pattern has changed. For example, if the input step is from Vdd/2 to 2*Vdd/3, then the modulator immediately shifts from the 1:1 pattern to the 2:3 pattern and the observer can realize part of that change in only a few cycles, but it will take many more cycles for the observer to obtain enough information to determine if the input is really something not exactly 2:3 but say more like 200:303.
@deSilva, that is a very nice reference in Elektronik, thanks. It is true as the author says that a lot of the material written is opaque, and alternative glib explanations can miss a lot of the counterintuitive nature of delta-sigma (or sigma-delta if you prefer). The article however gives little insight about the pending question of how to choose the capacitors for the Prop. Opaque too in that respect.
Thanks Tracy. I think this is close to saying that the RC time on the Prop side is equal to (some factor times) the sample period, where the sample period is clock period*2^SampleBits, right?
Tracy, you may well have read it in the SX forum.
I posted some ADC calculations there once.
Attached is a reworked text that has the outcome you mentioned.
Edit: I forgot to edit the line below the diagram.
New file attached.
regards peter ·
Post Edited (Peter Verkaik) : 10/17/2007 7:42:51 PM GMT
Well, I've experimentally found that very large capacitor values still work when you average a large number of samples together to get the result, but individual samples are all either 0, 50, or 100% ...
Just tried it with no capacitors at all:· Still works!· Maybe even less noisy than with the 1nF caps!
@Rayman, @Tracy: I am happy to hear that you are slowly converging to the opinion I try to express for nearly a day now. I know those situation. Someone explains something that is not quite obvious to you, you say "No, that cannot be the case, look this is why..." then your own awareness process starts, and after some rearrangements of your own notions you sometimes find the same words as the person who - seemingly in vain - tried to explain it to you.
This is sometimes the situation I find myself here in this a forum. I read a posting, and I think: "But these are my words from two postings above", "But I explained this to him in the beginning, didn't I?"
So to summarize: Yes this is all so, and there is no "I have heard" and "Why, even without an external cap".
The question of "work" has to include "noise" and "aliasing". This is why I found the referenced article quite instructive.....
All explanations lead to the same conclusions.
(a) Classically considering the input RC combination as a lowpass filter, after which the signal is - logically! - sampled with twice the filter frequenciy
(b) More in the spirit of the delta-sigma theory seeing the cap as an "incremental" integrator, needing just enough capacity to hold the charge swing during one clock cycle.
I said above that - as the clockfrequency even for 2 bit conversion is many times the signal bandwidth, we need not bother with it.
This however was wrong! It refered to the situation that the signal is in fact already bandwidth limited. But this is not necessarily the case. It is it AFTER the RC lowpass, but not IN THE PROCESS of being compensated for by the feed-back clock pulses!
So the "oversampling" is (also) needed to be fast enough to compensate for the higher frequency parts of the signal.
So the reasoning is that:
(1) Tell me the bit resolution you need
(2) I tell you the oversampling needed for it (2^N)
(3) Tell me your clock rate
(4) I tell you the bandwidh you can handle, in terms of f and RC
(5) You tell me your pet values for the Rs (low current at the Prop, other considerations at the signal output)
(6) I tell you the C
@Rayman:· I already made a dual ADC object for use with my touch screen driver.· Works great, and I used through-hole components as well.·· My effective range on the touch screen is about 20% to 80% of the voltage range, but that does seem to be adequate.· I included a routine in the touch screen object to calebrate it using screen coordinates and corresponding touch readings.
I have included it again here in case anyone's interested.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
The more I know, the more I know I don't know.· Is this what they call Wisdom?
Post Edited (Ken Peterson) : 10/17/2007 11:54:58 PM GMT
Peter,
My analysis was very similar to yours, although I cheated. I linearized the charging curve in the limit of a one bit change around Vdd/2. That is easier but not as general as the RC exponential that you solved.
from
I = C dV/dt
rearrange
dV = I dt / C
and substitute I = (Vdd/2)/R for the incremental current around the sig-delta set point in the Prop.
dV = Vdd*dt / (2*R*C)
and then require dV to be a change of one bit, i.e., dV = Vdd/Nbits where Nbits = 2^bits
and dt is the duration of on time slot, e.g. 12.5ns on a Prop at 80 mhz
Vdd/Nbits = Vdd * dt / (2 * R * C)
and then rearrange,
R * C = dt Nbits /2 = dt * 2^(bits-1)
That is the same as your result using the exponentials. I'm not sure where I first became aware of this analysis. Maybe I cooked it up out of thin air, or maybe i saw your earlier post, or maybe I am "slowly converging to the opinion (the estimable deSilva) try to express for nearly a day now" It seems like a reasonable thing to do, but despite the calculation I am not on a solid footing of why it is(?) correct and what metric to use for a further sensitivity analysis.
I find it most productive to have things explained from several different angles, beginner's mind. There is always the possibility that there is a clear explanation for things when stripped down to fundamentals. Also there is the possibilty that fundamental aspects of a tricky problem like this have never been explored.
@Tracy , thank you for your remark(s)
I can even FEEL your uneasiness in this simple matter.... I think I also looked at the system diagrams with the same uneasiness some months ago.
And then it made sense suddenly :
- The "Adder" - oh, yes thats where the both currents (!) from the input and the feedback through these high value resistors meet. And the counter issues an inverted pulse at the feed-back pin in this mode - how clever they thought of that!
- The "Integrator" - oh, yes: a cap of course. But does it really integrate? Just "a little bit", it gives a stabilized point of voltage reference in the first place, around the trigger threshold.... It could be called a "virtual integrator" for this reason. So its value only matters wrt its "swing" around this point of reference, a "swing" due to the high frequency parts of the signal - the parts much above(!) the used bandwidth, that will not be eliminated immediately by the "overclocked" feed-back pulses. Oh, I really "see" the noise here And how it vanishes by oversampling...
- The "Comparator" - oh, yes: Very good thinking to have inputs switching straight at Vdd/2
- The "Sample and Hold", well thats what a counter is made for
- The "Feed-back" - oh, yes - an ingenious design of an seemingly "exotic" counter mode!
Rayman said...
Just tried it with no capacitors at all: Still works!
Maybe my answer to that got lost... You are using the 6 to 10 pF Propeller input pin capacitance. This is fine, as the formula derived above just says
C <= something
When you have no "natural" highter frequency parts (as with your quasi static pot) then the missing low pass will do no harm.
Post Edited (deSilva) : 10/18/2007 11:20:15 AM GMT
Rayman said...
Well, I've experimentally found that very large capacitor values still work when you average a large number of samples together to get the result, but individual samples are all either 0, 50, or 100% ...
And I also forgot to answer to this...
This is not so much an effect of the cap, but you have a changed RC now! The formula said:
C < 1 nF for 10kHz
So when using - say: 10uF - you have an immense latency of 1 second! There is no useful information within smaller intervals.
In other words: It takes time to recharge such a large cap through such high resistors.
I am sure you have not changed the resistors; to have the old situatioin again you should change them to 100 Ohms, needing a buffering for the input...
Post Edited (deSilva) : 10/18/2007 11:18:08 AM GMT
This seems to make a lot of sense to me now.· The frequency response of this ADC is fundamentally limited by the Nyquist frequency, which is half the sampling rate = 1/(dt*Nbits).· So, in order not to reduce the frequency response, we·want the cutoff frequency, 1/(2PI*RC), to be about the same.
But, why you wouldn't want an even smaller value for RC isn't perfectly clear to me...· I suppose this would have something to do with the effective number of bits of the digitization...
R*C = Ts*2^(N-1) = (2^(N-1))/Fs where Fs = 1/Ts is the sample frequency
The condition is in fact
R*C >= (2^(N-1))/Fs
and it assures the accuracy is within 1 LSB every DAC pulse.
The second condition for R*C is determined by the input bandwidth
R*C = 1/(2*pi*Fi) where Fi is the highest input frequency.
So if you have a given input bandwidth, calculate R*C and
adjust Fs and/or the resolution N to match the first condition.
If you have a given Fs, you can calculate what input bandwidth
you can use at specific resolutions.
Peter, I tried using a really big C, and it didn't work very well... Individual samples all had values of 0, 50, or 100%. (This is with DC input)
So, I think there must be some upper limit on RC as well, regardless of the input frequency.
I used >= in the first condition to make clear
it is the lowest possible value to use.
It does not mean you can increase the C
value to any extent, as deSilva explained a few
posts earlier, without decreasing the resistors.
So the RC value to use is the nearest value above
the calculated value, that you can easily create
from standard resistor and capacitor values.
Nice.
Just a few remarks.
You mention Ts = (2^N - 1)/Fs (3rd equation)
I assume you mean to calculate C*R there
which is (2^(N-1))/Fs
Also, that formula is only valid when R1=R2 (R = R1/2) and C1=C2 (C = 2*C1)
then C*R = (2^(N-1))/Fs
I have not checked it but with different R1 and R2, I guess R equals (R1*R2)/(R1+R2)·.
Since C1 = C2 all the time, just name both capacitors C.
Ts there is just that given by the #bits and the clock frequency. And, Fs is just the inverse of this.
I want to add something about this (2^(N-1))/Fs, but I still coming to grips with it... Instead, I just put in the frequencies corresponding to R1*2*C and R2*2*C. If I figure this stuff out, I'll put in what you and Tracy are saying...
I did actually come up with this level shifter idea myself yesterday! Actually, since the voltage between the caps is kept fixed at Vdd/2, things are a lot like the situation with opamps... So, you can form an analog summer by just bringing in any number of voltages through resistors.
That level shifter is a 3-way summer, summing the input/R2, Vdd/R3, and Vss/R4...
Comments
What do you think the clock speed can have to do with it?
Aha, there is another low pass filter at the Prop feed back pin
Post Edited (deSilva) : 10/17/2007 9:10:15 AM GMT
You need a certain charge to change the voltage at a cap:
Q = C * V
The feedback current just tries to do this. It is of no concern in what way: Charge is charge!
So when you want to compensate for a voltage change per time you must not use a capacity that need more current for it than you can deliver:
dQ/dt >= C * dV/dt
approximately:
C <= I/(V * f)
So if your current is limited by a (feed back) resistor R, this is
C <= 1/( f R)
which should not astonish you
Values: f = 10 kHz, R = 100k --> C <= 1nF
On the other hand you have some "latency" or reaction time, before you start your current feed-back business...
This is the "clock". If the source gets a chance to fill up (or empty) the cap before you can intervene, you have lost... However this cannot happen when the clock is much faster than the bandwidth limited signal. Note that the cap C is working as part of this low pass filter, so everything is quite "automatical"
But it is important to adapt the feed back resistor to the input current... When the involved voltages are similar, a current limiting resistor around R will be fine.
The tricky things are to consider parasitary capacities and inductancies...
Post Edited (deSilva) : 10/17/2007 10:03:20 AM GMT
Let's say R1 is from prop to caps and R2 is from caps to input...
The desired voltage range fixes the ratio of R1 to R2.
The desired frequency response fixes the ratio of R2 to C.
But, what to use for optimal values? R1 is limited on the low end by the rated drive ability of the chip... But, I think there must be a fundamental relationship for optimal R1*C time relative to the Prop sampling rate. It appears that in the Microphone2Vga example and the demo board, they are using an R1*C time equal to the sampling rate.
But, I don't know if this is a good "rule of thumb", or how much it really matters...
Indeed, why not?
The only reason I can think of is to generally keep any flow of current as low as noise will allow. But is that not just one of the problems: noise? All right, so shun megohms! But higher currents generate magnetic fields, and inductance is something a hobby electronicist shuns even more
Many considerations go beyond "theory". We need a very "good" cap: Fast switching (80 MHz), little inductance. This costs at higher values...
Parasitic effects are in the order of 10 pF, so we should stay right above 100pF
So I think you could scale C between 10 nF and 100pF, changing the resistors accordingly to 1M or 10k.
Most important is the low pass effect to the signal source!
I am not aware of any impact of the clock. As I said: charge is charge!
So 80MHz worstcase through 100k to 1 nF looks like a NO-OP
Post Edited (deSilva) : 10/17/2007 4:30:44 PM GMT
But, I think maybe this degree of freedom is not so free... I've read a little theory that leads me to believe that the RC time on the Prop side is an additional low pass filter on the response (I guess I'm going to have to test this...).
The clock and bits determine the sampling rate, which is a third low pass filter on the response. Generally, one oversamples and then digitally filters to reduce quantization noise.
What is this theory you have read?
Graham
I like the following article.. I must confess I didn't understand it at the first reading some months ago, but after some experience with delta-sigma it makes much sense to me...
www.beis.de/Elektronik/DeltaSigma/DeltaSigma.html
Post Edited (deSilva) : 10/17/2007 3:33:41 PM GMT
(Vdd * clkperiod) / (2 * R * C).
Equating the two makes Vdd drop out and Nbits = 2 * R * C / clkperiod. For example, the demo board uses R=100k and C=1nf, and clkperiod=12.5ns, so Nbits=16000 or about 14 bits. Of course, external noise sources are a separate issue. One could rearrange that formula to calculate the RC required given the number of bits. R is chosen to be large relative to the output resistance of the mosfets.
Now, the thing is, I don't remember where I heard that and I don't see a quick theoretical or rule of thumb explanation for it. In particular, what are the consequences of making it much less or much larger, in terms of speed of transient or frequency response, vs accuracy? I started out on a gedanken experiment, imagining the extremes of zero capacitance and infinite capacitance. In the first case, it turns into a comparator with three possible states (always high, always low, or oscillating at clkfreq), and you have to wait three clock periods (two transitions) to get the first level of confidence in the current state. On the other hand, with infinite capacitance, you have to wait forever to get any information at all. There is a lot of territory between the extremes, and there may be an optimum in there somewhere. Maybe a pretty wide optimum.
One sort of counterintuitive notion is that the step response of the sigma-delta is instantaneous, in the sense that if the input current takes a sudden step, the modulator pattern immediately alters to the new one appropriate to the new current, however, it takes time for the observer of the bit stream to realize that the pattern has changed. For example, if the input step is from Vdd/2 to 2*Vdd/3, then the modulator immediately shifts from the 1:1 pattern to the 2:3 pattern and the observer can realize part of that change in only a few cycles, but it will take many more cycles for the observer to obtain enough information to determine if the input is really something not exactly 2:3 but say more like 200:303.
@deSilva, that is a very nice reference in Elektronik, thanks. It is true as the author says that a lot of the material written is opaque, and alternative glib explanations can miss a lot of the counterintuitive nature of delta-sigma (or sigma-delta if you prefer). The article however gives little insight about the pending question of how to choose the capacitors for the Prop. Opaque too in that respect.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Tracy Allen
www.emesystems.com
If you're still out there, I've just posted my own dual-adc object code. Might help you with yours...
Ray
I posted some ADC calculations there once.
Attached is a reworked text that has the outcome you mentioned.
Edit: I forgot to edit the line below the diagram.
New file attached.
regards peter
·
Post Edited (Peter Verkaik) : 10/17/2007 7:42:51 PM GMT
Just tried it with no capacitors at all:· Still works!· Maybe even less noisy than with the 1nF caps!
This is sometimes the situation I find myself here in this a forum. I read a posting, and I think: "But these are my words from two postings above", "But I explained this to him in the beginning, didn't I?"
So to summarize: Yes this is all so, and there is no "I have heard" and "Why, even without an external cap".
The question of "work" has to include "noise" and "aliasing". This is why I found the referenced article quite instructive.....
All explanations lead to the same conclusions.
(a) Classically considering the input RC combination as a lowpass filter, after which the signal is - logically! - sampled with twice the filter frequenciy
(b) More in the spirit of the delta-sigma theory seeing the cap as an "incremental" integrator, needing just enough capacity to hold the charge swing during one clock cycle.
I said above that - as the clockfrequency even for 2 bit conversion is many times the signal bandwidth, we need not bother with it.
This however was wrong! It refered to the situation that the signal is in fact already bandwidth limited. But this is not necessarily the case. It is it AFTER the RC lowpass, but not IN THE PROCESS of being compensated for by the feed-back clock pulses!
So the "oversampling" is (also) needed to be fast enough to compensate for the higher frequency parts of the signal.
So the reasoning is that:
(1) Tell me the bit resolution you need
(2) I tell you the oversampling needed for it (2^N)
(3) Tell me your clock rate
(4) I tell you the bandwidh you can handle, in terms of f and RC
(5) You tell me your pet values for the Rs (low current at the Prop, other considerations at the signal output)
(6) I tell you the C
Post Edited (deSilva) : 10/17/2007 8:46:16 PM GMT
I have included it again here in case anyone's interested.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
The more I know, the more I know I don't know.· Is this what they call Wisdom?
Post Edited (Ken Peterson) : 10/17/2007 11:54:58 PM GMT
My analysis was very similar to yours, although I cheated. I linearized the charging curve in the limit of a one bit change around Vdd/2. That is easier but not as general as the RC exponential that you solved.
That is the same as your result using the exponentials. I'm not sure where I first became aware of this analysis. Maybe I cooked it up out of thin air, or maybe i saw your earlier post, or maybe I am "slowly converging to the opinion (the estimable deSilva) try to express for nearly a day now" It seems like a reasonable thing to do, but despite the calculation I am not on a solid footing of why it is(?) correct and what metric to use for a further sensitivity analysis.
I find it most productive to have things explained from several different angles, beginner's mind. There is always the possibility that there is a clear explanation for things when stripped down to fundamentals. Also there is the possibilty that fundamental aspects of a tricky problem like this have never been explored.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Tracy Allen
www.emesystems.com
I can even FEEL your uneasiness in this simple matter.... I think I also looked at the system diagrams with the same uneasiness some months ago.
And then it made sense suddenly :
- The "Adder" - oh, yes thats where the both currents (!) from the input and the feedback through these high value resistors meet. And the counter issues an inverted pulse at the feed-back pin in this mode - how clever they thought of that!
- The "Integrator" - oh, yes: a cap of course. But does it really integrate? Just "a little bit", it gives a stabilized point of voltage reference in the first place, around the trigger threshold.... It could be called a "virtual integrator" for this reason. So its value only matters wrt its "swing" around this point of reference, a "swing" due to the high frequency parts of the signal - the parts much above(!) the used bandwidth, that will not be eliminated immediately by the "overclocked" feed-back pulses. Oh, I really "see" the noise here
- The "Comparator" - oh, yes: Very good thinking to have inputs switching straight at Vdd/2
- The "Sample and Hold", well thats what a counter is made for
- The "Feed-back" - oh, yes - an ingenious design of an seemingly "exotic" counter mode!
Post Edited (deSilva) : 10/18/2007 9:30:35 AM GMT
C <= something
When you have no "natural" highter frequency parts (as with your quasi static pot) then the missing low pass will do no harm.
Post Edited (deSilva) : 10/18/2007 11:20:15 AM GMT
This is not so much an effect of the cap, but you have a changed RC now! The formula said:
C < 1 nF for 10kHz
So when using - say: 10uF - you have an immense latency of 1 second! There is no useful information within smaller intervals.
In other words: It takes time to recharge such a large cap through such high resistors.
I am sure you have not changed the resistors; to have the old situatioin again you should change them to 100 Ohms, needing a buffering for the input...
Post Edited (deSilva) : 10/18/2007 11:18:08 AM GMT
But, why you wouldn't want an even smaller value for RC isn't perfectly clear to me...· I suppose this would have something to do with the effective number of bits of the digitization...
A smaller RC will bring you into aliasing trouble...
Post Edited (deSilva) : 10/18/2007 1:53:45 PM GMT
I actually have mine working now. It turns out that when you have everything soldered properly and neatly, things work much better.
The condition is in fact
R*C >= (2^(N-1))/Fs
and it assures the accuracy is within 1 LSB every DAC pulse.
The second condition for R*C is determined by the input bandwidth
R*C = 1/(2*pi*Fi) where Fi is the highest input frequency.
So if you have a given input bandwidth, calculate R*C and
adjust Fs and/or the resolution N to match the first condition.
If you have a given Fs, you can calculate what input bandwidth
you can use at specific resolutions.
regards peter
So, I think there must be some upper limit on RC as well, regardless of the input frequency.
it is the lowest possible value to use.
It does not mean you can increase the C
value to any extent, as deSilva explained a few
posts earlier, without decreasing the resistors.
So the RC value to use is the nearest value above
the calculated value, that you can easily create
from standard resistor and capacitor values.
regards peter
http://www.pulsedpower.net/Applets/Electronics/SigmaDeltaADC/SigmaDelta.html
to help look at things...
Just a few remarks.
You mention Ts = (2^N - 1)/Fs (3rd equation)
I assume you mean to calculate C*R there
which is (2^(N-1))/Fs
Also, that formula is only valid when R1=R2 (R = R1/2) and C1=C2 (C = 2*C1)
then C*R = (2^(N-1))/Fs
I have not checked it but with different R1 and R2, I guess R equals (R1*R2)/(R1+R2)·.
Since C1 = C2 all the time, just name both capacitors C.
regards peter
Original german page:
http://www.sprut.de/electronic/pic/programm/compadc/compadc.html
Translated to english by google page:
http://www.google.com/translate?u=http%3A%2F%2Fwww.sprut.de%2Felectronic%2Fpic%2Fprogramm%2Fcompadc%2Fcompadc.html&langpair=de%7Cen&hl=en&ie=UTF8
The above pages are based upon the Microchip appnote AN700:
http://www.e-sonic.com/whatsnew/Microchip/signal/AN700.pdf
regards peter
Post Edited (Peter Verkaik) : 10/18/2007 7:13:05 PM GMT
Ts there is just that given by the #bits and the clock frequency. And, Fs is just the inverse of this.
I want to add something about this (2^(N-1))/Fs, but I still coming to grips with it... Instead, I just put in the frequencies corresponding to R1*2*C and R2*2*C. If I figure this stuff out, I'll put in what you and Tracy are saying...
I did actually come up with this level shifter idea myself yesterday! Actually, since the voltage between the caps is kept fixed at Vdd/2, things are a lot like the situation with opamps... So, you can form an analog summer by just bringing in any number of voltages through resistors.
That level shifter is a 3-way summer, summing the input/R2, Vdd/R3, and Vss/R4...
Ray