Troubles with Sigma-Delta ADC

slosjo

Hello all-

I am trying to implement a Sigma-Delta ADC object into my code.· After I call the ADC object, I am using PropTerminal to monitor·a variable being set by the ADC.· The results are not what they should be and·I'm not sure what I am doing wrong or weather it is a software or hardware issue.· If anyone is interested in offering up some advice, let me know and I will send you my code and/or elaborate more on my problem.·

Thanks



·

Mike Green

Please post your code and your schematic as well as a description of what problem you're seeing. The Sigma-Delta ADC is sensitive to switching noise and the components need to be mounted close to the Propeller if you're going to run it at high speed (as the ADC object does).

Rayman

I was just thinking that the electret microphone circuit on the propeller demo board is something of a sigma-delta ADC... It uses P8 as a 1-bit quantizer, P9 and the 100k resistor as the 1-bit DAC and the 1-nF caps as the integrator/summer. Is this what you are doing? Or, do you have an external IC for it?

slosjo

That is basically what I am doing. The analog input is the voltage across a potentiometer which ranges from about 0.4VDC to about 3VDC. This goes through a 150K resistor and then to an input pin. Connected to the input pin are also 2 - 1nF ceramic caps, one going to VSS and the other to VDD. There is a 100k resistor going from the input pin to a feedback pin. I connected everything on the prototype board to the pin access holes around the outside of the prop.

Rayman

Then, it sounds like you could just borrow code from the "Microphone2VGA" example that digitizes the microphone. Parallax has made good use of counter module to do the digitization.

slosjo

I looked at that code, and I think that I have it working now, at least sort of. I may have more questions shortly.

Thanks

slosjo

Well it looks as though my ADC is not working as well as I thought.· The value is supposed to be between 0 and 255, and I am getting some change in the value as I change the pot, but it's not very stable, and not·even close to 255.· I have attached the ADC code and hardware specifics·that i'm using if anyone would like to have a look.

Thanks



Post Edited (slosjo) : 9/21/2007 6:36:38 PM GMT

Mike Green

The ADC code is pretty straightforward and looks fine.

Try slowing everything down. Instead of using an 80MHz clock, try a 40MHz clock, then a 20MHz clock, etc. by changing _clkmode to pll8 or pll4, etc. If the problem is noise or reflections, etc., slowing down the clock should help. The serial debug routines should adjust their timing since the clkfreq function is normally used to calculate timing for drivers that are speed dependent.

slosjo

Ahhh good call Mike.· That helped a lot with the stability issue, but I'm still not getting the range that I should.· I changed my sample bits to 8, so I should be getting a range from just over 0 to just under 255.· I'm getting something like 20 or so to about 70.· My voltages on the analog input pins are about 0.4 - 2.8.· Also, should I be doing x := getvalues.read1 >>2· ?

Rayman

Isn't that 150k resistor way too big?·

What is the resistance of your pot?· It need to be much smaller that 150k...

Post Edited (Rayman) : 9/21/2007 7:27:15 PM GMT

slosjo

The pot is a max of about 5.5k

Rayman

Maybe replace the 150k with 100k. I think then that when Vin is VCC, the ADC input pin will be at Vcc/2. Right now, if the ADC input were all 1s then the feedback would be a constant 0 and the ADC input voltage would be Vcc/2.5, below the trigger threshold of Vcc/2.

slosjo

That makes sense. I will give it a try, thank you very much.

Mike Green

slosjo,
You're not going to get a range from 0 to 3.3V. Actually, 0.4 to 2.9 sounds pretty good. Don't forget that the output (feedback) pin doesn't really switch from 0 to 3.3V. There are some voltage drops in the output switching transistors. If it's important to get a wider range, you could use an op-amp on the input to the ADC with an offset of about 0.4V and less than unity gain. That would transform a range of 0-3.3V to something more like the 0.4-2.9V that the ADC can handle.

The ">> 8" I suggested before was based on your using 14 bit resolution and was just a way to focus on the significant bits (given the noise involved). You could leave out the shift entirely if you think the numbers you're seeing are valid.

Tracy Allen

Hi slosjo,

I'd posted a circuit analysis for Prop Sigma-Delta at
this link.
It might help with the choice of resistors for the range.
With 100k for feedback and 150k for input, and a prop threshold of 1.65 volts nominal, the range calculated range should be a count of 68 at 2.8 volts input up to a count of 191 at 0.4 volts input.

count = (2^bits) * (1.65*(R1+R2) - (R2 * Vin)) / (3.3 * R1)
R1=input ohms
Vin=input voltage
1.65=threshold voltage
3.3=Vdd-Vss
bits=bits in result, eg WAITCNT N=256 cycles for 8 bit result
count= change in phsx register in N cycles, result.

I don't know why you're only seeing 20 to 70. You asked if you should be "doing x := getvalues.read1 >>2 ?". I don't think so. Why?

P.S. Edited it to use the names stated. I had first posted it with cell references from an Excel spreadsheet. As Mike points out, the result depends too on the drive capabilities of the totem pole output transistors and on the exact threshold level of the input transistors.

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Tracy Allen
www.emesystems.com

Post Edited (Tracy Allen) : 9/21/2007 11:50:30 PM GMT

Rayman

Anybody know why we need 1nF caps to both VCC and ground? Wouldn't just one 2nF cap to ground do exactly the same thing? I don't get it...

Phil Pilgrim (PhiPi)

It helps to reduce the effects of noise on Vdd. Since the input threshold is Vdd/2 at any particular instant, a capacitive divider will keep the sampling node at this level in a noisy environment better than just a capacitor to ground would.

-Phil

Tracy Allen

As Phil pointed out, the Prop has a CMOS threshold of Vdd/2. It is not a TTL type threshold referenced to ground. The double capacitor technique is predicated on having equal levels of noise on both Vdd and Vss, so both squeeze in or stretch out at the same time. That is what you might expect from pulses of current that pass through equal wiring resistances on their way into the Vdd and out of the Vss pins. But it won't do so much good if the wiring is haphazard, or if there is high current sourcing and sinking happening at other Prop I/O pins, being reflected unequally on the two supplies at the points where they feed the two ADC capacitors. The idea is to keep the wiring short and to consider what would generate noise across those capacitors or the signal source. Here are two threads that are informative about these issues:
Initial efforts, bad results halfway down the thread, Chip is puzzled too.
Chip got it working!
The ADC circuit on the new demo board reflect those insights.

Remember too that the sigma-delta technique causes the input pin to hover exactly at its input threshold. Both input transistors are partly turned on. According to Chip, the input transistors have a relatively small geometry, and by my measurement the totem pole current due to them hovering at threshold is around 1 or 1.5 milliamps. That fluctuates wildly as the sigma-delta action is taking place, alternately driving the pin just below and just above threshold. That is another reason to to pay close attention to the layout, and that is especially true when the clock frequency is high.

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Tracy Allen
www.emesystems.com

slosjo

Hello all-

I just read Chip Gracey's example about Sigma Delta ADC conversion and he said that he used surface mount components extremely close to the pins. Has anyone done a successful sigma delta using the holes surrounding the·propeller·on the prototype board to connect their inputs and capacitors? If so, please elaborate on the specifics of your connections because I am having troubles with mine and still getting very unstable results.

Thanks

Post Edited (slosjo) : 9/24/2007 1:32:40 PM GMT

deSilva

Some aspects of ADC are still a "black art". I know this remark is not particularly helpful, but should be taken as a warning to expect too much of a "low cost solution" when going > 10 kHz.

Maybe using a "real" comparator rather than a Prop pin will improve things much (reasons for this given by Tracy)
Absolutely stable power supply is a "must": Do you have at least 200nF close at the Prop power pins?

slosjo

I have a 1nF cap going to VDD and a 1 nF cap going to VSS(through hole ceramic caps). I connected them to the analog input pins' access hole on the prototype board and cut the leads as short as physically possible. I used these values because they were suggested by the author of the ADC code that I posted above.

deSilva => "Absolutely stable power supply is a "must": Do you have at least 200nF close at the Prop power pins?"

Are you referring to the caps I described above, connected to the analog input pin?

cgracey

Here are some other things to consider...

Output/direction signals for pins 0-15 run right-to-left on the die, going through OR gates beginning with Cog7 and ending at Cog0. So Cog0 has the shortest drive path to pins 0-15. Furthermore, the last series OR coming from Cog0 has very short wires to pins·7 and 8. So, having a low-numbered cog drive pins physically close to Cog0 is very low-latency, which matters greatly at 80MHz, but not at 40MHz.

Conversely, output/direction signals·for·pins 16-31 run left-to-right on the die, going through OR gates beginning with Cog0 and ending with Cog7. So, Cog7 has the shortest drive path to pins 16-31. And from Cog7, the wires connecting to pins 23 and 24 are quite short, keeping latency minimal.

This right-to-left·and left-to-right arrangement was to keep worst-case wiring lengths at half of what they would have been, had all pin-control signals·begun at Cog0 and ended at Cog7, or vice-versa. even so, the worst-case output/direction signal delay through 7 cogs is only about 1.5ns.

For inputs, all cogs see the same signals at the nearly the same time, as there are no series-gate delays. There is a slightly increasing wire delay from pin 7 down to 0, pin 8 up to 15, pin 23 down to 16, and pin 24 up to 31. The·worst-case input signal wiring delay·is about 500ps. These wiring delays affect both inputs and output signals.

So, the best sigma-delta cog/pin combinations would be Cog0 using pins 7 and 8, and Cog7 using pins 23 and 24.

There is one more source of delay, and that is the I/O pad, itself. It takes about 500ps to translate an input to a driven internal signal which goes to all the cogs. It takes about 700ps to translate an output signal to a pad voltage. This means that the best case output-to-input loop delay is ~1.2ns (700ps + 500ps). The worst case is that value plus max wiring delays both directions and 1.5ns for 7 series-ORs. This would sum to 4ns. That's a big chunk of a 12.5ns (80MHz) cycle and it eats greatly·into the feedback time.

What can really mess things up are parasitic capacitances and inductances due to PCB/breadboard wiring. They make the on-chip delays seem like nothing. If you look at the microphone·layout on the Propeller Demo Board, you'll see that wires were kept to just a few millimeters and small SMT parts were used. Also, pins 8 and 9 were chosen to keep on-chip wire delays to a minimum, especially when driven with a low-numbered cog.

And as was said earlier, having identical sigma-delta filter caps to both VSS and VDD keep power supply noise balanced at the input. This makes a big difference·over having·just·one to VSS or one to VDD.


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Chip Gracey
Parallax, Inc.

Post Edited (Chip Gracey (Parallax)) : 9/25/2007 5:36:31 AM GMT

deSilva

slosjo said...
Are you referring to the caps I described above, connected to the analog input pin?

Funny idea - I was referring to a 100 to 200nF cap between the POWER pins, close to the chip! From your words I assume you have none :-(

Rayman

I just went to work on a dual-ADC in single COG object this morning and already have it working [noparse]:)[/noparse] Started from the Microphone2VGA example. I'm using fairly long leads on the Prop demo board proto area and it seems to be working fine... Now, just need to add a VGA GUI...

Rayman

One thing I'm not clear on is how to select values for the two capacitors of the divider... It seems that Parallax picked values that, with the feedback resistor, give an RC time of 200us, about the same as the sample period at 12-bits, as in the demo. But, I'm not sure if they did this on purpose, or how much it really matters...

Anybody up on Sigma-Delta ADC theory?

deSilva

First order Delta-Sigma modulation is not such a black art. You will find some explanations here in some threads (see Tracy's resistor computations) as well as all over the web...

The basic idea is - looking at the Demo Board circuit - to keep the cap(s) at some voltage level (Vdd/2 to be precise) by feeding it exactly enough current from the Prop (or drawing from it) as is drawn from/fed to the external source. This is accomplished by some sort of PWM (>50%: feeding, <50% drawing). The program logic is another thing but the "electrical" idea is quite simple. So to be able to fast react to a change of voltage the cap must not be too large, as you might not be able to provide the needed charge by your pulses. On the other hand a tiny cap will not allow you to use the full pulse width of your signal, thus reducing the possible dynamic range.

Allowing a full voltage swing each T will require a C around T/2R; a smaller cap will reduce the dynamic, a larger will generate distortion at higher frequencies (low pass characteristic)

The R at the Prop feedback pin depends on the situation at the signal source - you have to adapt to its output impedance.. See Tracy's computations...

Post Edited (deSilva) : 10/16/2007 11:35:02 PM GMT

Rayman

The way I'm looking at it is that the voltage between the capacitors is fixed at Vdd/2. The Prop is then a variable current source that feeds these capacitors to maintain the voltage. The maximum current into the capacitors is Imax=(Vdd-Vdd/2)/R1 and the minimum current is Imin=-(Vdd/2)/R1 (where R1 is the resistor between the Prop output pin and the capacitors). This current is exactly balanced by Iin from the voltage source being measured, limited by the resistor between it and the caps, R2, so Iin=Vin/R2. You can find the upper limit in Vin by equating Iin and Imax and the lower limit in Vin by equating Iin and Imin.

But, what I don't know is how to pick the best value for the capacitors [noparse]:)[/noparse]

deSilva

Have you read my posting above?

Rayman

Yes, but I'm still not sure what to do for capacitor values... I guess I'll try equating the RC time on the prop side to the sampling period (while making sure the RC time on the input side is fast enough for the input frequency...)

deSilva

Funny man! I told him that his damned cap and the output impedance of his signal source form a low pass, and that the feed back resistor has to be choosen so that the Prop can "equalize" the charge flow.
And he says he is unsure how to chose the capacity. Sigh....

Graham Stabler

deSilva,

You shouldn't get upset when people don't seem to read or understand your posts, it's not always their fault, sometimes your posts are hard to understand for a variety of reasons (readers technical background, English, formatting, "comedy").

Having said that it's important to spend at least as much time reading replies as the person spent typing them.

Graham