Thanks, Everyone, for participating today. I probably only saw a small fraction of what you were posting, text wise. It was something that at the end of the day it started working. I really need to review what's up with those resistor settings.
Anyway, I've got one unit that I'm taking back home to evaluate. There's really not that much to test, just the analog hookup and the PLL.
Hopefully, in a week, we will know if this is a go or not. I hope it turns out to be perfect, but all those delays scared me today.
Thanks, Everyone, for participating today. I probably only saw a small fraction of what you were posting, text wise. It was something that at the end of the day it started working.
I really need to review what's up with those resistor settings..
I wondered if the FPGA and actual silicon, may behave slightly differently in doing the Float/Pullup/Pulldown tests ?
Thanks, Everyone, for participating today. I probably only saw a small fraction of what you were posting, text wise. It was something that at the end of the day it started working.
I really need to review what's up with those resistor settings..
I wondered if the FPGA and actual silicon, may behave slightly differently in doing the Float/Pullup/Pulldown tests ?
No pullups needed on all the FPGA's except the P123-A7 which behaves like the silicon.
I wonder whether some of those FPGA builds have an Altera pin config that puts them into a particular mode or not? eg weak pullup, hard current drive mode, etc. Perhaps they affect the sensing
Also we don't know where the boundaries between pulldown-floating-pullup are. As in what size of resistor is at the borderline between the different sensed states. We could easily find this out with the A7 build, just use the decade resistor box to find the limits
I wonder whether some of those FPGA builds have an Altera pin config that puts them into a particular mode or not? eg weak pullup, hard current drive mode, etc. Perhaps they affect the sensing
Also we don't know where the boundaries between pulldown-floating-pullup are. As in what size of resistor is at the borderline between the different sensed states. We could easily find this out with the A7 build, just use the decade resistor box to find the limits
The clue with the A7 board was the cog led flashes on briefly after a reset.
This indicated instant shutdown which is what Chip experienced with the silicon.
You're right OzPropDev, that cog run led showed it
$5000 buys quite a few pullup resistors. I find it amusing how, hours after a working P2 with decade long gestation becomes alive, we're already talking changes.
Chances are there will be other things that need a ROM tweak, pullup is absolutely no trouble for now
...
Chances are there will be other things that need a ROM tweak, pullup is absolutely no trouble for now
I'd agree needing a pullup is not a huge issue, provided that pullup does not mean some part of the Boot tree decision is excluded.
SPI and SD Boot need exercising yet, & over power cycles which are harder to test on a FPGA host.
It looks like the Prop needs a pullup for the reset line anyway but I find that all this is simply a matter of documentation. Sure, we'd like it to not need these components ideally but the next option is to do a new ROM in which case I'd be happy to include a lot of "improvements"
It looks like the Prop needs a pullup for the reset line anyway ...
Trying to keep up here ... I think this means the P2 needs 2 pullups, one on RESn and one on P59 ?
Is the RESn cell a schmitt trigger (& sysclk sync'd on release ) ?
Comments
Can you post some Pin-Toggle (via TAQOZ script) and Analog capture pictures on here, as milestones ?
@Peter Jakacki - thank you very much! We had TWO first bloods, at the same time.
Chip's and your's, both succesfull !
Anyway, I've got one unit that I'm taking back home to evaluate. There's really not that much to test, just the analog hookup and the PLL.
Hopefully, in a week, we will know if this is a go or not. I hope it turns out to be perfect, but all those delays scared me today.
Also we don't know where the boundaries between pulldown-floating-pullup are. As in what size of resistor is at the borderline between the different sensed states. We could easily find this out with the A7 build, just use the decade resistor box to find the limits
Yes, good idea to do that test on P2 chips too...
This indicated instant shutdown which is what Chip experienced with the silicon.
$5000 buys quite a few pullup resistors. I find it amusing how, hours after a working P2 with decade long gestation becomes alive, we're already talking changes.
Chances are there will be other things that need a ROM tweak, pullup is absolutely no trouble for now
SPI and SD Boot need exercising yet, & over power cycles which are harder to test on a FPGA host.
Trying to keep up here ... I think this means the P2 needs 2 pullups, one on RESn and one on P59 ?
Is the RESn cell a schmitt trigger (& sysclk sync'd on release ) ?
Yes for RESn. Need to investigate P59.
Yes on both.
Mike
Definately not worth a ROM change for 2 external resistors!
It was just a documentation error
Well done everybody.
Now I have to catch up on the first hour or so of the stream that I missed.