My wife's nephew moved in, and started to act like a cat. One day, after he got fired ..again.. for sleeping late, I told him I was going to run fishing line through all his piercings while he was asleep, and then throw a bucket of cold water on him to see which piercing was the strongest. He never again slept in my presence, and soon moved out. I had my electronic shop back, smiling as I pulled a protoboard off the shelf...
Oh, please, don't talk about chewing nails; for a cannibal like me, it would sound like I'll have to eat a whole tube of fried chips.... but with a substancial increase in fat contents..
As this would certainly not satisfy my huge appetite, my own hands and arms would be in serious risks!
Now that's a twitch stream I'll watch! I'll reserve my fingernails for the power on test.
Notice in many ways that is the first power on test... - OnSemi are running all the self test Logic on these parts, covering the digital stuff, (& some of the clocks ?)
" ... OnSemi and she said that the post-package test is scheduled for tomorrow."
I'm less clear on which clock paths the test pin uses, it may use RCFAST, or it may bypass all PAD Ring clocks, and expect an external Logic CLK on a pin.
If it does use an external logic clock, then a Digital Test (pass) plus then Icc capture in normal mode, should show the RST+RCFAST+Verilog ROM loader actions.
OnSemi's digital test doesn't use our clock pad. They feed in their own clock for their own circuitry into an I/O pin. About 25 pairs of I/O pins serve as DI/DO pairs, if I'm remembering correctly. It's their own concoction, but it uses JTAG signalling, just many sets of data in/out to speed up their test. I believe their whole test takes 880ms. A lot of that is the built-in self-tests (BIST) on the memory instances, of which there are 25:
8 of 16k x 32 single-port (hub RAMs)
16 of 512x32 dual-port (cog and LUT RAMs)
1 of 16k x 8 (boot ROM)
So finally there is a P2, soon. But what to do now with all this time, freed from reading P2 threads? It is now almost a decade I spend religiously reading every post about the P2, I learned a lot about things even never heard of before. And now?
Life will get lonely. No heated discussions about features, no new insights about Verilog, no sitting stunned over timing diagrams. It already has started and I had to start programming the P1 again, instead of just reading posts abut the P2.
Since years, the first thing in the morning is checking the Parallax Forum while starting up my work environment, transitioning my Desk-Computers from home to work (I am working from home). And now, sometimes I do not find unread posts! I even started to read threads again, I feel information-deprived.
I can't imagine how this is for Chip, sure he is glad that this is finished, that he can take his mind off Verilog and on to something different, but surely a big transition.
I still hope someone will build some module like the flip with connectors on top and bottom, maybe one side with P1 compatible Pin-out. FLIP would have a real meaning then, I really would like to reuse my PPDB.
Yes, there will be discussions about actual P2 silicon usage to help us through this "life change". We're all going to be in transition for a little while.
Since years, the first thing in the morning is checking the Parallax Forum while starting up my work environment, transitioning my Desk-Computers from home to work (I am working from home). And now, sometimes I do not find unread posts! I even started to read threads again, I feel information-deprived.
Yeah, forum activity seems to have diminished significantly. Maybe it will pick up again once people get their hands on P2. However, I've been having a lot of fun with P1 lately as well.
Provided we have success this round, we are likely to schedule an event at Parallax in April.
It would be a four-day joint "Blockly World Summit" and "Propeller 2 Expo". Thursday and Friday would be all educational presentations, demonstrations and table displays. Saturday and Sunday would focus on Propeller 2 how-to's, presentations and table displays.
This type of design would support cross-collaboration, mingling and sharing between educational, hobby and engineering users.
Provided we have success this round, we are likely to schedule an event at Parallax in April.
It would be a four-day joint "Blockly World Summit" and "Propeller 2 Expo". Thursday and Friday would be all educational presentations, demonstrations and table displays. Saturday and Sunday would focus on Propeller 2 how-to's, presentations and table displays.
This type of design would support cross-collaboration, mingling and sharing between educational, hobby and engineering users.
Ken Gracey
Cool! You'll surely want a P2 version of my text adventure game authoring system on display!
Ken,
That would be AWESOME (yes all caps). I miss the Prop Expo's of years past so much. Meeting so many great people and seeing all their excellent projects.
Ken,
That would be AWESOME (yes all caps). I miss the Prop Expo's of years past so much. Meeting so many great people and seeing all their excellent projects.
OnSemi's digital test doesn't use our clock pad. They feed in their own clock for their own circuitry into an I/O pin. About 25 pairs of I/O pins serve as DI/DO pairs, if I'm remembering correctly. It's their own concoction, but it uses JTAG signalling, just many sets of data in/out to speed up their test. I believe their whole test takes 880ms. A lot of that is the built-in self-tests (BIST) on the memory instances, of which there are 25:
8 of 16k x 32 single-port (hub RAMs)
16 of 512x32 dual-port (cog and LUT RAMs)
1 of 16k x 8 (boot ROM)
Google says it is 5:58pm in Pocatello.... is no news good news, or are they still setting up the tester ?
Comments
My finger nails are chewed down to the bone.
Now that's a twitch stream I'll watch! I'll reserve my fingernails for the power on test.
Oh, please, don't talk about chewing nails; for a cannibal like me, it would sound like I'll have to eat a whole tube of fried chips.... but with a substancial increase in fat contents..
As this would certainly not satisfy my huge appetite, my own hands and arms would be in serious risks!
Notice in many ways that is the first power on test... - OnSemi are running all the self test Logic on these parts, covering the digital stuff, (& some of the clocks ?)
" ... OnSemi and she said that the post-package test is scheduled for tomorrow."
I'm less clear on which clock paths the test pin uses, it may use RCFAST, or it may bypass all PAD Ring clocks, and expect an external Logic CLK on a pin.
If it does use an external logic clock, then a Digital Test (pass) plus then Icc capture in normal mode, should show the RST+RCFAST+Verilog ROM loader actions.
8 of 16k x 32 single-port (hub RAMs)
16 of 512x32 dual-port (cog and LUT RAMs)
1 of 16k x 8 (boot ROM)
Life will get lonely. No heated discussions about features, no new insights about Verilog, no sitting stunned over timing diagrams. It already has started and I had to start programming the P1 again, instead of just reading posts abut the P2.
Since years, the first thing in the morning is checking the Parallax Forum while starting up my work environment, transitioning my Desk-Computers from home to work (I am working from home). And now, sometimes I do not find unread posts! I even started to read threads again, I feel information-deprived.
I can't imagine how this is for Chip, sure he is glad that this is finished, that he can take his mind off Verilog and on to something different, but surely a big transition.
I still hope someone will build some module like the flip with connectors on top and bottom, maybe one side with P1 compatible Pin-out. FLIP would have a real meaning then, I really would like to reuse my PPDB.
Enjoy!
Mike
Gonna be like early P1 days! Can hardly wait!
Can't wait to build real projects around the P2!
It would be a four-day joint "Blockly World Summit" and "Propeller 2 Expo". Thursday and Friday would be all educational presentations, demonstrations and table displays. Saturday and Sunday would focus on Propeller 2 how-to's, presentations and table displays.
This type of design would support cross-collaboration, mingling and sharing between educational, hobby and engineering users.
Ken Gracey
Cool! You'll surely want a P2 version of my text adventure game authoring system on display!
That would be AWESOME (yes all caps). I miss the Prop Expo's of years past so much. Meeting so many great people and seeing all their excellent projects.
Was hoping you'd jump in the way you did.
I might have to figure out how to come out for that!!
Doc
Google says it is 5:58pm in Pocatello.... is no news good news, or are they still setting up the tester ?
We will have chips at Parallax on Thursday. Hoping it works. We will put some kind of streaming program together, for better or for worse.
Cool.. What tests did they pass ?
Did they apply power in non-test mode and capture Icc on a scope ?
Well, they did use our XI pin as an input to clock the memories for their BIST.
I've been lurching for years to get my hands on a P2. Good luck with it next week. You must be BEYOND psyched!!!!
-Parsko