I had to show my science teacher wife these photos and very carefully explain them. No, that's not intentional that image of two crazy dudes riding a gator beating it along with that stick!
If these chips check out ok I will send off for more pcbs with my newer P2D2 artwork and also make a evaluation board as well for the P2D2 to plug into so we can explore.
Hey! I just received some more parts from Mouser this very minute for my P2D2 boards.
Also, if I rummage though my junk box I'm sure I could find a better camera to donate to these guys than the 13 year old 3MP Canon they used to take these important photos (why oh why).
Here is a quick edit of the best photo of the chip that I could find.
Could you please confirm to me, what are the dimensions of the GND land pattern, where the exposed metal pad is intended to be soldered?
I'm asking this because, despite the silicon die, IIRC, is a square 9.5 mm x 9.5 mm wide, it appears that OnSemi prototype assembly team has done some milling (carving?) at the package inner sidewalls, top to bottom, if you can understand what I'm trying to mean, creating a cavity large enough for the silicon die to be placed inside.
But, if my eyes aren't failing again, they preserved, by not trimming it, the original size of Amkor's exposed pad metal, wich is the largest available at the market, whose dimensions are 10.3 mm x 10.3 mm.
Sure I understand that, and again, provided my eyes are not cheating with me, if they had tryed to trimm the original exposed pad to reach chip dimensions, they would had destructed the package, then I'm not accusing them of any lazyness or wrong procedure. It's not my intention doing something like this.
Despite having a layer of solder resist protecting them, are the power lines you'd designed safely placed away (out) of that 10.3 x 10.3 area?
Chip,
Wonderful piccys! I want all Prop2 to be open top now.
Henrique,
In the photos the die is 8.5 x 8.5, Thermal pad is 9.5 x 9.5.
These aren't packaged by Amkor I don't think. What that means for the finished Prop2 I don't know. That raised ground bonding ring presumably won't exist.
In the photo below, you can see the formed metal between the thermal pad and ground ring. I've circled one.
This prototype packaging solution is something that ON Semi came up with for this job. It is true that the Amkor package is going to look different. I think this package they're using for the prototypes was harvested from some other chip. They had to mechanically mill it down.
Henrique,
In the photos the die is 8.5 x 8.5, Thermal pad is 9.5 x 9.5.
These aren't packaged by Amkor I don't think. What that means for the finished Prop2 I don't know. That raised ground bonding ring presumably won't exist.
In the photo below, you can see the formed metal between the thermal pad and ground ring. I've circled one.
Hi evanh
Sure, I know they were not packaged by Amkor; it was OnSemi's team who did them. But the production P2 will be sent to Amkor to be packaged, IIRC.
Since Amkor is so jealous to the point to don't publish their technology-related photos on their website, I need to resort to Shinko's to get the links, but both companies use the same knowledge/technology base, thru a patent exchange agreement they have. I know because it appeared somewere, including SEC public available documents, due to Amkor's shares being negotiated at the USA stock exchange market. Sorry, but I don't have the SEC-related links at hand, ATM.
Contrary to you, I believe they'll keep the ground ring, by two reasons:
- the package will be a LQFP (1.4 mm body thickness), thus "deeper" than its equivalent TQFP (1.0 mm body thickness);
- as it can be seen at the photos Chip has attached, it's easier to connect the pad ring GND pads to an elevated GND ring, than it would be, if the exposed pad inner surface was used to solder the wires.
Moreover due to the fact that (9.5 - 8.0) / 2 = 0.75 mm; it means too little space remaining at the copper metal, protruding lateraly each side, for the soldering of the gold wires coming from the pad ring gnd pads, thus the wire dispensing/soldering tool should "go deeper", with all the other package pin inner-tips floating around, as obstacles, and in another (and elevated) plane.
Yes, I believe that is like what Chip called it. Strange machine. It just looks odd. I think the best was Ken sharing his take on Chip fixing his chip! He did create every polygon for P1. Entirely custom all the way down.
The P1 was laid out by Frank Olson, who used to work at Parallax. He made the polygons to match my schematic. It was a lot of creative work on his part.
Beau Schwabe did tons of early layout on P2, but we wound up having Treehouse redo it all, in order to realize late changes I had made. Beau even laid out custom ROM, DPRAM, and SPRAM that we proved on a test chip, but later swapped out for ON Semi memory IP.
The chips are supposed to arrive at 10:30 a.m. Ken will live stream the testing. He thinks Facebook would work best. Maybe if it fails right away, we could just use Twitter. On the other hand, Facebook may censor good news. Let's all just hope for the best.
Comments
Ground?
Yes.
Fingers crossed it works flawlessly.
Wait, I think I see that is the under die ground plane. Just looks kindof grainy in other photo...
Maybe it's copper?
Hard to tell depth but looks like all the gold bond wires have to bend over the ground ring...
If these chips check out ok I will send off for more pcbs with my newer P2D2 artwork and also make a evaluation board as well for the P2D2 to plug into so we can explore.
Hey! I just received some more parts from Mouser this very minute for my P2D2 boards.
Also, if I rummage though my junk box I'm sure I could find a better camera to donate to these guys than the 13 year old 3MP Canon they used to take these important photos (why oh why).
Here is a quick edit of the best photo of the chip that I could find.
Methinks I'm going to be building me a conference badge for this ;-)
(and the badge will double-up as a dev board)
Assuming all goes to plan we should be at general availability by this date - right?
Could you please confirm to me, what are the dimensions of the GND land pattern, where the exposed metal pad is intended to be soldered?
I'm asking this because, despite the silicon die, IIRC, is a square 9.5 mm x 9.5 mm wide, it appears that OnSemi prototype assembly team has done some milling (carving?) at the package inner sidewalls, top to bottom, if you can understand what I'm trying to mean, creating a cavity large enough for the silicon die to be placed inside.
But, if my eyes aren't failing again, they preserved, by not trimming it, the original size of Amkor's exposed pad metal, wich is the largest available at the market, whose dimensions are 10.3 mm x 10.3 mm.
Sure I understand that, and again, provided my eyes are not cheating with me, if they had tryed to trimm the original exposed pad to reach chip dimensions, they would had destructed the package, then I'm not accusing them of any lazyness or wrong procedure. It's not my intention doing something like this.
Despite having a layer of solder resist protecting them, are the power lines you'd designed safely placed away (out) of that 10.3 x 10.3 area?
Henrique
Wonderful piccys! I want all Prop2 to be open top now.
Henrique,
In the photos the die is 8.5 x 8.5, Thermal pad is 9.5 x 9.5.
These aren't packaged by Amkor I don't think. What that means for the finished Prop2 I don't know. That raised ground bonding ring presumably won't exist.
In the photo below, you can see the formed metal between the thermal pad and ground ring. I've circled one.
Hi evanh
Sure, I know they were not packaged by Amkor; it was OnSemi's team who did them. But the production P2 will be sent to Amkor to be packaged, IIRC.
Since Amkor is so jealous to the point to don't publish their technology-related photos on their website, I need to resort to Shinko's to get the links, but both companies use the same knowledge/technology base, thru a patent exchange agreement they have. I know because it appeared somewere, including SEC public available documents, due to Amkor's shares being negotiated at the USA stock exchange market. Sorry, but I don't have the SEC-related links at hand, ATM.
https://shinko.co.jp/english/product/leadframe/etp-lf.html#link3
Contrary to you, I believe they'll keep the ground ring, by two reasons:
- the package will be a LQFP (1.4 mm body thickness), thus "deeper" than its equivalent TQFP (1.0 mm body thickness);
- as it can be seen at the photos Chip has attached, it's easier to connect the pad ring GND pads to an elevated GND ring, than it would be, if the exposed pad inner surface was used to solder the wires.
Moreover due to the fact that (9.5 - 8.0) / 2 = 0.75 mm; it means too little space remaining at the copper metal, protruding lateraly each side, for the soldering of the gold wires coming from the pad ring gnd pads, thus the wire dispensing/soldering tool should "go deeper", with all the other package pin inner-tips floating around, as obstacles, and in another (and elevated) plane.
Hey, seems like the OnSemi guys are treating you right Chip!
It is fun to see.
And it makes me think about back in the day, you with that crazy vacuum, space ship looking contraption used ro make an early P1 work.
These chips look kind of like that early, open top P1 did.
Peter's P2D2 board is for the OnSemi prototype package.
I wasn't around here back then. Didn't see any of those.
[img][/img]
Beau Schwabe did tons of early layout on P2, but we wound up having Treehouse redo it all, in order to realize late changes I had made. Beau even laid out custom ROM, DPRAM, and SPRAM that we proved on a test chip, but later swapped out for ON Semi memory IP.
I thought there was to be a simple live stream to Youtube.