Somehow, I sort of imagined the Hub RAM may have been in the centre with the cogs around it.
The cogs have to connect among themselves, mostly. So, it's best to fling the memories to the outside, with as many degrees of symmetry as possible, to allow for a circular blob in the middle. All the random logic sits happily in the blob.
I would have thought the monstrous bus surrounding the hub going out to the cogs would be smaller by surrounding a central hub. There's not much going on between cogs, and them being on the outer ring would have allowed them to hook into the I/O bus surrounding the smart pins.
curious, are the blocks auto placed?
Only the memories were hand-placed.
The cog logic needs to be in a blob because all the pin-control signals need combining before going out to all the smart pins, which probably do locate outwards, closer to the pins.
Is the black gap between the VIO planes and the central grey available for synthesis space?
I think that's routing space for signals and power. The cell area is grey. You can see thin grey lines on the outsides of the memories. The router may place some cells out there.
I was just talking to Wendy at OnSemi, who's doing the synthesis, and she said that since the last change to XORO32 was made, along with improvements to the memory built-in-self-test, things are looking a lot better.
The prior Fmax after synthesis was 193Mhz and the cell count was 647k.
Now, the Fmax is coming in at 216MHz and the cell count has dropped to 527k.
That's way less buffering, which means lower power at the same speed.
Bryan is now pushing this through his physical place and route tool. Who knows, maybe we'll get 200MHz, after all.
Wendy said that the timing tool can compute extra Fmax values for tighter voltages and lower temperatures. So, we can have some breakdown in Fmax with regards to voltage and temperature, which can give us conditionally higher Fmax values.
I was just talking to Wendy at OnSemi, who's doing the synthesis, and she said that since the last change to XORO32 was made, along with improvements to the memory built-in-self-test, things are looking a lot better.
The prior Fmax after synthesis was 193Mhz and the cell count was 647k.
Now, the Fmax is coming in at 216MHz and the cell count has dropped to 527k.
That's way less buffering, which means lower power at the same speed.
Interesting how this bounces around.... with small changes, rippling to cause larger effects on the totals.
Bryan is now pushing this through his physical place and route tool. Who knows, maybe we'll get 200MHz, after all.
Wendy said that the timing tool can compute extra Fmax values for tighter voltages and lower temperatures. So, we can have some breakdown in Fmax with regards to voltage and temperature, which can give us conditionally higher Fmax values.
Sounds great - I think that's well worth having, from a sales viewpoint.
Even P1 could benefit from such a multiple spec. Most voltage regulators are well inside 5% these days, and Ta to 125°C is not that commonly needed !
So since the only change was in the XORO32 doesn't this indicate that the XORO32 was the slowest part, and not the hub RAM? I wonder if there might be further improvement in the XORO32 that would increase the speed of the chip even more.
So since the only change was in the XORO32 doesn't this indicate that the XORO32 was the slowest part, and not the hub RAM? I wonder if there might be further improvement in the XORO32 that would increase the speed of the chip even more.
XORO32 was the slowest part. Now it's the hub RAMs.
Two improvements were made to XORO32 that sped it up. First, its result was made higher-priority in the Q-register mux. Second, the PRNG result was computed from the initial state and first iteration values, instead of the first and second iteration values.
Yes, it all fits. In that screenshot, not only is the memory and logic present, but so is the scan change, the memory built-in-self-test (MBIST), and the clock tree.
It's looking like 200MHz is not going to be possible, but 180MHz should be fine. In this preliminary reality-check layout, the critical paths were in the initial implementation of the MBIST (which has since been much improved), and the whole thing was coming in at around 165MHz, worst-case.
What Voltage and temperature ( Tj? ) are those worst-case for ? (ISTR 125°C was mentioned ? )
Worst-case is:
* Slow process corner
* 90% voltages (2.97V, 1.62V)
* Tj = 150 C
What is the low temp spec?
I used P1s for avionics (the name propeller is a perfect fit then). I have to go down to at least -40°C.
What is the low temp spec?
I used P1s for avionics (the name propeller is a perfect fit then). I have to go down to at least -40°C.
As a guide, P1 spec's say -55 °C to +125 °C but I'm not sure how much of that is tested 100%.
Parallax have taken much pride in their torture chamber, in the which the P1 has been subjected to all sorts of abuse, and still functioned. A zillion years back I read a piece about that, and saw some pictures of the equipment. I think the chip has been fully wrung out.
Yes, it all fits. In that screenshot, not only is the memory and logic present, but so is the scan change, the memory built-in-self-test (MBIST), and the clock tree.
It's looking like 200MHz is not going to be possible, but 180MHz should be fine. In this preliminary reality-check layout, the critical paths were in the initial implementation of the MBIST (which has since been much improved), and the whole thing was coming in at around 165MHz, worst-case.
What Voltage and temperature ( Tj? ) are those worst-case for ? (ISTR 125°C was mentioned ? )
Worst-case is:
* Slow process corner
* 90% voltages (2.97V, 1.62V)
* Tj = 150 C
What is the low temp spec?
I used P1s for avionics (the name propeller is a perfect fit then). I have to go down to at least -40°C.
I think we spec'd -40C. I'll ask about -55C. I don't think we'd need to make any changes. We'd just need to have a timing report.
Isn't any low temp spec all about mechanical stresses breaking things in the packaging. Or even the leads at such low temperatures losing their malleability and fracturing.
EDIT: A quick search reveals copper and its alloys gets more malleability at lower temperature, so I guess that point is no concern. Nice bonus.
Yes, it all fits. In that screenshot, not only is the memory and logic present, but so is the scan change, the memory built-in-self-test (MBIST), and the clock tree.
It's looking like 200MHz is not going to be possible, but 180MHz should be fine. In this preliminary reality-check layout, the critical paths were in the initial implementation of the MBIST (which has since been much improved), and the whole thing was coming in at around 165MHz, worst-case.
What Voltage and temperature ( Tj? ) are those worst-case for ? (ISTR 125°C was mentioned ? )
Worst-case is:
* Slow process corner
* 90% voltages (2.97V, 1.62V)
* Tj = 150 C
What is the low temp spec?
I used P1s for avionics (the name propeller is a perfect fit then). I have to go down to at least -40°C.
I think we spec'd -40C. I'll ask about -55C. I don't think we'd need to make any changes. We'd just need to have a timing report.
I know, I saw a report from Parallax. And I have tested my devices down to -45°C.
Yes, it all fits. In that screenshot, not only is the memory and logic present, but so is the scan change, the memory built-in-self-test (MBIST), and the clock tree.
It's looking like 200MHz is not going to be possible, but 180MHz should be fine. In this preliminary reality-check layout, the critical paths were in the initial implementation of the MBIST (which has since been much improved), and the whole thing was coming in at around 165MHz, worst-case.
What Voltage and temperature ( Tj? ) are those worst-case for ? (ISTR 125°C was mentioned ? )
Worst-case is:
* Slow process corner
* 90% voltages (2.97V, 1.62V)
* Tj = 150 C
What is the low temp spec?
I used P1s for avionics (the name propeller is a perfect fit then). I have to go down to at least -40°C.
I think we spec'd -40C. I'll ask about -55C. I don't think we'd need to make any changes. We'd just need to have a timing report.
I know, I saw a report from Parallax. And I have tested my devices down to -45°C.
Just forgot, you all just talked about the P1. I hope the P2 will be spec'd similarly.
GREAT!!!! Now the whole forum will be frothing at the mouth I think there needs to be an ad campaign and slogan drive for this P2. I envision an EE defecating on a bunch of the competitions uCs, screaming "I need to P2"
GREAT!!!! Now the whole forum will be frothing at the mouth I think there needs to be an ad campaign and slogan drive for this P2. I envision an EE defecating on a bunch of the competitions uCs, screaming "I need to P2"
Maybe we could make a board that contains some common uC's and a P2. We could call it "Number 3".
Maybe we could make a board that contains some common uC's and a P2. We could call it "Number 3".
You may be onto something there....
Many manufacturers create evaluation boards for their own products. However, if you were to install some competition chips side by side, with the P2, than the EEs could do some serious evaluation, of the various uCs. However, you would definitely want the P2 to outshine the competitive uCs on such a board.
Comments
Only the memories were hand-placed.
The cog logic needs to be in a blob because all the pin-control signals need combining before going out to all the smart pins, which probably do locate outwards, closer to the pins.
I think that's routing space for signals and power. The cell area is grey. You can see thin grey lines on the outsides of the memories. The router may place some cells out there.
The prior Fmax after synthesis was 193Mhz and the cell count was 647k.
Now, the Fmax is coming in at 216MHz and the cell count has dropped to 527k.
That's way less buffering, which means lower power at the same speed.
Bryan is now pushing this through his physical place and route tool. Who knows, maybe we'll get 200MHz, after all.
Wendy said that the timing tool can compute extra Fmax values for tighter voltages and lower temperatures. So, we can have some breakdown in Fmax with regards to voltage and temperature, which can give us conditionally higher Fmax values.
Sounds great - I think that's well worth having, from a sales viewpoint.
Even P1 could benefit from such a multiple spec. Most voltage regulators are well inside 5% these days, and Ta to 125°C is not that commonly needed !
Love to see what would happen if the hub ram were in the centre of the die
Yes, I know it won't happen but I can be curious.
It would be forced to split the logic blob around the sides and timing would go to pot, as it routed around the memories.
XORO32 was the slowest part. Now it's the hub RAMs.
Two improvements were made to XORO32 that sped it up. First, its result was made higher-priority in the Q-register mux. Second, the PRNG result was computed from the initial state and first iteration values, instead of the first and second iteration values.
What is the low temp spec?
I used P1s for avionics (the name propeller is a perfect fit then). I have to go down to at least -40°C.
As a guide, P1 spec's say -55 °C to +125 °C but I'm not sure how much of that is tested 100%.
Parallax have taken much pride in their torture chamber, in the which the P1 has been subjected to all sorts of abuse, and still functioned. A zillion years back I read a piece about that, and saw some pictures of the equipment. I think the chip has been fully wrung out.
I think we spec'd -40C. I'll ask about -55C. I don't think we'd need to make any changes. We'd just need to have a timing report.
EDIT: A quick search reveals copper and its alloys gets more malleability at lower temperature, so I guess that point is no concern. Nice bonus.
I know, I saw a report from Parallax. And I have tested my devices down to -45°C.
Just forgot, you all just talked about the P1. I hope the P2 will be spec'd similarly.
GREAT!!!! Now the whole forum will be frothing at the mouth
Maybe we could make a board that contains some common uC's and a P2. We could call it "Number 3".
It looks like there are lots of things called P2. So, probably not.
Is PP2 (Parallax Propeller 2) trademarked or P^2 (P squared)?
We don't have trademarks on any of those names.
You may be onto something there....
Many manufacturers create evaluation boards for their own products. However, if you were to install some competition chips side by side, with the P2, than the EEs could do some serious evaluation, of the various uCs. However, you would definitely want the P2 to outshine the competitive uCs on such a board.
Very bold, but shame it's not a Google-friendly label, or something likely to enter the lexicon....