"I see. Thanks for the elaboration. I'm pretty much the best layout guy here on the farm, and maybe even in Red Bluff." ... As I said, I might be a little biased, only for a good reason though. I didn't realize you were doing the layout. Hind sight is 20/20
What is the process limitation for frequency? ... While at NSC, the TSMC rule of thumb for 180nm was about 350MHz mostly due to substrate leakage. That rule of thumb is usually derated, so double that would not be out of the question. However with appropriate use of NWELL isolation you could greatly reduce the substrate leakage where higher frequencies would be achievable.
I don't know what the frequency limitation is considered to be for this process.
I did what Jmg suggested, and added some "parasitic" caps to ground on the VCO inverter's input and output nodes. It took 3fF per node to get the frequency down to 630MHz under 'typical' conditions. Then, I ran the new L=0.5u VCO inverter with those parasitics at the slow process corner with VDD=1.62V and temp=150C. The thing only ran 208MHz. I want it to be a little more above 200MHz. So, I made L=0.45u and that got the frequency up to 238MHz, which is sufficiently in-the-clear above 200MHz, considering there may be some sleeper issues elsewhere that could slow it down. So, we have an apparent 19% margin now, which is good. And at typical conditions, the VCO maxes out at 360MHz, which is nicely below the 440MHz limit of the divider circuits.
How does NWELL isolation reduce substrate leakage at high-frequency? The NWELL is tied to VDD and forms a reverse-biased diode to the subtrate which is tied to GND, right? How can it leak, at all, and even more at high frequency? Are you talking about some capacitive coupling effect that results in more power dissipation?
My only concern is that I understand why the VCO was so off. I can understand that with long wire runs, the digital counters could slow, but I don't know how something as compact as the VCO could be so far off..
A simple litmus test is to add some fF of parasitic C to every inverter, and adjust that to drop the Spice-1G to the Measured-630MHz
You only need to add ~42ps to each inverter.
"The NWELL is tied to VDD and forms a reverse-biased diode to the subtrate which is tied to GND, right?" ... Specializing in high speed communication with IC layout, there is no specific rule that requires you to tie NWELL to VDD. Aside from that, NMOS resistive leakage to the substrate and capacitive effects are going to be your biggest problem. I wish I could just do the layout for you and look over it as a second set of eyes to avoid any potential issues, but that's not going to happen.
"The NWELL is tied to VDD and forms a reverse-biased diode to the subtrate which is tied to GND, right?" ... Specializing in high speed communication with IC layout, there is no specific rule that requires you to tie NWELL to VDD. Aside from that, NMOS resistive leakage to the substrate and capacitive effects are going to be your biggest problem. I wish I could just do the layout for you and look over it as a second set of eyes to avoid any potential issues, but that's not going to happen.
"Why do you say it's not going to happen?" ... You took me off the payroll.
I failed to keep you busy enough to make it work out. That wasn't a good situation, for you, especially. It's better for a person to have work that is consistently engaging.
We will not hire another layout employee because our sporadic needs could easily undermine their security. It's not a good situation, long term, for either party.
On the other hand, there is certainly need for freelance layout workers who can engage on projects for a few months at a time. Expensive tools might dictate how those arrangements work. If you had your own set of affordable tools, though, you could easily do full projects for people. Layout is very labor-intensive and usually underestimated. it quite often BECOMES the critical path, from what I've seen, recently. There is a lot of need for good layout work.
"I failed to keep you busy enough to make it work out." ... I was plenty busy with all of the constant changes that were made with the schematics and 12 hour days I pulled for years at a time. I offered to be on R&D many many times and it always fell on deaf ears. The only way contracting will work is if the tools are supplied by the interested company. Quality layout tools especially are cost prohibitive as you well know, and if Parallax couldn't afford them, how do you expect a freelance layout guy to be able to afford them? "A few months at a time" simply won't work, as I have seventeen mouths to feed.
These Tanner EDA tools are pretty decent, I think. Mentor knows that their customer doesn't have nearly the resources of the guys that buy Cadence. They've been pretty flexible with us. I'm kind of liking them these days.
We have Ducks, Horses, Dogs, Cats, and the kids :-)
...With more ducks on the way.
I don't mean to sound harsh, but the truth of the matter is that if I hadn't been let go from Parallax I wouldn't have the farm I have.
So perhaps it was a blessing in disguise. I do business in a different gear now, and unfortunately layout is not that gear.... instead I design equipment that reverse engineers IC layout designs other people have done. So in a way I am on the other side of the fence.
Here's the logo that goes onto the upper-left corner of the die.
It looks simple, but it was a bear to get it passing DRC. I designed it at a tiny empirical scale and then instanced it into another cell. There, I scaled it up and rotated it 45 degrees. Then, I flattened it, divorcing it from the source cell and turning it into a bunch of off-grid polygons. So, I had to snap all the vertices to the 0.005um manufacturing grid, and then go in and tweak it here and there to get every vertex flush with any adjacent polygon edge. It was tedious. Anyway, it finally passes DRC and is the right size with the origin in the right place, and so on. Whew.
Here is a screenshot of the current floorplan/layout:
The eight different VIO/GIO domains, which each support four I/O pins (and RESn/TEST in the upper left, and XI/XO in the lower right), are uniquely color coded.
You can see the big 64KB hub RAM instances (8 of them) and the smaller 2KB cog and lut RAM instances (16 total, 2 per cog). Then, there's the singular 16KB ROM instance in the middle left.
The eight different VIO/GIO domains, which each support four I/O pins (and RESn/TEST in the upper left, and XI/XO in the lower right), are uniquely color coded.
Cool, but never mind all that... more important questions...
Does it fit (512K) , and what MHz does it come in at ?
The eight different VIO/GIO domains, which each support four I/O pins (and RESn/TEST in the upper left, and XI/XO in the lower right), are uniquely color coded.
Cool, but never mind all that... more important questions...
Does it fit (512K) , and what MHz does it come in at ?
Yes, it all fits. In that screenshot, not only is the memory and logic present, but so is the scan change, the memory built-in-self-test (MBIST), and the clock tree.
It's looking like 200MHz is not going to be possible, but 180MHz should be fine. In this preliminary reality-check layout, the critical paths were in the initial implementation of the MBIST (which has since been much improved), and the whole thing was coming in at around 165MHz, worst-case.
Yes, it all fits. In that screenshot, not only is the memory and logic present, but so is the scan change, the memory built-in-self-test (MBIST), and the clock tree.
It's looking like 200MHz is not going to be possible, but 180MHz should be fine. In this preliminary reality-check layout, the critical paths were in the initial implementation of the MBIST (which has since been much improved), and the whole thing was coming in at around 165MHz, worst-case.
What Voltage and temperature ( Tj? ) are those worst-case for ? (ISTR 125°C was mentioned ? )
Yes, it all fits. In that screenshot, not only is the memory and logic present, but so is the scan change, the memory built-in-self-test (MBIST), and the clock tree.
It's looking like 200MHz is not going to be possible, but 180MHz should be fine. In this preliminary reality-check layout, the critical paths were in the initial implementation of the MBIST (which has since been much improved), and the whole thing was coming in at around 165MHz, worst-case.
What Voltage and temperature ( Tj? ) are those worst-case for ? (ISTR 125°C was mentioned ? )
Worst-case is:
* Slow process corner
* 90% voltages (2.97V, 1.62V)
* Tj = 150 C
* Slow process corner
* 90% voltages (2.97V, 1.62V)
* Tj = 150 C
Sounds good, that's what many would call the old industrial or maybe even Automotive specs.
If they run for 95% voltage, and lower Tj ( 115-120-125°C ?) how much does it change ?
Many vendors have multiple MHz specs, with the highest having tightest Vcc & lower temps (as expected).
Chip,
Those VIO planes look way bigger than I was expecting. I'm assuming that is solely the custom area, ie: None of Smartpin or other synthesis goes under them.
Chip,
Those VIO planes look way bigger than I was expecting. I'm assuming that is solely the custom area, ie: None of Smartpin or other synthesis goes under them.
Was this process, group, and equipment used to design the Basic Stamp Modules?
Nope, Basic Stamp goes way-way-way-back, to when PIC's were 'goto' small MCUs, and even OTP (one time programmable).
Someone clever squashed a BASIC token playback engine into the PIC+EEPROM, and the rest is history.
I see you can even still buy PIC16C57 (OTP), tho at a 'you have to really want this' price.
Somehow, I sort of imagined the Hub RAM may have been in the centre with the cogs around it.
The cogs have to connect among themselves, mostly. So, it's best to fling the memories to the outside, with as many degrees of symmetry as possible, to allow for a circular blob in the middle. All the random logic sits happily in the blob.
Refering to the screenshot you've published, is there any available space (%) at the grey-colored area?
There's lots of empty space, spread all around.
On initial logic placement, 65% utilization of space is ideal. After that, clock trees, scan chains, and test circuits are added interstitially. Also, buffering is added to meet timing on slow signals. In the end, area utilization may wind up at around 95%.
Somehow, I sort of imagined the Hub RAM may have been in the centre with the cogs around it.
The cogs have to connect among themselves, mostly. So, it's best to fling the memories to the outside, with as many degrees of symmetry as possible, to allow for a circular blob in the middle. All the random logic sits happily in the blob.
I would have thought the monstrous bus surrounding the hub going out to the cogs would be smaller by surrounding a central hub. There's not much going on between cogs, and them being on the outer ring would have allowed them to hook into the I/O bus surrounding the smart pins.
Comments
I don't know what the frequency limitation is considered to be for this process.
I did what Jmg suggested, and added some "parasitic" caps to ground on the VCO inverter's input and output nodes. It took 3fF per node to get the frequency down to 630MHz under 'typical' conditions. Then, I ran the new L=0.5u VCO inverter with those parasitics at the slow process corner with VDD=1.62V and temp=150C. The thing only ran 208MHz. I want it to be a little more above 200MHz. So, I made L=0.45u and that got the frequency up to 238MHz, which is sufficiently in-the-clear above 200MHz, considering there may be some sleeper issues elsewhere that could slow it down. So, we have an apparent 19% margin now, which is good. And at typical conditions, the VCO maxes out at 360MHz, which is nicely below the 440MHz limit of the divider circuits.
How does NWELL isolation reduce substrate leakage at high-frequency? The NWELL is tied to VDD and forms a reverse-biased diode to the subtrate which is tied to GND, right? How can it leak, at all, and even more at high frequency? Are you talking about some capacitive coupling effect that results in more power dissipation?
This was good advice. See post above.
Why do you say it's not going to happen?
I failed to keep you busy enough to make it work out. That wasn't a good situation, for you, especially. It's better for a person to have work that is consistently engaging.
We will not hire another layout employee because our sporadic needs could easily undermine their security. It's not a good situation, long term, for either party.
On the other hand, there is certainly need for freelance layout workers who can engage on projects for a few months at a time. Expensive tools might dictate how those arrangements work. If you had your own set of affordable tools, though, you could easily do full projects for people. Layout is very labor-intensive and usually underestimated. it quite often BECOMES the critical path, from what I've seen, recently. There is a lot of need for good layout work.
Best of luck to you Chip
...With more ducks on the way.
I don't mean to sound harsh, but the truth of the matter is that if I hadn't been let go from Parallax I wouldn't have the farm I have.
So perhaps it was a blessing in disguise. I do business in a different gear now, and unfortunately layout is not that gear.... instead I design equipment that reverse engineers IC layout designs other people have done. So in a way I am on the other side of the fence.
It looks simple, but it was a bear to get it passing DRC. I designed it at a tiny empirical scale and then instanced it into another cell. There, I scaled it up and rotated it 45 degrees. Then, I flattened it, divorcing it from the source cell and turning it into a bunch of off-grid polygons. So, I had to snap all the vertices to the 0.005um manufacturing grid, and then go in and tweak it here and there to get every vertex flush with any adjacent polygon edge. It was tedious. Anyway, it finally passes DRC and is the right size with the origin in the right place, and so on. Whew.
You've said it was a bear to pass DRC.
Before expanding the image, I've understood it as being an actual bear, with the Propeller beanie in its head!
Anyway, amazing (and time consuming) job!
The eight different VIO/GIO domains, which each support four I/O pins (and RESn/TEST in the upper left, and XI/XO in the lower right), are uniquely color coded.
You can see the big 64KB hub RAM instances (8 of them) and the smaller 2KB cog and lut RAM instances (16 total, 2 per cog). Then, there's the singular 16KB ROM instance in the middle left.
Cool, but never mind all that... more important questions...
Does it fit (512K) , and what MHz does it come in at ?
Yes, it all fits. In that screenshot, not only is the memory and logic present, but so is the scan change, the memory built-in-self-test (MBIST), and the clock tree.
It's looking like 200MHz is not going to be possible, but 180MHz should be fine. In this preliminary reality-check layout, the critical paths were in the initial implementation of the MBIST (which has since been much improved), and the whole thing was coming in at around 165MHz, worst-case.
What Voltage and temperature ( Tj? ) are those worst-case for ? (ISTR 125°C was mentioned ? )
Worst-case is:
* Slow process corner
* 90% voltages (2.97V, 1.62V)
* Tj = 150 C
Sounds good, that's what many would call the old industrial or maybe even Automotive specs.
If they run for 95% voltage, and lower Tj ( 115-120-125°C ?) how much does it change ?
Many vendors have multiple MHz specs, with the highest having tightest Vcc & lower temps (as expected).
Chip,
Those VIO planes look way bigger than I was expecting. I'm assuming that is solely the custom area, ie: None of Smartpin or other synthesis goes under them.
Right. They are the custom pads.
Nope, Basic Stamp goes way-way-way-back, to when PIC's were 'goto' small MCUs, and even OTP (one time programmable).
Someone clever squashed a BASIC token playback engine into the PIC+EEPROM, and the rest is history.
I see you can even still buy PIC16C57 (OTP), tho at a 'you have to really want this' price.
Somehow, I sort of imagined the Hub RAM may have been in the centre with the cogs around it.
The cogs have to connect among themselves, mostly. So, it's best to fling the memories to the outside, with as many degrees of symmetry as possible, to allow for a circular blob in the middle. All the random logic sits happily in the blob.
Refering to the screenshot you've published, is there any available space (%) at the grey-colored area?
There's lots of empty space, spread all around.
On initial logic placement, 65% utilization of space is ideal. After that, clock trees, scan chains, and test circuits are added interstitially. Also, buffering is added to meet timing on slow signals. In the end, area utilization may wind up at around 95%.
curious, are the blocks auto placed?