The XMOS chips are used as FPGA replacements, and can do high-speed USB and fast Ethernet in software. They are made using a much faster process, of course.
,,,Maybe that is where Parallax should look, bring FPGAs to the DIY market with simple software tools, I am not suggesting they build any silicon.
I think that is a good opening, Parallax can address pretty much right now.
They do plan a large FPGA board, but that will be Niche for P2 development and $hundreds.
I think a smaller module board with a P1 and P1V using a MAX10 allows a common tool chain ecosystem, and they can leverage on the P1-FPGA loader they plan on the large board.
Such a board would allow development of projects that might logically move to P2 when it ships.
It could also field prove the Smart-Pin P2 cells, if Parallax wanted to, and seed Library support for them.
It certainly reaches way above where P1 can right now.
What I mean is that I have seen the Prop suggested as a low end FPGA replacement, which I don't understand.
Do you mean P1 or P2 ?
There is a large enough area of FPGA usage that is effectively smart-RAM, and if the P2 manages 512K+ of RAM, then it can compete quite well in that niche. So it does not 'replace a FPGA' so much as displace a FPGA usage.
Check out the prices of Dual Port memory.
I have seen the Prop suggested as a low end FPGA replacement, which I don't understand.
The concept is simple:
An FPGA is a sea of logic blocks. Logic blocks are arrangements of combinatorial and sequential logic that can be configured to perform a variety of functions. All logic blocks are the same. They are all interconnected by a configurable matrix. Those configurations are generated from VHDL/Verilog that defines the functionality you want.
So, what if you made the logic blocks a bit more complex and more flexible. Use actual CPU's instead of logic blocks. They are "configured" using normal programming languages. Now replace that interconnect matrix with high speed communication channels, or just shared RAM. Again that interconnect is defined in the normal programming language.
Bingo! you have a replacement for the FPGA out of a mass of processors.
Now, of course those CPU's are never going to be as fast as those logic units. And you may never get so many of them on a chip. But you have a viable FPGA replacement for low end FPGA tasks that is a thousand times easier to program. It also has some advantages, like simply being able to run application software as well, no need to put a soft core CPU in your FPGA to do that.
That is the idea behind the multi-core XMOS devices and the Prop is leaning in that direction. Admittedly the Prop 1 is a lot slower but there we go.
Verilog is terrible. So is VHDL. We may be able to get to grips with it but I don't think the regular programmers of the world would have an easy time of it without a lot of study and practice.
Yes, academics may well be reinventing the wheel. In the case of Chisle for good reason. The main problem with all this is that no matter how easy you make a hardware description language you still need those huge and complex tools from the FPGA vendors to synthesize the design for their devices.
Yes, as I said, low end FPGA tasks. Certainly there is not the speed for HDMI and ethernet. That is an issue that can, to a certain extent be helped with some flexible serdes and clocked IO peripheral hardware. That is the approcach taken by XMOS and the new LowRISC design.
I don't see Parallax getting much gain from becoming an FPGA board supplier. There are many of those already. Unless they could magically make an FPGA as popular as the Arduino made the micro-controller I don't see that idea going anywhere. The big stumbling block as I said is the need to have those huge, complex and slow, development softwares from the FPGA manufacturer to do anything with an FPGA.
OK maybe there is a small niche there (easier to program small FPGA replacements), but not sure I buy it, but then its not my money.
FPGAs use the latest technology, Xilinx is already announcing 20nm and 16nm products.
GreenArray and XMOS raised a bunch of money probably to afford the mask sets, I'm not sure which process they ended up using, my WAG would be 60nm maybe 45.
So big FPGAs (yes expensive in low volume, but Cisco and the like don't pay a lot for them) will be 100 times denser in memory/logic.
As for programmers and HDL, I actually know a couple software guys that converted over and are some of the hotshot "hardware" designers in Silicon Valley (both at billion $ + fabless semi companies)
To get the most out of a Parallax COG, you need to be writing in ASM, and I find few software people these days that know much about any assembly language.
I'll make username happy and go to sleep now, looking forward to P2 in 2016.
Bruce,
I see you're still fixated on large volume products. Parallax has never in it's entire history been operating in such markets. EDIT: Not to say that a deal couldn't be reached if there was someone ready to put down an order for a few million units in one run.
To get the most out of a Parallax COG, you need to be writing in ASM, and I find few software people these days that know much about any assembly language.
Or use someone else's code from the object exchange. Even maybe get it tweaked to your needs via forum questions. And there is cogC option also, I'm not sure how well that works but it's there. Linking in soft devices is easy with Spin, and not too hard with C.
Once upon part of the P2 open design thread, Chip and Beau discussed some of the issues and tradeoffs involved in the range of IC processes available covering the range of 180nm through 60nm (as I recall). The P1 has low idle state power consumption, particularly when most of the chip is shut down (idle) and the rest of the chip operating at 32kHz. As the process features get smaller, the leakage gets larger to where the leakage dominates the power consumption, even with the clock essentially turned off. I believe you can partly deal with this by shutting off the power to sections of the chip, but the wake up time requires some power stabilization and reinitialization in that case while the P1 is statically clocked and can just pick up where it left off with the next clock pulse.
I don't see Parallax getting much gain from becoming an FPGA board supplier. There are many of those already. Unless they could magically make an FPGA as popular as the Arduino made the micro-controller I don't see that idea going anywhere. The big stumbling block as I said is the need to have those huge, complex and slow, development softwares from the FPGA manufacturer to do anything with an FPGA.
This is *precisely* why we need someone like Parallax to dive into this area and pave the way for us. Like the basic stamp and propeller have done.
It'd be interesting to set Andy and Stephanie onto this and see what they came up with
Fortunately we don't have to wrestle the toolchain. Its relatively simple to use the stand alone programmer to burn a P1V or P2 image, and probably even have a P3 image (note the new Parallax FPGA board title).
The GadgetFactory is already way ahead of them. They already adopted the Arduino IDE to work with Xilinx FPGA. The results look pretty good, And their boards aren't much more than a BasicStamp2.
But there isn't anything wrong with Verilog or VDHL or Quartus, but they don't lend themselves to sloppy thinking and coding. You need to really think about what you're doing. What is difficult to is come up with a design that works and works reliably.
I think wherever there is complexity there's also great opportunity in eliminating/minimizing that complexity.
You're probably right about about verilog being unforgiving, but not everyone will have to dive into the verilog to get a result. And it's probably correspondingly rewarding when it does work : )
"-- I don't see this happening for several reasons.... "
Yes, I just asked in case that you were ocious. Just not to lose those 8 years at 12 hours per day in a way that would benefit you (and parallax) and everyone too (hopefully, giving birth a Propeller brother).
The fixed-locked design was not supposed to be an issue (in that hypothetical project), because nobody but you was able (and allowed) to define the design and execute it. The main issue was related on how to balance the project NRE and rewards to make it succesful.
How large would the area of a shrinked P1 in 180nm be? I suppose that half the size in a linear scale plus some percentage to allow non-shrinkable pads and analog. If P1 at 350nm was 53 mm square (7.28 x 7.28 mm), can a shrinked P1 @180nm fit in 4x4 mm or 5x5 mm?
Current AMS shuttle prices are around 1300 Euros per mm square. That means 20,800 (for 16mm2) or up to 32,500 Euros (for 25mm2). This amount is above ther mimimum charge (Eur 18,900) for a standard shuttle run that delivers 40 dice (without packaging). The price per dice is high. But they allows to order an additional 100 dices (two lots) per shuttle paying extra 5000 euros. That means 185 euros per dice (@16mm2) or 268 euros if size is 25 mm2 and a total amount of 140 unpacked ICs.
Adding packaging and shipment cost will easily make each final packaged IC around US $500. That's probably too much to get funding succeed.
And that makes me think about another unrelated (?) issue. Who is going to buy the Parallax FPGA boards at US $500?
A lot of people in this forum already has one (or several) boards like DE-0, DE2-115, BEMICRO ... After 8 years, are they willing to spend yet another $500 in a new FPGA board?
75 FPGA boards at $500 means US $37,500. This is almost the same amount of the hypothetical 4x4 mm square design described above. The question is whether a 4x4 mm square design at 180nm can be done to get around the same amount or packaged ICs? But you are already working again, so the answer is NO.
To answer the original question of this thread ... The silence from parallax, makes me think about this three options:
- Parallax already has a working shuttle. The design house team are experts. They showed several months ago to Chip and Ken the available geometries in which this the design can be currently done. Instead of 180nm, they are going for the current low cost-low power geometry (that is 130nm LP) and the IC will fit in 6.4x6.4 mm (40.96 mm square). It will allow 64 TQFP too !!!!. They will announce the new P2 IC this summer (4th July) at initial price of US $23.99 80-TQFP. And they will sell evalution boards at $34.99 (a square board 2"x2", with 2.54mm spacing between pins, for total 80 pins), along with the new FPGA boards to start P3 design.
- The IC design house has not performed as expected. They are new to such kind of microcontroller design that never have heard before of. Project moves slowly, everytime they are asking more money to Parallax, and the project is at risk again. Parallax is looking ways to new revenue and want to make their own shuttle run again, so they will make their own crowdfunding project selling the FPGA boards to people willing to spend $500 and collaborate on the Verilog design. And those people will later receive a packaged IC as reward.
- The IC design house has a layout ready, but they don't have a working shuttle yet. So parallax will sell the $500 boards with the a FPGA P2 beta image to their high volume customers as a design prototype to get feedback.
In summary:
1) Specs are not yet defined, but maybe they have a working shuttle prototype. This looks like a paradox, but its not.
2) Expected date is not defined yet but probably can be something between 4 July 2015 and december 2016 (or never, but not before).
3) The price is also not defined yet, but according to current FPGA/Microcontrollers/XMOS pricing it will be near $23.99 or any other random value, but it is expected to be reduced by half (for high volume customers and also if sales grow up).
Thanks for the congrats! As far as anything else, Parallax will need to detail your specific questions. Too many variables have changed since I was at Parallax to give an educated answer at this point.
On thing I didn't see in your figures are the annual cost of the layout software required to do the layout design adequately. Originally the software license cost $45k a year but we had to contract for a 3 year locked agreement .... Last summer the layout software company Laker was acquired by another company called Synopsis increasing the annual license cost so much that Parallax could not justify paying me and the license fee, thus the reason for my layoff in October.
Yes, I did't mentioned anything about EDA software.
That maybe would require another 4 pages long thread discussing about the strange political-economic-military forces and mechanism that have keep a viable combination of free IC layout software tools and MPW foundries shuttle runs out of the reach of anyone but selected corporations and individuals for several decades.
Maybe somewhere near 2035 we will be able to cook P1 verilog in a free open source synthetizer (with Qflow 8.16, Yosys 7.10, and OpenRAM 6.25 versions) and make the IC with a desktop DIY CNC CVD UV-248nm EBL 1" Vacuum Wafer-printer-and-packager as easy as toasting bread.
Wow. That's some $$$ I saw a lot of SYNOPSIS ads while in Cali earlier. It's tough when the software companies merge, and I've seen that kind of thing before. A lot of the funding for the merge / buy happens on the backs of people on software.
(Always by a perpetual license, if you can kids. You can maintain it, or drop it and stay at a version... Best option, even when that costs a bit more up front.)
FEA simulation comes with similar dollar figures. $50K plus for a multi-physics, multi-core seat isn't uncommon. Maintenance on that can run 20 percent plus too. It's often easier to use a service where the seats are well funded by billing people out.
Seems layout has similar metrics, but a bit more brutal software terms. Ouch! Sorry that happened Beau. Thanks for some of the back story. It's good to understand.
One other obvious thing here is that smaller or niche players are largely shut out.
Honestly, given the time, expenses, things learned, I'm considering the current experiences quite valuable. And when we get a P2 chip to jam on, it's a notable accomplishment. If you all remember, dev costs were pegged at about $1 Million and some change. Most of this has been funded through ongoing business activity, and that's to avoid outside investment and or a line of credit burden that could significantly impact the Parallax risk profile, and thus it's costs.
In business terms, that's known as boot strapping, and it's not always quick to market, but it is frequently easier to manage risks and costs and remain viable while building new things. I can't blame a private company for taking that path. With $$$ incoming, there are also expectations. We, as customers, may not like the implications those expectations may have.
I know Chip really wants to do this, and he gets a lot out of it, as do we. It's not the usual business scenario. Part of the reason Parallax exists is due to people really wanting to do stuff. Count me as a fan.
Try to think about it all with some perspective. I am.
Re: Another FPGA board that might end up on Ebay
Me? Yes. Saving pennies right now.
And got in at a reasonable price the first time, because I shared my DE2 with a student, meaning it's an academic investment, not production. No way it will end up on Ebay as that's not what the vendor had planned when they let it go for the low cost they did. It's important to have those access programs, and we won't if they are abused. So I'll treat Terasic right and get it into the hands of somebody, who I can count on to continue doing the right thing, and who wants to learn.
Some people did pick up those boards at free to resell costs. They can and should put them on Ebay to maximize their dollars. I'm sure the buyer can get a lot out of it. There are some other DE2 projects out there that may be interesting too. Lots to do there. No harm, no foul for anybody really.
Many others chose the cheaper NANO boards.
Either way, I know I learned a whole lot! Never did much with FPGA devices before, and the bootstrapping / testing type work we all did was high value. Worth it.
For those here who really understand what FPGAs can do, it's maybe more of a wash. Fair enough.
This current design is a good one. We were split across a number of lines. Major design conflict. Chip and Roy kicked it all around, realized they could take a trick from GPU land, seriously improve the HUB, and delegate some tasks right to the pins. The result is really interesting and something I want to see happen.
I know there are some questions about the egg-beater HUB and the Smart Pins. I think both are going to play out well. HUB throughput is going to be off the charts great and that's one difficulty with P1 gone, and with twice the number of COGS! Count me in. It will take a bit to get used to, but once we do, that kind of throughput is really going to maximize what the COGS can do together. P1 is only a taste! The Smart Pins are something I'm confident Chip can make work well.
There are some buffering issues left on the table. Maybe Chip has those sorted now, or completing that will be FPGA task one.
P2 will be another highly differentiated design that keeps a lot of what makes P1 great, while adding some new and powerful ideas.
We will be able to take a lot of what we know how to do on a P1 and continue on, while these changes will require some effort, the results hold a lot of promise. This is really good news, and I'll bet we see enough FPGA buyers to test it out and maximize it all too.
Finally, Chip says he will support some of the other boards for a while. The new design fits in a NANO, so maybe we will get NANO, DE2, and the Parallax board, which I'll start to refer to as the reference design, just like we have always had. (Demo Board, Proto Board, SPIN, PASM, etc... all done by reference designs, and it's all played out just fine.)
Of course, this means those boards don't really need to go to Ebay right away, or we can get them distributed to people really interested in this project. I'm open to that.
Above all, I believe in Parallax. I want this to see success. Seeing Chip light up about these things and Ken and all the others at Parallax really enjoy seeing us do well in our various ways, and the community as a whole is all a fine thing. My only regret is not finding out about it all earlier!
One other thing: Some seriously interesting work went into the P2 "Hot." It's not like that effort was entirely wasted. I can see some of the better ideas bubbling up sometime in the future, ideally the future after we've got a real P2 out there for everybody to use.
This is *precisely* why we need someone like Parallax to dive into this area [ FPGA ] and pave the way for us. Like the basic stamp and propeller have done.......Fortunately we don't have to wrestle the toolchain. Its relatively simple to use the stand alone programmer to burn a P1V or P2 image, and probably even have a P3 image (note the new Parallax FPGA board title). It doesn't have to be as complex as it seems
I don't see how it is possible.
FPGA's are much more expensive. This is not going to fly as a BASIC Stamp, Propeller, Arduino, Espruino, MicroPython, whatever competitor/alternative.
Playing with a P1 or P2 image on an FPGA booard is great for those who have the skills to do it, or want to acquire them. We can experiment with tweaking a P1 configuration for example. Or add extra bells and whistles. Importantly that FPGA board can also be used for other things if people get into logic design like that.
It's a fine educational device but expensive.
My view is that even with the recent, relatively cheap, FPGA boards for hobbyists this is a very niche field and will remain so for the foreseeable future.
What would really blow this mass FPGA market open would be for the arrival of Free and Open Source HLL compiler and synthesiser tools. Plus whatever else it is you need between HLL source and a working FPGA configuration.
Then, we might see a FPGA/ FPGA board gain huge traction, even if it is small and low end, like the Arduino did.
UC Berkeley are working on this with their Chisle hardware design software. But I think that still depends on the tools from Altera and co. to make a working device.
What would really blow this mass FPGA market open would be for the arrival of Free and Open Source HLL compiler and synthesiser tools. Plus whatever else it is you need between HLL source and a working FPGA configuration.
Free is already here, and I doubt anyone would want to actually compile the tools, so "open source' adds nothing to someone wanting to get working devices.
I'd rather have tools developed with pre-release silicon, than something cobbled months after release.
C++, fpga's are not.
Note my use of capitalization in "Free and Open Source". That is commonly understood today to mean Free Software as defined by the Free Software Foundation [http://www.fsf.org/] and Open Source Software as defined by the Open Source Software Initiative http://opensource.org/
So that is "free" as in "libre" not "free" as in "free beer". It's about software freedom not price.
As such, as far as I know there, is no Free software tool chain to get you from HLL source code to a working FPGA configuration. Correct me if I am wrong.
It is in large part due to the open source nature of it's hardware and software tools that the Arduino took off like it did.
It's true that nobody wants to compile their own toolchain. In the same way we don't compile our Linux based operating systems and open source applications. In the same way that Arduino users do not compile the GCC compiler or IDE they use. That is all beside the point.
It's likely that such a tool chain is so huge and complex that there is never going to be an open source alternative. But the fact that we have Linux and GCC and other huge complex softwares makes me think it's not impossible. There is for example a VHDL to C compiler written by one man, GHDL. That is only the tip of the FPGA iceberg of course.
It does not help that the means of creating an FPGA configuration is a closely guarded secret of the vendors, unlike the instruction sets of CPUs for which compilers can be written.
Both Xilinx and Altera have free versions of their tools for both Verilog and VHDL. They only work with the smaller devices but they are still useful for many people. Here is the Altera Web Edition:
As such, as far as I know there, is no Free software tool chain to get you from HLL source code to a working FPGA configuration. ...
It does not help that the means of creating an FPGA configuration is a closely guarded secret of the vendors, unlike the instruction sets of CPUs for which compilers can be written.
There is no toolchain yet (not something as easy as "make myverilog.v") but some working pieces. And a lot of clever people working on that closely guarded secret.
Sorry Heater. I didn't read your post properly where you mentioned the distinction between Free and free. The X and A tools aren't Free.
I've just spent a couple of hours installing the latest Altera tools. Although I have quite a fast connection (> 20 Mbps) the actual download speed was rather slow, probably because of other people doing the same thing. I then spent another 30 minutes downloading the Cyclone IV and V device files. A test compilation worked OK.
But the fact that we have Linux and GCC and other huge complex softwares makes me think it's not impossible.
They are VERY different beasts, not able to be compared.
Yes, you can get 3rd party FPGA front ends, for an interesting one look at http://www.myhdl.org/
I think there even was offered Free Simulator (Icarus ?)
However, for the back end things like timing driven device routers and fitters ? Forget it.
Also the devices themselves are neither open source nor free, so the 'Free' pitch fails right there.
They are VERY different beasts, not able to be compared.
Do you really know that?
They are very different beasts for sure.
The only reason they cannot be compared is that we cannot see the millions of lines of code in their implementation or the specification to which it is written.
I am very sure the Linux kernel project is much bigger and more complex.
It seems to me that if the means of creating an FPGA configuration was public knowledge and if there were enough geeks wanting to create tools to do that, then it would be done. Slowly but surely, like the emergence of GCC and the Linux kernel.
Of course the FPGA vendors don't want to tell you how to do that.
There is one significant difference with Linux, and that's who's using it and why it got investment. Linux could be called a last stand collaborative response to the evolving ecology (read, Wintel) of the eighties and nineties. With the GPL being a critical factor in the stability of the collaboration.
PS: It's a beautiful example of the prisoners dilemma with a rule that fosters hanging in there.
Comments
I think that is a good opening, Parallax can address pretty much right now.
They do plan a large FPGA board, but that will be Niche for P2 development and $hundreds.
I think a smaller module board with a P1 and P1V using a MAX10 allows a common tool chain ecosystem, and they can leverage on the P1-FPGA loader they plan on the large board.
Such a board would allow development of projects that might logically move to P2 when it ships.
It could also field prove the Smart-Pin P2 cells, if Parallax wanted to, and seed Library support for them.
It certainly reaches way above where P1 can right now.
Do you mean P1 or P2 ?
There is a large enough area of FPGA usage that is effectively smart-RAM, and if the P2 manages 512K+ of RAM, then it can compete quite well in that niche. So it does not 'replace a FPGA' so much as displace a FPGA usage.
Check out the prices of Dual Port memory.
http://www.xmos.com/products/silicon/u-series
An FPGA is a sea of logic blocks. Logic blocks are arrangements of combinatorial and sequential logic that can be configured to perform a variety of functions. All logic blocks are the same. They are all interconnected by a configurable matrix. Those configurations are generated from VHDL/Verilog that defines the functionality you want.
So, what if you made the logic blocks a bit more complex and more flexible. Use actual CPU's instead of logic blocks. They are "configured" using normal programming languages. Now replace that interconnect matrix with high speed communication channels, or just shared RAM. Again that interconnect is defined in the normal programming language.
Bingo! you have a replacement for the FPGA out of a mass of processors.
Now, of course those CPU's are never going to be as fast as those logic units. And you may never get so many of them on a chip. But you have a viable FPGA replacement for low end FPGA tasks that is a thousand times easier to program. It also has some advantages, like simply being able to run application software as well, no need to put a soft core CPU in your FPGA to do that.
That is the idea behind the multi-core XMOS devices and the Prop is leaning in that direction. Admittedly the Prop 1 is a lot slower but there we go.
Verilog is terrible. So is VHDL. We may be able to get to grips with it but I don't think the regular programmers of the world would have an easy time of it without a lot of study and practice.
Yes, academics may well be reinventing the wheel. In the case of Chisle for good reason. The main problem with all this is that no matter how easy you make a hardware description language you still need those huge and complex tools from the FPGA vendors to synthesize the design for their devices.
Yes, as I said, low end FPGA tasks. Certainly there is not the speed for HDMI and ethernet. That is an issue that can, to a certain extent be helped with some flexible serdes and clocked IO peripheral hardware. That is the approcach taken by XMOS and the new LowRISC design.
I don't see Parallax getting much gain from becoming an FPGA board supplier. There are many of those already. Unless they could magically make an FPGA as popular as the Arduino made the micro-controller I don't see that idea going anywhere. The big stumbling block as I said is the need to have those huge, complex and slow, development softwares from the FPGA manufacturer to do anything with an FPGA.
FPGAs use the latest technology, Xilinx is already announcing 20nm and 16nm products.
GreenArray and XMOS raised a bunch of money probably to afford the mask sets, I'm not sure which process they ended up using, my WAG would be 60nm maybe 45.
So big FPGAs (yes expensive in low volume, but Cisco and the like don't pay a lot for them) will be 100 times denser in memory/logic.
As for programmers and HDL, I actually know a couple software guys that converted over and are some of the hotshot "hardware" designers in Silicon Valley (both at billion $ + fabless semi companies)
To get the most out of a Parallax COG, you need to be writing in ASM, and I find few software people these days that know much about any assembly language.
I'll make username happy and go to sleep now, looking forward to P2 in 2016.
I see you're still fixated on large volume products. Parallax has never in it's entire history been operating in such markets. EDIT: Not to say that a deal couldn't be reached if there was someone ready to put down an order for a few million units in one run.
Or use someone else's code from the object exchange. Even maybe get it tweaked to your needs via forum questions. And there is cogC option also, I'm not sure how well that works but it's there. Linking in soft devices is easy with Spin, and not too hard with C.
This is *precisely* why we need someone like Parallax to dive into this area and pave the way for us. Like the basic stamp and propeller have done.
It'd be interesting to set Andy and Stephanie onto this and see what they came up with
Fortunately we don't have to wrestle the toolchain. Its relatively simple to use the stand alone programmer to burn a P1V or P2 image, and probably even have a P3 image (note the new Parallax FPGA board title).
It doesn't have to be as complex as it seems
The GadgetFactory is already way ahead of them. They already adopted the Arduino IDE to work with Xilinx FPGA. The results look pretty good, And their boards aren't much more than a BasicStamp2.
But there isn't anything wrong with Verilog or VDHL or Quartus, but they don't lend themselves to sloppy thinking and coding. You need to really think about what you're doing. What is difficult to is come up with a design that works and works reliably.
I think wherever there is complexity there's also great opportunity in eliminating/minimizing that complexity.
You're probably right about about verilog being unforgiving, but not everyone will have to dive into the verilog to get a result. And it's probably correspondingly rewarding when it does work : )
"-- I don't see this happening for several reasons.... "
Yes, I just asked in case that you were ocious. Just not to lose those 8 years at 12 hours per day in a way that would benefit you (and parallax) and everyone too (hopefully, giving birth a Propeller brother).
The fixed-locked design was not supposed to be an issue (in that hypothetical project), because nobody but you was able (and allowed) to define the design and execute it. The main issue was related on how to balance the project NRE and rewards to make it succesful.
How large would the area of a shrinked P1 in 180nm be? I suppose that half the size in a linear scale plus some percentage to allow non-shrinkable pads and analog. If P1 at 350nm was 53 mm square (7.28 x 7.28 mm), can a shrinked P1 @180nm fit in 4x4 mm or 5x5 mm?
Current AMS shuttle prices are around 1300 Euros per mm square. That means 20,800 (for 16mm2) or up to 32,500 Euros (for 25mm2). This amount is above ther mimimum charge (Eur 18,900) for a standard shuttle run that delivers 40 dice (without packaging). The price per dice is high. But they allows to order an additional 100 dices (two lots) per shuttle paying extra 5000 euros. That means 185 euros per dice (@16mm2) or 268 euros if size is 25 mm2 and a total amount of 140 unpacked ICs.
Adding packaging and shipment cost will easily make each final packaged IC around US $500. That's probably too much to get funding succeed.
And that makes me think about another unrelated (?) issue. Who is going to buy the Parallax FPGA boards at US $500?
A lot of people in this forum already has one (or several) boards like DE-0, DE2-115, BEMICRO ... After 8 years, are they willing to spend yet another $500 in a new FPGA board?
75 FPGA boards at $500 means US $37,500. This is almost the same amount of the hypothetical 4x4 mm square design described above. The question is whether a 4x4 mm square design at 180nm can be done to get around the same amount or packaged ICs? But you are already working again, so the answer is NO.
To answer the original question of this thread ... The silence from parallax, makes me think about this three options:
- Parallax already has a working shuttle. The design house team are experts. They showed several months ago to Chip and Ken the available geometries in which this the design can be currently done. Instead of 180nm, they are going for the current low cost-low power geometry (that is 130nm LP) and the IC will fit in 6.4x6.4 mm (40.96 mm square). It will allow 64 TQFP too !!!!. They will announce the new P2 IC this summer (4th July) at initial price of US $23.99 80-TQFP. And they will sell evalution boards at $34.99 (a square board 2"x2", with 2.54mm spacing between pins, for total 80 pins), along with the new FPGA boards to start P3 design.
- The IC design house has not performed as expected. They are new to such kind of microcontroller design that never have heard before of. Project moves slowly, everytime they are asking more money to Parallax, and the project is at risk again. Parallax is looking ways to new revenue and want to make their own shuttle run again, so they will make their own crowdfunding project selling the FPGA boards to people willing to spend $500 and collaborate on the Verilog design. And those people will later receive a packaged IC as reward.
- The IC design house has a layout ready, but they don't have a working shuttle yet. So parallax will sell the $500 boards with the a FPGA P2 beta image to their high volume customers as a design prototype to get feedback.
In summary:
1) Specs are not yet defined, but maybe they have a working shuttle prototype. This looks like a paradox, but its not.
2) Expected date is not defined yet but probably can be something between 4 July 2015 and december 2016 (or never, but not before).
3) The price is also not defined yet, but according to current FPGA/Microcontrollers/XMOS pricing it will be near $23.99 or any other random value, but it is expected to be reduced by half (for high volume customers and also if sales grow up).
Have a nice April 1 !
Thanks for the congrats! As far as anything else, Parallax will need to detail your specific questions. Too many variables have changed since I was at Parallax to give an educated answer at this point.
On thing I didn't see in your figures are the annual cost of the layout software required to do the layout design adequately. Originally the software license cost $45k a year but we had to contract for a 3 year locked agreement .... Last summer the layout software company Laker was acquired by another company called Synopsis increasing the annual license cost so much that Parallax could not justify paying me and the license fee, thus the reason for my layoff in October.
Chip is nowhere near finished the verilog. End of story.
That maybe would require another 4 pages long thread discussing about the strange political-economic-military forces and mechanism that have keep a viable combination of free IC layout software tools and MPW foundries shuttle runs out of the reach of anyone but selected corporations and individuals for several decades.
Maybe somewhere near 2035 we will be able to cook P1 verilog in a free open source synthetizer (with Qflow 8.16, Yosys 7.10, and OpenRAM 6.25 versions) and make the IC with a desktop DIY CNC CVD UV-248nm EBL 1" Vacuum Wafer-printer-and-packager as easy as toasting bread.
Evanh, really? Opps ... Now you had me worried !
But thats no problem however, add just 2 weeks to the previous dates. (18 July 2015 - 15 Jan 2017)
(Always by a perpetual license, if you can kids. You can maintain it, or drop it and stay at a version... Best option, even when that costs a bit more up front.)
FEA simulation comes with similar dollar figures. $50K plus for a multi-physics, multi-core seat isn't uncommon. Maintenance on that can run 20 percent plus too. It's often easier to use a service where the seats are well funded by billing people out.
Seems layout has similar metrics, but a bit more brutal software terms. Ouch! Sorry that happened Beau. Thanks for some of the back story. It's good to understand.
One other obvious thing here is that smaller or niche players are largely shut out.
Honestly, given the time, expenses, things learned, I'm considering the current experiences quite valuable. And when we get a P2 chip to jam on, it's a notable accomplishment. If you all remember, dev costs were pegged at about $1 Million and some change. Most of this has been funded through ongoing business activity, and that's to avoid outside investment and or a line of credit burden that could significantly impact the Parallax risk profile, and thus it's costs.
In business terms, that's known as boot strapping, and it's not always quick to market, but it is frequently easier to manage risks and costs and remain viable while building new things. I can't blame a private company for taking that path. With $$$ incoming, there are also expectations. We, as customers, may not like the implications those expectations may have.
I know Chip really wants to do this, and he gets a lot out of it, as do we. It's not the usual business scenario. Part of the reason Parallax exists is due to people really wanting to do stuff. Count me as a fan.
Try to think about it all with some perspective. I am.
Re: Another FPGA board that might end up on Ebay
Me? Yes. Saving pennies right now.
And got in at a reasonable price the first time, because I shared my DE2 with a student, meaning it's an academic investment, not production. No way it will end up on Ebay as that's not what the vendor had planned when they let it go for the low cost they did. It's important to have those access programs, and we won't if they are abused. So I'll treat Terasic right and get it into the hands of somebody, who I can count on to continue doing the right thing, and who wants to learn.
Some people did pick up those boards at free to resell costs. They can and should put them on Ebay to maximize their dollars. I'm sure the buyer can get a lot out of it. There are some other DE2 projects out there that may be interesting too. Lots to do there. No harm, no foul for anybody really.
Many others chose the cheaper NANO boards.
Either way, I know I learned a whole lot! Never did much with FPGA devices before, and the bootstrapping / testing type work we all did was high value. Worth it.
For those here who really understand what FPGAs can do, it's maybe more of a wash. Fair enough.
This current design is a good one. We were split across a number of lines. Major design conflict. Chip and Roy kicked it all around, realized they could take a trick from GPU land, seriously improve the HUB, and delegate some tasks right to the pins. The result is really interesting and something I want to see happen.
I know there are some questions about the egg-beater HUB and the Smart Pins. I think both are going to play out well. HUB throughput is going to be off the charts great and that's one difficulty with P1 gone, and with twice the number of COGS! Count me in. It will take a bit to get used to, but once we do, that kind of throughput is really going to maximize what the COGS can do together. P1 is only a taste! The Smart Pins are something I'm confident Chip can make work well.
There are some buffering issues left on the table. Maybe Chip has those sorted now, or completing that will be FPGA task one.
P2 will be another highly differentiated design that keeps a lot of what makes P1 great, while adding some new and powerful ideas.
We will be able to take a lot of what we know how to do on a P1 and continue on, while these changes will require some effort, the results hold a lot of promise. This is really good news, and I'll bet we see enough FPGA buyers to test it out and maximize it all too.
Finally, Chip says he will support some of the other boards for a while. The new design fits in a NANO, so maybe we will get NANO, DE2, and the Parallax board, which I'll start to refer to as the reference design, just like we have always had. (Demo Board, Proto Board, SPIN, PASM, etc... all done by reference designs, and it's all played out just fine.)
Of course, this means those boards don't really need to go to Ebay right away, or we can get them distributed to people really interested in this project. I'm open to that.
Above all, I believe in Parallax. I want this to see success. Seeing Chip light up about these things and Ken and all the others at Parallax really enjoy seeing us do well in our various ways, and the community as a whole is all a fine thing. My only regret is not finding out about it all earlier!
One other thing: Some seriously interesting work went into the P2 "Hot." It's not like that effort was entirely wasted. I can see some of the better ideas bubbling up sometime in the future, ideally the future after we've got a real P2 out there for everybody to use.
FPGA's are much more expensive. This is not going to fly as a BASIC Stamp, Propeller, Arduino, Espruino, MicroPython, whatever competitor/alternative.
Playing with a P1 or P2 image on an FPGA booard is great for those who have the skills to do it, or want to acquire them. We can experiment with tweaking a P1 configuration for example. Or add extra bells and whistles. Importantly that FPGA board can also be used for other things if people get into logic design like that.
It's a fine educational device but expensive.
My view is that even with the recent, relatively cheap, FPGA boards for hobbyists this is a very niche field and will remain so for the foreseeable future.
What would really blow this mass FPGA market open would be for the arrival of Free and Open Source HLL compiler and synthesiser tools. Plus whatever else it is you need between HLL source and a working FPGA configuration.
Then, we might see a FPGA/ FPGA board gain huge traction, even if it is small and low end, like the Arduino did.
UC Berkeley are working on this with their Chisle hardware design software. But I think that still depends on the tools from Altera and co. to make a working device.
Free is already here, and I doubt anyone would want to actually compile the tools, so "open source' adds nothing to someone wanting to get working devices.
I'd rather have tools developed with pre-release silicon, than something cobbled months after release.
C++, fpga's are not.
Note my use of capitalization in "Free and Open Source". That is commonly understood today to mean Free Software as defined by the Free Software Foundation [http://www.fsf.org/] and Open Source Software as defined by the Open Source Software Initiative http://opensource.org/
So that is "free" as in "libre" not "free" as in "free beer". It's about software freedom not price.
As such, as far as I know there, is no Free software tool chain to get you from HLL source code to a working FPGA configuration. Correct me if I am wrong.
It is in large part due to the open source nature of it's hardware and software tools that the Arduino took off like it did.
It's true that nobody wants to compile their own toolchain. In the same way we don't compile our Linux based operating systems and open source applications. In the same way that Arduino users do not compile the GCC compiler or IDE they use. That is all beside the point.
It's likely that such a tool chain is so huge and complex that there is never going to be an open source alternative. But the fact that we have Linux and GCC and other huge complex softwares makes me think it's not impossible. There is for example a VHDL to C compiler written by one man, GHDL. That is only the tip of the FPGA iceberg of course.
It does not help that the means of creating an FPGA configuration is a closely guarded secret of the vendors, unlike the instruction sets of CPUs for which compilers can be written.
http://www.altera.com/products/software/quartus-ii/web-edition/qts-we-index.html
There are both Windows and Linux versions.
You don't even need any hardware if you want to learn Verilog or VHDL as the supplied Modelsim simulator is excellent.
There is no toolchain yet (not something as easy as "make myverilog.v") but some working pieces. And a lot of clever people working on that closely guarded secret.
http://www.clifford.at/yosys/cmd_synth_xilinx.html
http://www.eevblog.com/forum/microcontrollers/open-source-software-for-verilog-synthesis/
http://www.isi.edu/~nsteiner/publications/soni-2013-bitstream-fccm13.pdf
http://www.ece.ubc.ca/~eddieh/vtr-to-bitstream.html
http://www.ece.ubc.ca/~eddieh/hung_fccm13.pdf
http://torc-isi.sourceforge.net/documents/fpga2011-torc.pdf
https://vimeo.com/59160413
Thanks, that is all interesting stuff.
I've just spent a couple of hours installing the latest Altera tools. Although I have quite a fast connection (> 20 Mbps) the actual download speed was rather slow, probably because of other people doing the same thing. I then spent another 30 minutes downloading the Cyclone IV and V device files. A test compilation worked OK.
They are VERY different beasts, not able to be compared.
Yes, you can get 3rd party FPGA front ends, for an interesting one look at
http://www.myhdl.org/
I think there even was offered Free Simulator (Icarus ?)
However, for the back end things like timing driven device routers and fitters ? Forget it.
Also the devices themselves are neither open source nor free, so the 'Free' pitch fails right there.
They are very different beasts for sure.
The only reason they cannot be compared is that we cannot see the millions of lines of code in their implementation or the specification to which it is written.
I am very sure the Linux kernel project is much bigger and more complex.
It seems to me that if the means of creating an FPGA configuration was public knowledge and if there were enough geeks wanting to create tools to do that, then it would be done. Slowly but surely, like the emergence of GCC and the Linux kernel.
Of course the FPGA vendors don't want to tell you how to do that.
PS: It's a beautiful example of the prisoners dilemma with a rule that fosters hanging in there.