Companion parts for Prop 2

jmgjmg Posts: 12,618
edited November 2014 in Propeller 2 Vote Up0Vote Down
Following from this comment
cgracey wrote: »
Here's the Spin2 Interpreter, so far:

Attachment not found.

This interpreter is for the built-in 17-bit address space (128KB), but can easily be changed to 32-bit XMM. I started out on the 32-bit addressing path, but figured it was more practical, at first, to make a native 17-bit version, as an external SDRAM can easily be managed by Spin code for huge data.

This interpreter leaves the first $150+ longs in the cog free for in-line assembly code and terminate-stay-resident type applications which can run concurrently with the interpreter via hardware multi-tasking.....

and seeing this new Si504 Clock device (32Khz ~ 100MHz) :
http://news.silabs.com/press-release/product-news/silicon-labs-introduces-industrys-first-single-die-mems-oscillator
http://www.silabs.com/products/clocksoscillators/mems/Pages/si504.aspx
http://www.silabs.com/Support%20Documents/TechnicalDocs/Si504.pdf

claims price " begins at $0.44 /10k", and it looks simple to talk to : 1 pin, but edge-change-modulated, so would need PASM, and it directly accepts a real number, and an (optional) offset integer.

Some command code examples :

NewFreq [0x0C] + 4 Bytes (floating point 32-bit IEEE-754 number in Hz, MSB first)
OffsetFreq [0x3A] + 2 Bytes (signed integer MSB first) Offset Frequency in increments of 29.8 ppb (or 2^-25).

A small portion of that first $150+ longs in the cog free for in-line assembly code could load the Frequency.

This little part would complement the PLL, and it looks like the Offset mode allows a digital trim to lock to something like a GPS 1pps.

Depending on the 'real' price of the Si504, this could be a great part to place on any Prop 2 breakout board.
«13

Comments

  • 78 Comments sorted by Date Added Votes
  • cgraceycgracey Posts: 10,542
    edited July 2013 Vote Up0Vote Down
    HDTV needs a clock of 148.5MHz. If the Prop2 XIN frequency can be some simple division of 148.5MHz, then dot crawl can be totally eliminated. I didn't read the datasheet for that clock generator, but if it can start up in some known mode and then be configured, that's all you'd need for the Prop2.
  • jmgjmg Posts: 12,618
    edited July 2013 Vote Up0Vote Down
    The Si50x series have different models - some are fixed, or pin-selectable, and the more interesting Real-Number programmable Si504 data says this

    ["From initial power up, the Si504 starts in Run mode with the output frequency and device configuration set to the ordered configuration."]

    ie SiLabs provide each unit with a default Fo, and you can change from there, as needed.
    Hopefully they will generate some 'standard values' for stocking. - I guess 13.50MHz or 6.75MHz would do for 148.5MHz ?

    27MHz is more common, is the Prop 2 PLL VCO divided before it is used ?
  • cgraceycgracey Posts: 10,542
    edited July 2013 Vote Up0Vote Down
    jmg wrote: »
    The Si50x series have different models - some are fixed, or pin-selectable, and the more interesting Real-Number programmable Si504 data says this

    ["From initial power up, the Si504 starts in Run mode with the output frequency and device configuration set to the ordered configuration."]

    ie SiLabs provide each unit with a default Fo, and you can change from there, as needed.
    Hopefully they will generate some 'standard values' for stocking. - I guess 13.50MHz or 6.75MHz would do for 148.5MHz ?

    27MHz is more common, is the Prop 2 PLL VCO divided before it is used ?

    The Prop2's main clock PLL can multiply by any integer from 2 to 16. It is designed to work optimally with 10MHz or 20MHz crystals, or a clock input signal in that range.

    An input of 13.5MHz would be good, since it could be multiplied by 11 to get 148.5MHz.
  • jmgjmg Posts: 12,618
    edited July 2013 Vote Up0Vote Down
    cgracey wrote: »
    The Prop2's main clock PLL can multiply by any integer from 2 to 16. It is designed to work optimally with 10MHz or 20MHz crystals, or a clock input signal in that range.

    An input of 13.5MHz would be good, since it could be multiplied by 11 to get 148.5MHz.

    Some PLLs run higher than the SysCLK, often x2 or x4, so they can divide by 2 to get a precise 50% duty cycle to work with on the main Clock.

    Sounds like the Prop 2 does not do that ?
  • SapiehaSapieha Posts: 2,964
    edited July 2013 Vote Up0Vote Down
    Hi jmg.

    Propeler and Propeller 2 -- always multiply XIN by 16 then apply Yours desired divider.

    XIN x 16 / by 2-16

    jmg wrote: »
    Some PLLs run higher than the SysCLK, often x2 or x4, so they can divide by 2 to get a precise 50% duty cycle to work with on the main Clock.

    Sounds like the Prop 2 does not do that ?
    Regards
    Sapieha
    _____________________________________________________
    Nothing is impossible, there are only different degrees of difficulty.
    For every stupid question there is at least one intelligent answer.
    Don't guess - ask instead.
    If you don't ask you won't know.
    If your gonna construct something, make it as simple as possible yet as versatile/usable as possible.
  • cgraceycgracey Posts: 10,542
    edited July 2013 Vote Up0Vote Down
    Sapieha wrote: »
    Hi jmg.

    Propeler and Propeller 2 -- always multiply XIN by 16 then apply Yours desired divider.

    XIN x 16 / by 2-16

    On the Prop2, it's different. You can select x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, or x16 for the main clock PLL multiplier.
  • SapiehaSapieha Posts: 2,964
    edited July 2013 Vote Up0Vote Down
    Hi Chip.

    Thanks for clarify that.


    cgracey wrote: »
    On the Prop2, it's different. You can select x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, or x16 for the main clock PLL multiplier.
    Regards
    Sapieha
    _____________________________________________________
    Nothing is impossible, there are only different degrees of difficulty.
    For every stupid question there is at least one intelligent answer.
    Don't guess - ask instead.
    If you don't ask you won't know.
    If your gonna construct something, make it as simple as possible yet as versatile/usable as possible.
  • jmgjmg Posts: 12,618
    edited December 2013 Vote Up0Vote Down
    I'll bump this with a couple of new Companion Devices :

    MOSFET and Power Support Module

    The MCP8024 device integrates three half-bridge drivers to drive external NMOS/NMOS transistor pairs configured to drive a 3-phase BLDC motor, a comparator, a voltage regulator to provide bias to a companion microcontroller, power monitoring comparators, an overtemperature sensor, two level translators and three operational amplifiers for motor current monitoring.

    http://www.microchip.com/wwwproducts/Devices.aspx?product=MCP8024

    It has a single SMPS, which could do the 3v3 and then a SOT23 sized LV-SMPS can do Core Vcc
    Charge pump allows 100% FET Drive, so there are many Bridge apps
    Small enough to include on a Prop 2 Module ?

    Fast Serial Download

    http://www.silabs.com/products/interface/usbtouart/Pages/usb-to-spi-bridge.aspx
    Highlights :
    SPI Controller 3 or 4-wire master mode operation
    Configurable clock rate
    12 MHz, 6 MHz, 3 MHz, 1.5 MHz, 750 kHz, 375 kHz, 187.5 kHz, 93.75 kHz
    Ready-to-read pin allows for external signal to trigger SPI read operations
    Ability to count edges or pulses using the Event Counter
    Configurable clock output (93.75 kHz to 24 MHz)

    Claims Write speeds of 5.8 Mbps (12MHz CLK, one way), which would make downloads fly :)

    No UART modes, but maybe the new SerDes will flip between SPI and Async easily enough ?
  • jmgjmg Posts: 12,618
    edited January 2014 Vote Up0Vote Down
    .. and another Part, suited to both P1 and P2, and looking rather like a Prop-lite is this new device from Freescale

    www.freescale.com/psc

    The 33816 is a programmable gate driver IC for precision solenoid control applications.
    The IC consists of
    * five external MOSFET high-side pre-drivers
    * seven external MOSFET low-side pre-drivers.
    * four independent microcores, and two Code RAM and two Data RAM banks.
    * 9-32 V continuous supply, 5.5-58 V transient
    * Integrated DC-DC boost converter control circuitry (100% duty cycle capability)
    * Choice of four programmable slew rates 12.5 V/uS – 300 V/uS
    * Includes ADC and DAC's
    * 10 x 10 mm 64-pin LQFP-EP package


    The 4 Microcores pair over 2 x 1023 x 16-bit CODE RAM and 2 x 64 x 16-bit DATA RAM.
    So that's the same code area as a P1 COG, shared over 2 Microcores.

    Data sheet lists the Opcodes, but is a little vague on getting code into the CODE RAM ?
  • pedwardpedward Posts: 1,547
    edited January 2014 Vote Up0Vote Down
    cgracey wrote: »
    The Prop2's main clock PLL can multiply by any integer from 2 to 16. It is designed to work optimally with 10MHz or 20MHz crystals, or a clock input signal in that range.

    An input of 13.5MHz would be good, since it could be multiplied by 11 to get 148.5MHz.

    The P2 PLL goes to 11!!! :lol:
  • jmgjmg Posts: 12,618
    edited January 2014 Vote Up0Vote Down
    pedward wrote: »
    The P2 PLL goes to 11!!! :lol:

    Well, it goes to 16, but it can do 11, or 9, or 12 or 2 or .. ;)

    2..16 is cool - allows far more crystal choice, and 5MHz crystals are getting rare and large.
  • jmgjmg Posts: 12,618
    edited February 2014 Vote Up0Vote Down
    Lattice have finally revealed more on the MachXO3.
    BGA only at the moment, but small, and they have LCD serial support

    http://www.latticesemi.com/Products/FPGAandCPLD/MachXO3.aspx

    DSI LCD Display Interfacing

    Supports DSI transmit signaling
    HS (High Speed) Mode transmit
    LP (Low Power) Mode transmit and receive
    Can be implemented in a 49 wlcsp (3.2 x 3.2 mm)
    Supports DSI formats RGB, YCbCr and User Defined
    Input bus can also be DSI to enable LCD screen replacement


    That 3.2mm package is small, but shows as 3rd from smallest die family member.
    Not clear if the interface needs the IO, or needs the Logic, & Lattice have poor migration in the smallest packages.

    A 6mm 121 pin package is needed before you covers all 3 smallest parts, and I see 256 pins covers largest 4, in a choice of 0.5mm 9x9 or 0.8mm 14x14.


    No prices yet, but a device that fits in a 3.2mm package, cannot be too expensive ;)
  • jmgjmg Posts: 12,618
    edited February 2014 Vote Up0Vote Down
    Reading more on the MachXO3, it looks to have similar Logic and identical Fabric speeds to MachXO2, which means unlike most significant model increments, this has the same process - what Lattice added is the Fast DSI Serial.

    I think that means the MachXO2 prices can be used as guidelines, and that would make these parts relatively cheap.
    - likely cheaper and smaller than parts like the ADV7125, and it also means Parallax can add one of these to get LVDS video, without needing a new version of the device.

    Video standards change often enough, that a small, programmable device as the bridge makes good sense.
  • RamonRamon Posts: 354
    edited February 2014 Vote Up0Vote Down
    I was really dissapointed. I waited for 5 months after the announcement of XO3L just to find that it has so little improvement over MachXO2. Also if I remember right, 5 months ago they announced up to 22,000 elements (on par with the Cyclone IV used in DE0-nano) but 5 months later we found that the bigger one has only 6900 elements. Also packaging is only BGA for XO3L (much higher PCBA cost than current 100 tqfp or 144 tqfp available for XO2). Completely dissapointed. Five months wasted in waiting for XO3.

    It looks that maybe because they have too much stock in current XO2 CPLD, and XP2 FPGAs, and they made a lot of invesment with ICE40 they really cannot really improve the MachXO2. Who knows. Don't know if they will annouce the real XO3 in a few months (not XO3L).
  • jmgjmg Posts: 12,618
    edited February 2014 Vote Up0Vote Down
    Ramon wrote: »
    Completely dissapointed. Five months wasted in waiting for XO3.

    Yes, XO3 was a little underwhelming - exactly the same speed specs as XO2, but the LVDS is nice, for those apps that need it. - so it should give a nice way to add LVDS to a Prop2.

    Lattice seem slow to release sensible packages, maybe they chase only highest volume runs ?
  • RamonRamon Posts: 354
    edited February 2014 Vote Up0Vote Down
    jmg wrote: »
    Yes, XO3 was a little underwhelming - exactly the same speed specs as XO2, but the LVDS is nice, for those apps that need it. - so it should give a nice way to add LVDS to a Prop2.

    You are wrong. XO2 already has LVDS (also BLVDS, MVDS, LVPECL, RSDS). They even had a reference design for Video (RD1093).

    You can look at their own words 5 months ago:

    "The new MachXO3 FGPA family carries forward the non-volatile benefits of the two earlier families, which also include on-chip memory, remote field upgrades, low-power sleep mode, LVDS and other features.

    MachXO3 devices come with hardened DSP and 3.125Gbps SERDES capabilities, smaller packaging, higher density of I/O and logic cells, as well as hard and soft IP support for MIPI, PCIe, GbE and other emerging connectivity interfaces."


    Please read the attached PDF and compare what they announced and what we have 5 months later with their XO3L.
  • RamonRamon Posts: 354
    edited February 2014 Vote Up0Vote Down
    jmg wrote: »
    Reading more on the MachXO3, it looks to have similar Logic and identical Fabric speeds to MachXO2, which means unlike most significant model increments, this has the same process - what Lattice added is the Fast DSI Serial.

    No, the DSI is a soft IP that works on MachXO2, ECP3 and MachXO3L. I am still reading the datasheet to find what did they added (if any).
  • jmgjmg Posts: 12,618
    edited February 2014 Vote Up0Vote Down
    Ramon wrote: »
    You are wrong. XO2 already has LVDS (also BLVDS, MVDS, LVPECL, RSDS).

    OK, I can see I used too few words, LVDS comparators in XO2, are not quite LVDS Geared Video in XO3.

    This is some of what XO3 adds,

    Pre-Engineered Source Synchronous I/O
    • DDR registers in I/O cells
    • Dedicated gearing logic
    • 7:1 Gearing for Display I/Os
    •Generic DDR, DDRx2, DDRx4


    No figures on the DSI transmit signaling HS (High Speed) Mode transmit Gbps levels, but maybe the 3.125Gbps SERDES still applies ?
    Ramon wrote: »
    MachXO3 devices come with hardened DSP and 3.125Gbps SERDES capabilities, smaller packaging, higher density of I/O and logic cells, as well as hard and soft IP support for MIPI, PCIe, GbE and other emerging connectivity interfaces."[/i]

    Yes, no sign of DSP or GbE or PCIe on the devices released this far.

    Suggests another block are coming > 7900 to 22,000 with DSP/GbE etc ?
  • RamonRamon Posts: 354
    edited February 2014 Vote Up0Vote Down
    MachXO2 Family Data Sheet (DS1035):

    Pre-Engineered Source Synchronous I/O
    • DDR registers in I/O cells
    • Dedicated gearing logic
    • 7:1 Gearing for Display I/Os
    • Generic DDR, DDRX2, DDRX4
    • Dedicated DDR/DDR2/LPDDR memory with DQS support


    MachXO3L Family Data Sheet (DS1047):

    Pre-Engineered Source Synchronous I/O
    • DDR registers in I/O cells
    • Dedicated gearing logic
    • 7:1 Gearing for Display I/Os
    • Generic DDR, DDRx2, DDRx4


    So not only did they didn't added extra "marketing words", they even removed some.

    About 3.125Gbps SERDES, DSP or GbE or PCIe : NO. IT IS NOT THERE.


    Please, look at:

    1) http://www.latticesemi.com/dsitx
    2) RD1185
    3) MIPIDisplaySerialInterfaceSolutionProductFlyer
  • jmgjmg Posts: 12,618
    edited February 2014 Vote Up0Vote Down
    Ramon wrote: »
    About 3.125Gbps SERDES, DSP or GbE or PCIe : NO. IT IS NOT THERE.[/b]

    Now I am more confused, I thought from the hoopla that DSI (Display Serial Interface) was what they added in XO3, but if it is warmed over beans, what exactly is new ?


    I can see a moderate speed 7:1 video in the larger XO2
    MachXO2-640U @ 144 TQFP & MachXO2-1200 and above - which are all larger packages.

    and MachXO3 shows 7:1 on MachXO3L-2100 , but tables also suggest it is on XO3L-640 121-ball fcCSP (0.5, 6 x 6)
    - so that makes the XO3 maybe smaller (but in BGA)

    Hmm...
  • RamonRamon Posts: 354
    edited February 2014 Vote Up0Vote Down
    jmg wrote: »
    Now I am more confused, I thought from the hoopla that DSI (Display Serial Interface) was what they added in XO3, but if it is warmed over beans, what exactly is new ?

    XO3L doesn't have a configuration flash like XO2. The XO3L has NVCM (inherited from ICE40).

    XO2 configuration flash has 10,000 programming cycles, and 10 years data retention.

    The new XO3L has a Multi Time Programmable NVCM. (see datasheet and also TN1279).

    And how many times is "Multi Time"? TWO. Yes, 2.

    So what the have done is XO2 warmed beans with ICE40 NVCM to make ICs smaller, get "billions" of dies per wafer and thus reduce cost.

    How do you feel now?
    jmg wrote: »
    Hmm...
  • jmgjmg Posts: 12,618
    edited November 2014 Vote Up0Vote Down
    Another new device that is sure to be P2 - significant is the upcoming
    FTDI SuperSpeed USB 3.0 FT600 series

    Such a device will likely make the connected device the bottleneck, and might even be a candidate for the new DMA video style modes.

    FTDI also have the FT4222H, a SPI/i2c Bridge with High Speed USB, that gives intermediate price and speed.
    Lower cost and smaller than FT232H/FT2232H, but also slower.
  • edited November 2014 Vote Up0Vote Down
    Ramon wrote: »
    XO3L doesn't have a configuration flash like XO2. The XO3L has NVCM (inherited from ICE40).

    XO2 configuration flash has 10,000 programming cycles, and 10 years data retention.

    The new XO3L has a Multi Time Programmable NVCM. (see datasheet and also TN1279).

    And how many times is "Multi Time"? TWO. Yes, 2.

    So what the have done is XO2 warmed beans with ICE40 NVCM to make ICs smaller, get "billions" of dies per wafer and thus reduce cost.

    Two is probably overkill for anything in serial production. Especially if they're cheap.

    Sandy
    Infantryman's Axiom; Always cheat, always win.
  • jmgjmg Posts: 12,618
    edited November 2014 Vote Up0Vote Down
    Two is probably overkill for anything in serial production. Especially if they're cheap.

    Some price comparisons


    LCMXO2-7000HE-4FG484C 100 @ $21.21
    ( 240k RAM bits )

    LCMXO3L-6900C-5BG256C 100 @ $11.525
    ( 240k RAM bits )

    Altera MAX 10 : 8000 LE Total RAM Bits 387072
    10M08SAU169C8GES 100 @ $15.020
    10M08SAE144C8GES 100 @ $19.94

    BGA's except for one package choice in MAX 10 from Atera.
  • jmgjmg Posts: 12,618
    edited November 2014 Vote Up0Vote Down
    jmg wrote: »
    Another new device that is sure to be P2 - significant is the upcoming
    FTDI SuperSpeed USB 3.0 FT600 series

    Some specs are up http://www.ftdichip.com/Products/ICs/FT600.html

    Support for
    * USB3.0 SuperSpeed (5Gbps),
    * USB High Speed (480Mbps) and
    * USB 2.0 Full Speed(12Mbps) transfer
    * Available with either16bit/32bit wide parallel FIFO interface
    * Supports 2 parallel slave FIFO bus protocols, with data bursting rate up to 400Mbps
    * Supports multi channel FIFO interface
    * Up to 8 configurable endpoints (pipes)
    * Built-in 16kB FIFO data buffer RAM
    * Supports multi voltage I/O: 1.8V, 2.5V and 3.3V

    Looks to have some simple handshake lines, and given FTDI target CPLD/FPGA here, some verilog should be available, along with some Eval boards.

    Does look like a very good companion part for P2, as it gives very fast IO, and connectivity .

    A P2 board, in this form-factor
    http://www.raspberrypi.org/raspberry-pi-model-a-plus-on-sale/
    with a FT600 USB connection, would also add something for raspberrypi users.
  • AribaAriba Posts: 2,199
    edited November 2014 Vote Up0Vote Down
    jmg wrote: »
    Some price comparisons


    LCMXO2-7000HE-4FG484C 100 @ $21.21
    ( 240k RAM bits )

    LCMXO3L-6900C-5BG256C 100 @ $11.525
    ( 240k RAM bits )

    Altera MAX 10 : 8000 LE Total RAM Bits 387072
    10M08SAU169C8GES 100 @ $15.020
    10M08SAE144C8GES 100 @ $19.94

    BGA's except for one package choice in MAX 10 from Atera.

    to be fair:

    LCMXO2-7000HC-4TG144C 100 @ $11.55

    I wonder what the price of the smaller Max10 devices will be. I hope Altera looks a bit at the smaller MachXO3, they beat even the ICE40:
    LCMXO3L-1300E-5UWG36CTR50 50 @ $2.06
    LCMXO3L-2100E-5UWG49CTR50 100 @ $2.96

    Andy
  • jmgjmg Posts: 12,618
    edited November 2014 Vote Up0Vote Down
    This one is not yet a companion device, but it is going to be quite embedded relevant as a superset of i2c and SPI

    http://mipi.org/content/mipi-alliance-introduces-sensor-interface-specification-mobile-mobile-influenced-and-embedde

    Marketing buzzwords
    ["SenseWire incorporates and unifies key attributes of I2C and SPI while improving the capabilities and performance of each approach with a comprehensive, scalable interface and architecture"]

    and some numbers
    ["..a two-pin interface that is backward compatible with the I2C standard.. On standard CMOS I/O, it supports a minimum data rate of 10 Mbps with options for higher performance high-data-rate (HDR) modes"]

    This could become a 'simpler than USB option', and what rates are chosen for HDR could be interesting.
    DDR CMOS seems to be capable of around 100MHz, for 200MBd top data rates.

    There is a 5MHz i2c mode, that changes from Open Drain clock, to CMOS Clock/Data drive.
    QuadSPI memory has examples of dummy clocks to allow bus-turn-around.
  • Looks like there has finally been some action on the I3C Sensewire front. This is the protocol jmg posted about that enhances I2C towards SPI speeds, while keeping a 2 wire (SDA/SCL) topology.

    There's a whitepaper that goes into its features and benefits
    http://mipi.org/specifications/i3c%E2%84%A0-sensor-specification

    And there seems to be some IP available from synopsys or cadence.

    There's a Mipi developers conference next week in Mountain View
  • And the other interesting companion is the recently released ESP3212, which builds on from the ESP8266 but does both bluetooth and wifi, and has plenty of ram.

    Could make for an interesting wireless 'prop plug'.

    Some will be reassured that it uses both external flash and crystal, like we expect for P2
  • Ken,

    The last time I looked... that insignia on the ESP3212 was owned by Qaulcomm...
    cut them off at the pass!!!

    Shoot to kill.

    RIch
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