library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity JC5 is
port ( CLKi : in std_logic;
Qc0 : in std_logic;
Qc2 : in std_logic;
Qc4 : in std_logic;
Qc6 : in std_logic;
SRn : in std_logic;
John_D : out std_logic;
Qc1 : out std_logic;
Qc3 : out std_logic;
Qc5 : out std_logic);
end JC5;
architecture BEHAVIORAL of JC5 is
begin
FIELD Qc = [Qc6..Qc0];
John_D = !(Qc2 # Qc1); /* NOR gives 2H 3L */
Qc.d = !SRn & 'b'0000000
# SRn & [Qc5..Qc0,John_D];
end BEHAVIORAL;
I have tried this, but looks like i on the wrong way !
i use a Arduino with a atmega328 and the JTAGWhisperer sketch to programm the CPLD's.
I can programm 3.3V and 5V CPLD's.
Attached is a very simple project example, for PLCC84 ATF1508ASV, and I used AtmelISP to create a SVF file.(does pgm/vfy)
( Load AtmeISP and tick [Write SVF file] )
Try feeding that SVF file into your JTAGWhisperer, to see what it does.
In theory, SVF is universal standard, and I would expect it to cough with the device ID check until you have ATF1508ASV connected ? ( ie it should load and run that far )
In the Project .PLD and .SI are the equation and Simulation source files, and .DOC and .SO are the Equation and Simulate outputs of pass1.
.FIT is the final fitter report, and .JED is the file loaded into AtmelISP, which is used to create .SVF
The most user-useful files for post-run reading are .SO and .FIT
I have tried this, but looks like i on the wrong way !
Yes, the code I gave was for the Atmel WinCUPL tool flow, http://www.atmel.com/tools/WINCUPL.aspx
so it is not VHDL or Verilog, but a simpler Boolean Equation entry.
WInCUPL is fine for a few flipflops and gates (ie SPLD/CPLD designs), but I would not use it for a SoftCPU design.
The compiler is small to download, and very fast to compile, just like any assembler.
In the moment i try to build a ISE part of the counter.
Next i put in the logic in VHDL.
The Atmel fitter has an option to create Verilog or VHDL output files, which are flat and verbose, but do have a framework for downstream simulation tests. I've updated the zip file above, to include those report files.
A first step is to just feed it into your SVF player setup.
With no device connected, it should give a Device ID / not found message, but making it that far is a useful test of file compatibility.
A worse possible outcome is something like 'unrecognized SVF file' and no JTAG activity at all.
It converts the file but gives a error message: Delay must be in terms of TCK count
Hmm... I see the AtmelISP has two choices and one says something about TCK, so I've added both SVF format choices as _C and _D to the Zip file above. Might be that rev C is needed ?
Is it possible to use standard SDRAM like Dualport DRAM ?
Through the use of CPLD's or equal ?
Sure that is what the VGA display is, effectively one port reads, and one writes, in a ping pong fashion.
In a display, the read-bandwidth dominates, and writes have to fit into what is left over.
Interesting question re dualport ram. With CPLDs you can do things that might be impractical with a board of TTL chips. How about you have two standard sdram chips, and both contain the picture, and one is doing the display and the other is totally free to write to at whatever speed you like? Use the CPLD to toggle between the two displays (or four 245 chips). The timing would be simpler as don't need to try to squeeze data in during blanking periods, and thus the code would be simpler too as one cog could be devoted to displaying and another devoted to talking to the other ram chip.
What is the price differential between dualport ram vs sdram?
Dualport ram has 2 addressports and 2 dataports !
It's possible to read and write at the same time, in 2 different memory banks i think !
One idea is to use 2 SDRAM with the same size.
Picture data writing into the first one and in the same time data sending from the second into the videodac.
When the picture is ready writen into the first one then function changement of the two sdrams.
The fps depends on the writing speed into the sdram.
The picture can be shown as long the picture data writing isn't finished !
1 times, 2 times or 3 times !
Not to forget, the P8X32A has 8 cogs to menage different things at the same time !
I also found this mention on the 'net, which suggests this pathway does work ?
ATF15xx Programmer
For programming atmel cplds you can create a SVF file with ATMISP.exe. For more information have a look at this documentation (http://www.atmel.com/dyn/resources/prod_documents/DOC1936.PDF)
Afterwards convert the created SVF file into a XSVF file: use impact or svf2xsvf (both from xilinx).
Program the ATF15xx with the integrated XSVF-Player.
They forget to mention to use SVF export revision C, but it sounds like svf2xsvf is OK with Atmel created SVF files.
ISE Design Suit 14.5:
1) Start ISE Project Navigator
2) Click on 'New Project'
I'm not even sure what I have is the right program. I downloaded this huge program and there is just one icon on the screen called "Xilinx SDK 2013.1" Run this and if I go into Help/About it says it is
Xilinx Software Development Kit
Release Version: Release 14.5 Build SDK_P.58f
But at the top of the screen on the menu bar it says it is "C/C++ -Xilinx SDK".
I am not at home at the moment but the SDK isn't the one that I have used, ISE opens up into the right screen.
The problem wit the Xilinx SW is that you get all of the high end chips support and if you are lucky the low end stuff too. I am trying to remember if ther was a CPLD only SW from the old days, that is still available.
For 95XXX chips the 7.x - l2.x worked for me but I see that there is a Vivado (something like that anyway) that give pretty crocus pictures, but possibly not old CPLD support.
Looking at altera vs xilinx, I found an article somewhere that pointed out the CPLD chips are almost identical. So it the chips are similar, then maybe it comes down to the software. I can't find anything on the internet that looks like the screen I have. I have a theory that maybe it is because I am using Windows 8 and win8 doesn't have the start button (news flash - they are putting it back in the next version), so you get one shortcut on the desktop (sometimes) and sometimes you get another shortcut on the bottom toolbar, and sometimes on the touchscreen swipe menu. But what you don't get is the familiar start button where you would scroll to Xilinx and then run the programs in the Xilinx group. So my theory is there are other programs besides the "SDK", ie another one maybe called "ISE" but I can't find that one.
I've sent several hours on this now, endlessly searching the internet and Google Images, trying to find something like the 6.2Gb Xilinx SDK C/C++ editor that I seem to have been given.
But enough ranting!!
I shall thumb my nose at Xilinx by going on ebay and purchasing a product from their competitor - an Altera Cyclone II EP2C5T144 FPGA Board + Altera USB Blaster JTAG programmer for $43.90 and Free Shipping.
I am now downloading Altera's software. Hah - 2Gb smaller than Xilinx's.
Actually, I was heading to a FPGA anyway. CPLD's are great for replacing glue chips, but for a VGA design like this, with memory, the 44 pin ones may not have enough pins for things I want to experiment with (also experiments with touchscreens). Move up to the 84 pin ones, and the chips are twice the price. Add in the PLCC socket, and the jtag programming, and the fact Eagle doesn't seem to have library parts for the XC95 series with the higher pin counts, and it starts to add up. For not much more, FPGA has far more pins, has cores for almost everything you want (including SDRAM drivers and VGA drivers), and heck, why not throw in a Z80 core as well?
As an aside,run that Altera part number "EP2C5T144" past Google, and result #1 is from Leon, and result #3 is a discussion on, you guessed it, the Propeller forum (from a post by Leon from back in 2011).
I wonder where all that discussion went? There was some mighty clever boffinry going on there looking at hybridising the propeller and FPGA's.
Drac: Why don't you get the DE0-nano (Cyclone iv) that we are using to emulate a single P2 cog & hub. While its 2x the price from Element14, you will get it in a couple of days.
Drac: Why don't you get the DE0-nano (Cyclone iv) that we are using to emulate a single P2 cog & hub. While its 2x the price from Element14, you will get it in a couple of days.
Yep, he's right. The DE0-nano is a beautiful little board. Just the thing we need whilst waiting for the Prop II.
Actually developing anything for an FPGA like that is a problem. As you saw the downloads are huge, not such a worry now that we have tera byte hard drives. Worse is the fact that they are really slow at compiling your VHDL/verilog into a chip configuration. I'm going to need a serious upgrade to my PC's before tackling that, I just don't have the patience to wait for it produce something that is loadable.
Yes, there are a lot of nice and ready to go CPLD and FPGA boards.
But, before you purchase one it's a good idea to check the software you need to programm it.
When you want use the free version of the software then check the supported CPLD's and FPGA's !!!
After that you can purchase the board or/and purchase a higher license of the software if necessary !
WebPack License is Free but the lowest price license is the Logic Edition with $2995 !
And Altera's free software does not take a advantage of multicore processors so compilation is slow. Perhaps you would not want to use it for the bigger devices that it does not support anyway.
I have to religiously use stuff that I find scrapped, so that will leave me planning to build a Spartan 2E board (slightly this side of CPLDs, and the stone age).
I will try to recreate something like the XESS-100. It has the chicken-and-egg programming interface using a XC9572XL, and uses a parallel port, bless.
Drac: Why don't you get the DE0-nano (Cyclone iv) that we are using to emulate a single P2 cog & hub. While its 2x the price from Element14, you will get it in a couple of days.
That makes good sense if going to a FPGA, but a middle step could be the Lattice MachXO2
see
That looks relatively expensive,
Still interested in how the JTAGwhisperer works on Atmel converted SVF - but I have also found a cleaner pathway.
The Atmel ATDH1150USB is not easy to find, but it uses FT2232 device, and I have FT2232H here, so I figured that was worth a try...
Using AtmelISP set for USB & ATDH1150USB, it works great with ATF1508AS, ATF1502ASL, ATF1502ASV which were what I had handy. Verify, and Pgm/.Verify all worked. No SVF dance needed, and a standard FT2232H part works.
I actually used this, as it has a FT2232H mounted, and has a 8 way header for JTAG, Needed 2 cuts to isolate LC4256ZE
LC4256ZE-B-EVN Mouser 1: $26.23
of course, these should all work equally well
LCMXO2-7000HE-B-EVN Mouser 1: $26.23
as should this
FT2232H MINI MODULE Mouser 1: $27.00
& this
DLP-USB1232H FT2232H Mouser 1: $28.95
Yes, the Lattice boards with a FT2232H+CPLD, are cheaper than the FTDI/DLP boards, with just a FT2232H alone
I tried a UM232H, but the Atmel tools do not recognize the 1 channel FT232H, probably too new ?.
Comments
library ieee; use ieee.std_logic_1164.ALL; use ieee.numeric_std.ALL; library UNISIM; use UNISIM.Vcomponents.ALL; entity JC5 is port ( CLKi : in std_logic; Qc0 : in std_logic; Qc2 : in std_logic; Qc4 : in std_logic; Qc6 : in std_logic; SRn : in std_logic; John_D : out std_logic; Qc1 : out std_logic; Qc3 : out std_logic; Qc5 : out std_logic); end JC5; architecture BEHAVIORAL of JC5 is begin FIELD Qc = [Qc6..Qc0]; John_D = !(Qc2 # Qc1); /* NOR gives 2H 3L */ Qc.d = !SRn & 'b'0000000 # SRn & [Qc5..Qc0,John_D]; end BEHAVIORAL;I have tried this, but looks like i on the wrong way !
Attached is a very simple project example, for PLCC84 ATF1508ASV, and I used AtmelISP to create a SVF file.(does pgm/vfy)
( Load AtmeISP and tick [Write SVF file] )
Try feeding that SVF file into your JTAGWhisperer, to see what it does.
In theory, SVF is universal standard, and I would expect it to cough with the device ID check until you have ATF1508ASV connected ? ( ie it should load and run that far )
In the Project .PLD and .SI are the equation and Simulation source files, and .DOC and .SO are the Equation and Simulate outputs of pass1.
.FIT is the final fitter report, and .JED is the file loaded into AtmelISP, which is used to create .SVF
The most user-useful files for post-run reading are .SO and .FIT
Yes, the code I gave was for the Atmel WinCUPL tool flow, http://www.atmel.com/tools/WINCUPL.aspx
so it is not VHDL or Verilog, but a simpler Boolean Equation entry.
WInCUPL is fine for a few flipflops and gates (ie SPLD/CPLD designs), but I would not use it for a SoftCPU design.
The compiler is small to download, and very fast to compile, just like any assembler.
Next i put in the logic in VHDL.
It look like this:
The Atmel fitter has an option to create Verilog or VHDL output files, which are flat and verbose, but do have a framework for downstream simulation tests. I've updated the zip file above, to include those report files.
Did you try the SVF file ?
A first step is to just feed it into your SVF player setup.
With no device connected, it should give a Device ID / not found message, but making it that far is a useful test of file compatibility.
A worse possible outcome is something like 'unrecognized SVF file' and no JTAG activity at all.
http://dangerousprototypes.com/2012/02/01/jtagwhisperer-an-arduino-jtag-programing-library/
http://dangerousprototypes.com/docs/JTAG_SVF_to_XSVF_file_converter
But in future i purchase this:
http://www.ebay.co.uk/itm/NEU-Xilinx-Plattform-Kabel-USB-Blaster-Downloaden-JTAG-Programmer-Platform-Cable/320854520606?_trksid=p2045573.m2042&_trkparms=aid%3D111000%26algo%3DREC.CURRENT%26ao%3D1%26asc%3D27%26meid%3D8082839998051485972%26pid%3D100033%26prg%3D1011%26rk%3D1%26sd%3D320854520606%26#ht_6197wt_1106
It converts the file but gives a error message: Delay must be in terms of TCK count
Hmm... I see the AtmelISP has two choices and one says something about TCK, so I've added both SVF format choices as _C and _D to the Zip file above. Might be that rev C is needed ?
Through the use of CPLD's or equal ?
Sounds good, be interesting to see how the JTAG player works on that.
Sure that is what the VGA display is, effectively one port reads, and one writes, in a ping pong fashion.
In a display, the read-bandwidth dominates, and writes have to fit into what is left over.
What is the price differential between dualport ram vs sdram?
A datasheet: http://pdfdata.datasheetsite.com/pdf1/IDT/IDT70V28L20PFI.pdf
I think great !
Dualport ram has 2 addressports and 2 dataports !
It's possible to read and write at the same time, in 2 different memory banks i think !
One idea is to use 2 SDRAM with the same size.
Picture data writing into the first one and in the same time data sending from the second into the videodac.
When the picture is ready writen into the first one then function changement of the two sdrams.
The fps depends on the writing speed into the sdram.
The picture can be shown as long the picture data writing isn't finished !
1 times, 2 times or 3 times !
Not to forget, the P8X32A has 8 cogs to menage different things at the same time !
I also found this mention on the 'net, which suggests this pathway does work ?
ATF15xx Programmer
For programming atmel cplds you can create a SVF file with ATMISP.exe. For more information have a look at this documentation (http://www.atmel.com/dyn/resources/prod_documents/DOC1936.PDF)
Afterwards convert the created SVF file into a XSVF file: use impact or svf2xsvf (both from xilinx).
Program the ATF15xx with the integrated XSVF-Player.
They forget to mention to use SVF export revision C, but it sounds like svf2xsvf is OK with Atmel created SVF files.
I'm really stuck with the Xilinx IDE. You said
I'm not even sure what I have is the right program. I downloaded this huge program and there is just one icon on the screen called "Xilinx SDK 2013.1" Run this and if I go into Help/About it says it is
But at the top of the screen on the menu bar it says it is "C/C++ -Xilinx SDK".
Where is the ISE project navigator?
The problem wit the Xilinx SW is that you get all of the high end chips support and if you are lucky the low end stuff too. I am trying to remember if ther was a CPLD only SW from the old days, that is still available.
For 95XXX chips the 7.x - l2.x worked for me but I see that there is a Vivado (something like that anyway) that give pretty crocus pictures, but possibly not old CPLD support.
http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/design-tools.html
This four files: All Platforms - Split Installer Base Image - File 1/4, Install Data A, B and C
After the installation you can found the Project Navigator here:
Xilinx Design Tools/ISE Design Suite 14.5/ISE Design Tools
Looking at altera vs xilinx, I found an article somewhere that pointed out the CPLD chips are almost identical. So it the chips are similar, then maybe it comes down to the software. I can't find anything on the internet that looks like the screen I have. I have a theory that maybe it is because I am using Windows 8 and win8 doesn't have the start button (news flash - they are putting it back in the next version), so you get one shortcut on the desktop (sometimes) and sometimes you get another shortcut on the bottom toolbar, and sometimes on the touchscreen swipe menu. But what you don't get is the familiar start button where you would scroll to Xilinx and then run the programs in the Xilinx group. So my theory is there are other programs besides the "SDK", ie another one maybe called "ISE" but I can't find that one.
I've sent several hours on this now, endlessly searching the internet and Google Images, trying to find something like the 6.2Gb Xilinx SDK C/C++ editor that I seem to have been given.
But enough ranting!!
I shall thumb my nose at Xilinx by going on ebay and purchasing a product from their competitor - an Altera Cyclone II EP2C5T144 FPGA Board + Altera USB Blaster JTAG programmer for $43.90 and Free Shipping.
I am now downloading Altera's software. Hah - 2Gb smaller than Xilinx's.
Actually, I was heading to a FPGA anyway. CPLD's are great for replacing glue chips, but for a VGA design like this, with memory, the 44 pin ones may not have enough pins for things I want to experiment with (also experiments with touchscreens). Move up to the 84 pin ones, and the chips are twice the price. Add in the PLCC socket, and the jtag programming, and the fact Eagle doesn't seem to have library parts for the XC95 series with the higher pin counts, and it starts to add up. For not much more, FPGA has far more pins, has cores for almost everything you want (including SDRAM drivers and VGA drivers), and heck, why not throw in a Z80 core as well?
As an aside,run that Altera part number "EP2C5T144" past Google, and result #1 is from Leon, and result #3 is a discussion on, you guessed it, the Propeller forum (from a post by Leon from back in 2011).
I wonder where all that discussion went? There was some mighty clever boffinry going on there looking at hybridising the propeller and FPGA's.
Oh darn. He is right, of course.
Actually developing anything for an FPGA like that is a problem. As you saw the downloads are huge, not such a worry now that we have tera byte hard drives. Worse is the fact that they are really slow at compiling your VHDL/verilog into a chip configuration. I'm going to need a serious upgrade to my PC's before tackling that, I just don't have the patience to wait for it produce something that is loadable.
Ah, thanks. I was on this page http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools.html and it looks like I was supposed to be on this page http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/design-tools.html
I guess Xilinx designers know the difference between a "Vivado Design Suite" and a "ISE Design Suite".
But it is another 7.79Gb. Yikes!
@heater, I'm coming up to speed with the cyclone series. They come out every few years http://www.altera.com/devices/fpga/cyclone-about/cyc-about.html
and then some clever people go and make boards with useful things like sdram. And everything else http://www.ebay.com.au/itm/EP4CE10-ALTERA-FPGA-Cyclone-IV-Evaluation-Board-3-2-Touch-LCD-18-Modules-/261187836950?pt=LH_DefaultDomain_0&hash=item3cd0021c16
There have to be some cool synergies with fpga and the propeller...
But, before you purchase one it's a good idea to check the software you need to programm it.
When you want use the free version of the software then check the supported CPLD's and FPGA's !!!
After that you can purchase the board or/and purchase a higher license of the software if necessary !
WebPack License is Free but the lowest price license is the Logic Edition with $2995 !
I will try to recreate something like the XESS-100. It has the chicken-and-egg programming interface using a XC9572XL, and uses a parallel port, bless.
That makes good sense if going to a FPGA, but a middle step could be the Lattice MachXO2
see
http://www.latticesemi.com/products/developmenthardware/developmentkits/machxo2breakoutboard.cfm
1: $26.23
This has RAM, and has many choices in 100pins, plus a 32 pin QFN for those 'little tasks', using the same tools.
It also needs no other Loader chips.
Added: See next post, this Board should also pgm the Atmel ISP CPLDs, as I have just done so using a closely USB related LC4256ZE-B-EVN
["But it is another 7.79Gb. Yikes!"]
Lattice Diamond flows are ~ 2GB, from a glance at my directory.
That looks relatively expensive,
Still interested in how the JTAGwhisperer works on Atmel converted SVF - but I have also found a cleaner pathway.
The Atmel ATDH1150USB is not easy to find, but it uses FT2232 device, and I have FT2232H here, so I figured that was worth a try...
Using AtmelISP set for USB & ATDH1150USB, it works great with ATF1508AS, ATF1502ASL, ATF1502ASV which were what I had handy. Verify, and Pgm/.Verify all worked. No SVF dance needed, and a standard FT2232H part works.
I actually used this, as it has a FT2232H mounted, and has a 8 way header for JTAG, Needed 2 cuts to isolate LC4256ZE
LC4256ZE-B-EVN Mouser 1: $26.23
of course, these should all work equally well
LCMXO2-7000HE-B-EVN Mouser 1: $26.23
as should this
FT2232H MINI MODULE Mouser 1: $27.00
& this
DLP-USB1232H FT2232H Mouser 1: $28.95
Yes, the Lattice boards with a FT2232H+CPLD, are cheaper than the FTDI/DLP boards, with just a FT2232H alone
I tried a UM232H, but the Atmel tools do not recognize the 1 channel FT232H, probably too new ?.