Looks fun! I'm sure there are SDRAM drivers out there written in verilog but it is a good mental challenge to think about what such a driver would look like. Loadable counters, ram on external pins, buffers, logic glue.
I'm looking forward to the board arriving. I know people say the compilation can take a while, but right now if I draw some logic gates on Eagle and get a board made, it can be 3 - 4 weeks before it is tested. This has got to be quicker!
Hmm - maybe define a simple 8 bit bus to the propeller - 8 data and 4 control bits and we can pump display data from a bitmap file out the data bus and into the fpga or cpld. We could do a lot with one cpld/fpga and a sdram and a propeller, plus the minimum resistors for the VGA.
What?
Draw as a schematic!!!
How long has this been available?
All the beolean stuff made my head spin (especially large layouts), but schematics I CAN do.
I really must look into this - if I can draw a schematic, allocate pins, program silicon, erase try again... this is marvellous.
Is it hugely expensive?
Am I missing something as this looks too good to be true?
Dave
What?
Draw as a schematic!!!
How long has this been available?
Just keep in mind that Schematics are not portable across Lattice/Xilinx/Altera/Cypress, whilst HDLs are.
Comments, conditional compiles, and test results summaries are also harder to add via Schematics.
( I think Cypress PSoC flows are still only Verilog, so for uC users ? that may make Verilog a more portable choice )
What?
Draw as a schematic!!!
How long has this been available?
All the beolean stuff made my head spin (especially large layouts), but schematics I CAN do.
I really must look into this - if I can draw a schematic, allocate pins, program silicon, erase try again... this is marvellous.
Is it hugely expensive?
Am I missing something as this looks too good to be true?
Dave
Well I just tested it out and it works! See the screen shot.
The last few comments are valid and one gets the vibe reading fpga forum posts that the "proper" way to do this is a text language rather than a schematic.
The software gives you both, and for a schematic person like me, that is just perfect.
Downloaded the Altera Quartus software. Took about two hours. Downloaded software to unzip a .tar file. Unzipped it - took about 15 mins. Installed it - took about 15 mins. Ran the program and created a new project. Then followed the tutorial in post #186.
One little catch - if you follow the tutorial you would create a "new project". But if you start up Quartus and run the new project wizard then the new project is already there but no schematic editor as yet as it doesn't know if you want verilog or schematic. Go to File/New and the fourth entry down is 'Block Design/Schematic' and that becomes a schematic within the new project. Then the schematic screen comes up.
Drawing is fairly intuitive. Grab gates, place them, and connect with wires.
Then Processing/Start Compilation just to see how long it takes - about 30 secs, which is way faster than waiting 3 weeks for a PCB.
I wanted to see what the verilog code looked like, and a forum post somewhere helped me with that - it is File/Create Update/Create HDL design file from current file, and then up comes a menu asking whether it is vhdl or verilog. These are text files so you can use notepad or whatever to cut and paste. The screenshot shows notepad with the generated verilog file.
If not anything else, it makes learning verilog/vhdl easier as you can try out circuits in the schematic and see what they look like in text.
I think it can create 'blocks'. I'm hoping that means I can put some gates in a box, and then call my box something else, like 'MyCPU', and then use that as a design element. Addit: thanks to Google "verilog code to block schematic convert question" You can create a "Symbol File" (with your verilog file open click File->Create/Symbol File) associated to your verilog module, so you can use it as a block in your block schematic file.
I love the idea of being able to add a clock to the testbench and test it all works first.
Can't wait for the Cyclone II board to arrive. Cost is $43.70 so far for the board/jtag programmer and the software is free. I'll need some headers to connect to propeller boards but overall this is not a very expensive exercise.
Addit: Something we may need for this project - an SDRAM/FPGA interface that behaves like an 'old school' ram with address/data/rd/wr/cs like this project http://www.delorie.com/electronics/sdram/
Noooo...is this the end of an era? No more TTL boards from Dr_Acula.
FPGA's are great, only all the smaller models that might actually be soldered to boards by humans or used in sockets seem to be obsolete.
I guess the thing about schematic vs HDL is that for larger more complex designs it's much easier to work with some VHDL source code than it is with huge schematics. Perhaps VHDL/Verilog is a lot more portable accross different devices from different manufacturers than the schematics.
Thanks for that post Dr_Acula, this is where I wish there was a 'cheers' button for individual posts.. this should push me enough to finally get my Cyclone II board out of the drawer, shake off the dust and do something with it.
about 30 secs, which is way faster than waiting 3 weeks for a PCB.
I've got some ideas for interfacing with propeller boards using a range of different sized headers and some custom adapter boards. I'll fire up eagle tomorrow night and post some screen shots. There are still lots of things the propeller does better, eg SD cards, I2C bus, keyboard, mouse, simple TV display.
@Dr_Acula
Gosh you don't hang about.
This is really interesting - exciting even!
You have given me a lot to think about.
You even have a soldering solution.
Thanks a lot for taking the time and sharing this, and please keep us updated with your progress.
mmm guess I have a huge download to face - I hope I get the right one first time.
Dave
I've been checking out the Opencores site http://opencores.org/projects as I think there could be some work already done.
The memory section includes SDRAM drivers. It might give us some ideas.
The display section has VGA drivers.
There are also some other goodies, eg hardware jpeg decompression. This is something that is beyond the prop I, but one could think of using a fpga as a co-processor for the propeller, load the .jpg file off the sd card and into prop memory, then through a bus to the fpga and then read back the decompressed file.
To download the files you need to register with opencores and I think they manually check the registrations as it took a few hours for the approval email to come back.
@heater, I momentarily got distracted by the Z80 cores...
The FST3257 2-to-1 BUS SWITCH seams to be a very usefull part.
It can switch between two different bus.
It can switch the communication between the mcu and two 2 SDRAM's and the communication between two SDRAM's and the ADV7123.
The idea behind the simple schematic above is the following.
One cog of the P8X32A creates the picture in the first SDRAM and a other cog controlls the data flow from the second SDRAM to the ADV7123.
There is a PictureReady and a DrawingReady flag.
When the picture is created then the PictureReady flag is set to TRUE.
The second cog shows the picture as long as the PictureReady flag is set to FALSE. 1,2,3 ... times.
When the first cog has created the picture then he waits for the DrawingReady flag is set to TRUE.
The second cog checks after every showed picture if the PictureReady flag is it set to TRUE, if so then he sets the DrawingReady flag to TRUE too.
When both flags are TRUE then is time for the SDRAM changement trough the BUS SWITCHES and both flags are set to FALSE.
Any chance that this concept works ? Or must i use two P8X32A to handle this ?
But wait! Pick one of the big fpga chips and you have so many pins, you can connect *two* sdram chips separately to fpga. Then you can do your bus switching inside the fpga, with a simulated logic chip.
The hardware gets simpler. One propeller. One fpga chip. Two ram chips.
Hey, check this out. Inside the Quartus software is the 74xx library. It is in "others/maxplus2"
There are 2 to 1 multiplexers. For the job you want to do above, the virtual 74157 chip can route the signals. (real datasheet is here http://www.futurlec.com/74HC/74HC157.shtml)
If we can put as much as possible in the fpga, it means we can brainstorm ideas much faster than actually building them on a breadboard.
My version of the DracBlade TTL bits was only the equivalent 74374s and 74138s drawn as schematics and poked into a XC9532 for the simple 64Kb one, or a XC9572 for the full 512Kb memory and extra I/O ports. Even these were pin count exercises rather than the actual silicon % used. The ISE programs got more and more in the libraries from v7.x thru to 12.x but the later ones are just so huge!
I am rather taken by that Lattice board, £18 might just get under the radar ;-)
@Dr_Acula
Lattice?
Zilinx?
Your picture shows - quartus software under altera directory
Your link is to MAX11 EPM240 - is this the same as MachXO2?
In simple terms - what have you ordered, (links) and where can the software you showed an example output from be acquired?
I found the software you downloaded by mistake, and the correct one you may or may not have used, but now I am confused.
I'm afraid my simple brain is showing overload with so many names.
I'd like to be able to keep up with what you are doing and at some stage jump in and have a go, but not until I see how you progress....
Thanks
Dave
Every company has its own jargon. CPLD means cheaper, less elements, to some extent less pins. FPGA means more pins, more elements, more expensive. Altera's software is called Quartus.
Xilinx, Altera and Lattice are the three big manufacturers. Not sure which is best. Maybe it does not matter?
I had some trouble with xilinx software but looking back, I think it might be a Windows8 problem. I don't know if xilinx has a 74xx library - they may well do.
For Altera, their CPLDs are the "MAX" series and their FPGAs are the "CYCLONE" series.
Every few years they seem to come out with a new one. The older ones get cheaper and I think the older FPGAs are now almost cheaper than the CPLDs.
The Altera software lets you program the new and the old chips. So whatever circuit you design can be sent to a wide range of boards.
I'm not sure the chips are solderable by mere mortals, so that means a board rather than a chip. In any case, you need to program the chip, so you need a jtag header, and a DC socket for power, and a regulator, and by the time you get all that, a board probably works out cheaper.
I'm working backwards now - get on ebay, ignore the chips, and try to find the cheapest boards out there.
My little problem now - all of the boards out there seem to have their own proprietary header. Some put the 3V and 5V power at the ends, some have ground pins in the middle, some have ground at the other end etc. There is no standard, so I am going to think about some little adapter boards to adapt to my standard (which no one else uses, I have 3V and 5V at one end of the header, 12V and Gnd at the other end, and signal pins in between, and any size header is allowed).
Comments
Nice link - reading the specs now.
Also time to learn a new language - verilog eg http://www.asic-world.com/verilog/veritut.html
Looks fun! I'm sure there are SDRAM drivers out there written in verilog but it is a good mental challenge to think about what such a driver would look like. Loadable counters, ram on external pins, buffers, logic glue.
http://esd.cs.ucr.edu/labs/tutorial/
And I presume that once you learn Verilog or VHDL, it can be used for both CPLD and FPGA?
I'm looking forward to the board arriving. I know people say the compilation can take a while, but right now if I draw some logic gates on Eagle and get a board made, it can be 3 - 4 weeks before it is tested. This has got to be quicker!
Hmm - maybe define a simple 8 bit bus to the propeller - 8 data and 4 control bits and we can pump display data from a bitmap file out the data bus and into the fpga or cpld. We could do a lot with one cpld/fpga and a sdram and a propeller, plus the minimum resistors for the VGA.
Draw as a schematic!!!
How long has this been available?
All the beolean stuff made my head spin (especially large layouts), but schematics I CAN do.
I really must look into this - if I can draw a schematic, allocate pins, program silicon, erase try again... this is marvellous.
Is it hugely expensive?
Am I missing something as this looks too good to be true?
Dave
It's like the programming with Delphi.
Look at post #177.
Just keep in mind that Schematics are not portable across Lattice/Xilinx/Altera/Cypress, whilst HDLs are.
Comments, conditional compiles, and test results summaries are also harder to add via Schematics.
( I think Cypress PSoC flows are still only Verilog, so for uC users ? that may make Verilog a more portable choice )
Could be worth trying, but if you have to modify the Schematic in Xilinx, and run two tools, that's not quite 'portable'.
It says this:
--Purpose:
-- This vhdl netlist is translated from an ECS schematic. It can be
-- synthesized and simulated, but it should not be modified.
Well I just tested it out and it works! See the screen shot.
The last few comments are valid and one gets the vibe reading fpga forum posts that the "proper" way to do this is a text language rather than a schematic.
The software gives you both, and for a schematic person like me, that is just perfect.
Downloaded the Altera Quartus software. Took about two hours. Downloaded software to unzip a .tar file. Unzipped it - took about 15 mins. Installed it - took about 15 mins. Ran the program and created a new project. Then followed the tutorial in post #186.
One little catch - if you follow the tutorial you would create a "new project". But if you start up Quartus and run the new project wizard then the new project is already there but no schematic editor as yet as it doesn't know if you want verilog or schematic. Go to File/New and the fourth entry down is 'Block Design/Schematic' and that becomes a schematic within the new project. Then the schematic screen comes up.
Drawing is fairly intuitive. Grab gates, place them, and connect with wires.
Then Processing/Start Compilation just to see how long it takes - about 30 secs, which is way faster than waiting 3 weeks for a PCB.
I wanted to see what the verilog code looked like, and a forum post somewhere helped me with that - it is File/Create Update/Create HDL design file from current file, and then up comes a menu asking whether it is vhdl or verilog. These are text files so you can use notepad or whatever to cut and paste. The screenshot shows notepad with the generated verilog file.
If not anything else, it makes learning verilog/vhdl easier as you can try out circuits in the schematic and see what they look like in text.
I think it can create 'blocks'. I'm hoping that means I can put some gates in a box, and then call my box something else, like 'MyCPU', and then use that as a design element. Addit: thanks to Google "verilog code to block schematic convert question" You can create a "Symbol File" (with your verilog file open click File->Create/Symbol File) associated to your verilog module, so you can use it as a block in your block schematic file.
Some clever boffins on the interwebs have taken the 74xx library and made verilog code eg http://code.google.com/p/tanukifu/source/browse/trunk/FPGA/7400/?r=10 so that makes importing existing schematics a lot easier.
I love the idea of being able to add a clock to the testbench and test it all works first.
Can't wait for the Cyclone II board to arrive. Cost is $43.70 so far for the board/jtag programmer and the software is free. I'll need some headers to connect to propeller boards but overall this is not a very expensive exercise.
Addit: Something we may need for this project - an SDRAM/FPGA interface that behaves like an 'old school' ram with address/data/rd/wr/cs like this project http://www.delorie.com/electronics/sdram/
My drawers of TTL chips seem kind of obsolete...
FPGA's are great, only all the smaller models that might actually be soldered to boards by humans or used in sockets seem to be obsolete.
I guess the thing about schematic vs HDL is that for larger more complex designs it's much easier to work with some VHDL source code than it is with huge schematics. Perhaps VHDL/Verilog is a lot more portable accross different devices from different manufacturers than the schematics.
It sounds somewhat faster, yes..
-Tor
I won't be soldering any of those chips either. There are some very kind people in China who seem keen to solder the cpld/fpga chips to PCBs and bring all the pins out to standard 0.1" headers, and so those are the ones I'll be buying
I've got some ideas for interfacing with propeller boards using a range of different sized headers and some custom adapter boards. I'll fire up eagle tomorrow night and post some screen shots. There are still lots of things the propeller does better, eg SD cards, I2C bus, keyboard, mouse, simple TV display.
The old unchanged and the updated schematic files.
Silverado_3_alpha has now added 2 X FST3257 2-to-1 BUS SWITCHES, 2 X 74HC573 are removed.
The schematic files are designed with the Xilinx Design Suite 14.5 for the XC9500XL CPLD family.
Gosh you don't hang about.
This is really interesting - exciting even!
You have given me a lot to think about.
You even have a soldering solution.
Thanks a lot for taking the time and sharing this, and please keep us updated with your progress.
mmm guess I have a huge download to face - I hope I get the right one first time.
Dave
http://shop.ztex.de/product_info.php?products_id=60&language=en
http://shop.ztex.de/product_info.php?cPath=21&products_id=30
http://shop.ztex.de/product_info.php?cPath=21&products_id=65
This year CPLD and next year FPGA.
The memory section includes SDRAM drivers. It might give us some ideas.
The display section has VGA drivers.
There are also some other goodies, eg hardware jpeg decompression. This is something that is beyond the prop I, but one could think of using a fpga as a co-processor for the propeller, load the .jpg file off the sd card and into prop memory, then through a bus to the fpga and then read back the decompressed file.
To download the files you need to register with opencores and I think they manually check the registrations as it took a few hours for the approval email to come back.
@heater, I momentarily got distracted by the Z80 cores...
It can switch between two different bus.
It can switch the communication between the mcu and two 2 SDRAM's and the communication between two SDRAM's and the ADV7123.
One cog of the P8X32A creates the picture in the first SDRAM and a other cog controlls the data flow from the second SDRAM to the ADV7123.
There is a PictureReady and a DrawingReady flag.
When the picture is created then the PictureReady flag is set to TRUE.
The second cog shows the picture as long as the PictureReady flag is set to FALSE. 1,2,3 ... times.
When the first cog has created the picture then he waits for the DrawingReady flag is set to TRUE.
The second cog checks after every showed picture if the PictureReady flag is it set to TRUE, if so then he sets the DrawingReady flag to TRUE too.
When both flags are TRUE then is time for the SDRAM changement trough the BUS SWITCHES and both flags are set to FALSE.
Any chance that this concept works ? Or must i use two P8X32A to handle this ?
But wait! Pick one of the big fpga chips and you have so many pins, you can connect *two* sdram chips separately to fpga. Then you can do your bus switching inside the fpga, with a simulated logic chip.
The hardware gets simpler. One propeller. One fpga chip. Two ram chips.
Hey, check this out. Inside the Quartus software is the 74xx library. It is in "others/maxplus2"
There are 2 to 1 multiplexers. For the job you want to do above, the virtual 74157 chip can route the signals. (real datasheet is here http://www.futurlec.com/74HC/74HC157.shtml)
If we can put as much as possible in the fpga, it means we can brainstorm ideas much faster than actually building them on a breadboard.
It has the same function as the BUS SWITCH.
I am rather taken by that Lattice board, £18 might just get under the radar ;-)
The Lattice Diamond flows I think also support Schematic entry, for those keen on this.
- google finds links like this http://www.latticesemi.com/support/faqs/details.cfm?id=2187
Lattice?
Zilinx?
Your picture shows - quartus software under altera directory
Your link is to MAX11 EPM240 - is this the same as MachXO2?
In simple terms - what have you ordered, (links) and where can the software you showed an example output from be acquired?
I found the software you downloaded by mistake, and the correct one you may or may not have used, but now I am confused.
I'm afraid my simple brain is showing overload with so many names.
I'd like to be able to keep up with what you are doing and at some stage jump in and have a go, but not until I see how you progress....
Thanks
Dave
Sorry, I'm racing ahead. Still working it out myself.
I'm using Altera software http://www.altera.com/products/software/quartus-ii/web-edition/qts-we-index.html which is free. Xilinx software is as well.
Every company has its own jargon. CPLD means cheaper, less elements, to some extent less pins. FPGA means more pins, more elements, more expensive. Altera's software is called Quartus.
Xilinx, Altera and Lattice are the three big manufacturers. Not sure which is best. Maybe it does not matter?
I had some trouble with xilinx software but looking back, I think it might be a Windows8 problem. I don't know if xilinx has a 74xx library - they may well do.
For Altera, their CPLDs are the "MAX" series and their FPGAs are the "CYCLONE" series.
Every few years they seem to come out with a new one. The older ones get cheaper and I think the older FPGAs are now almost cheaper than the CPLDs.
The Altera software lets you program the new and the old chips. So whatever circuit you design can be sent to a wide range of boards.
I'm not sure the chips are solderable by mere mortals, so that means a board rather than a chip. In any case, you need to program the chip, so you need a jtag header, and a DC socket for power, and a regulator, and by the time you get all that, a board probably works out cheaper.
I'm working backwards now - get on ebay, ignore the chips, and try to find the cheapest boards out there.
Search for cpld and things like this come up $11 http://www.ebay.com.au/itm/New-MAX-II-EPM240-CPLD-Development-Board-Minimum-System-/160772787179?pt=AU_B_I_Electrical_Test_Equipment&hash=item256ece0beb
And search for fpga and you can get this $19 http://www.ebay.com/itm/ALTERA-Cyclone-FPGA-Development-Board-JTAG-AS-SPI-Flash-EP1C3-Quartus-II-CPLD-/230960685109?pt=LH_DefaultDomain_0&hash=item35c6546035
Both of these chips can be selected from the Quartus software, so the same schematic could be sent to both boards.
Both have a similar number of pins. One is nearly twice the price of the other, but I think can fit a lot more than twice the number of elements.
Going off on a tangent, take a look at this board $23 http://www.ebay.com.au/itm/Altera-Cyclone-II-FPGA-EP2C5T144-Mini-Development-Learn-Core-Board-E081-/261095727391?pt=LH_DefaultDomain_0&hash=item3cca84a11f and scroll down about half way down, there are some addon boards - one looks like sdram and one looks like VGA. I can't seem to find those addon boards, but if they are cheap, it could make this whole project a lot easier for hardware. Just then need to think about a link to the propeller (which could be as simple as a 4 pin SPI).
My little problem now - all of the boards out there seem to have their own proprietary header. Some put the 3V and 5V power at the ends, some have ground pins in the middle, some have ground at the other end etc. There is no standard, so I am going to think about some little adapter boards to adapt to my standard (which no one else uses, I have 3V and 5V at one end of the header, 12V and Gnd at the other end, and signal pins in between, and any size header is allowed).
This board $21 http://www.ebay.com.au/itm/Altera-CycloneII-EP2C5T144-FPGA-Mini-Development-Board-/150835820710?pt=LH_DefaultDomain_0&hash=item231e83f8a6 includes a link to a schematic.
Then select the last categorie named 'TTL'.
The XC6SLX9 FPGA has integrated 2 SDRAM Controller, they can be programmed through ISE.
http://wiki.ztex.de/doku.php?id=en:ztex_boards:ztex_fpga_boards:memory_tutorial_1_11
PixelCounter counts the pixel of one horizontal row and the LineCounter counts the horizontal lines.