The CD4017 is a johnson decade counter, works this too ?
The CD4017 would be too slow, and whilst it has a HCMOS version, there are no fast 3.3V variants.
As the 174 is already on the BOM, why not just use that ?
Is it possible to drive a P8X32A with only have a clock signal on XI (6.29375MHz) ?
Yes, that gives the /4 and 100.7MHz operation (over clocked) - many report Prop operating fine at 100MHz, and if you ensure the Vcc is tightly regulated that has less risk. (and keep it cool... )
I'd suggest test first at /5, and certainly have /4 as an option
Parallel i'am planing the Silverado Version with CPLD's as SDRAM Controller
This is the schematic for the thirst CPLD, she controls the addressbus and the controllines.
The target device is a Xilinx XC9536XL-10PC44.
The schematic was used as top module for the CPLD programming.
Updated Silverado_2_alpha.pdf, now with Johnson Counter (U31).
You might want to check the Johnson wiring ? : with a MR to ensure no illegal states, usually you just make a ring with a single inverter for even divides, or if you want to /5, a NOR gate option.
I think i have done the Johnson Counter in this way (Frequency Division): http://osp.mans.edu.eg/cs212/FF_Applications.htm
Frequency in = 25.175MHz, after first flip-flop = 12.5875MHz = after second flip-flop = 6.29375MHz
I can connect MR with 3,3V if it isn't needed !
Yes the XC2C64A is supported !
Why is the XC2C64A a better solution as the XC9572XL-7PC44 ?
Yes the XC2C64A is supported !
Why is the XC2C64A a better solution as the XC9572XL-7PC44 ?
The 174 has a common clock, and usually a Johnson or ring counter, is a shift-register, with an inverter, or NOR feedback.
The XC2C64A is lower power, and cheaper, but one minor drawback, is it does need a 1.8V core supply (low current) I/Os are 3.3v.
Also check out the Lattice MachXO2 - more logic again, my main peeve with the XO2, is the lack of middle ground packages.
They have one part in QFN32, which can fit a good amount, provided you need only 21io, and then they leap to TQFP100.?!
(BGA parts are not easy to handle in moderate volumes or on 2 layer PCBs)
They should do 44/48 pin gull wing variants to allow retrofit of CPLD footprints - clearly the die can fit.
I suspect some turf-war inside Lattice is the reason for this silliness.
Adding : To give a feel for what fits in the QFN32, MachXO2, here are some tests I did for Multiple Quadrature counters :
// Design is 4 Quad counters and a single Muxed CW:0 SPI Capture/Shifter
// can vary the Counter+Shifter width, (CW) to fit into a 32 pin MachXO2-256
//
// parameter CW = 23; // ZE is lower power, slower variant, HC is 3.3V
// in XO2-256 SLICE 97/128 75% used Max : LCMXO2-256ZE : 77.730MHz
// parameter CW = 27;
// in XO2-256 SLICE 111/128 86% used MAX : LCMXO2-256HC 141.044MHz
// parameter CW = 29;
// in XO2-256 SLICE 118/128 92% used MAX : LCMXO2-256HC 133.815MHz
parameter CW = 31;
// in XO2-256-tqfp100 SLICE 125/128 97% used MAX : LCMXO2-256HC 138.947MHz
// in QFN32 SLICE 125/128 97% used MAX : LCMXO2-256HC 133.316MHz
// Slight change in MHz with package, perhaps more constrained routing ?
But that is a smaller ram chip and I think there are good reasons why the large SDRAM's are going to be better.
Re PLCC sockets - I like these too. And with sockets you can plug chips in and out and are less likely to cook a chip when soldering.
Addit: I think there might be equivalent chips that can be soldered that have more pins eg XC9572XLVQ64-7C. If there are not enough pins on the 44 pin version. And futurlec sell a PLCC 84 pin one for $6.90. The XC9572XL seems a very flexible choice.
(and they do have a QFN32 LCMXO2-256HC-4SG32C 256 LUTS, 22 I/O, 3.3V 1: $2.80 )
( & you can get going with LCMXO2-7000HE-B-EVN MACHXO2-7000HE BREAKOUT BOARD 1: $26.23)
and those cover a wide range of choices. The 640 and up, include Block rams, so can start to buffer writes.
Even the -256 would be able to manage the Pixel Start command in hardware,and it could also do the Line and Frame....
For absolute price tho, it is hard to beat LV174's ~20c/100+
PLCCs are great for being able to reuse the chips for many other things, after the present project is "yesterday's". They also give the wonderful feature of through hole 0.1" mounting so that home made PCBs are easier, but ...
They are so big, physically, and yet restrict the pin count. I have a couple of old PCBs that I will lever off some of the CPLDs, this time they are all Altera types (still obsolete stuff, Flex and Max, as is usual for me) and SM. I can do down to 0.5mm PCBs but 0.4mm isn't pretty, and that is to be Prop2 pitch :-(
I agree - something like this http://www.hdl.co.jp/en/index.php/plcc68-series-menu.html which at first sight is a standard PLCC but it is actually a ball grid array chip, plus some support components like capacitors. The power of modern FPGA but with connections that mere mortals can actually solder.
I keep coming back to the old school PLCC xilinx chips. I know the datasheet says they are obsolete, but they do seem about the right mix of simplicity and cost for this sort of project.
Also - been downloading the xilinx software all day. It is a 6GB file. Hope it is worth much of my monthly download limit!
I keep coming back to the old school PLCC xilinx chips. I know the datasheet says they are obsolete, but they do seem about the right mix of simplicity and cost for this sort of project.
Also - been downloading the xilinx software all day. It is a 6GB file. Hope it is worth much of my monthly download limit!
If you like PLCC84, for one still with a (some? **) pulse, Newark show 395 pcs of stock of Atmel ATF1508ASV-15JU84 , at 1-9 : $3.42 (128 macrocells) and Digikey show 900.
The Atmel WinCUPL software is about a ~20MB download (and much faster than Xilinx to compile and fit)
** The ATF1508ASV-15JU84 seems to be a still valid part code, as those stock levels indicate.
Data sheet indicates ATF1508ASV-15JU84 (PLCC84) and TATF1508ASV-15AU100 (TQFP100)
I'm a bit miffed. Spent 5 hours downloading the xilinx package (6Gb), an hour installing it, it takes over a minute to start the program and comes up looking like a simple C/C++ text editor.
That should be a program that takes a few megabytes. Bloatware++ !
I'm not interested in C for this purpose. If I wanted to use C to program a chip, I'd have used a Propeller
Can this xilinx program draw schematics to program a XC9572 or have I got the wrong program?
ISE Design Suit 14.5:
1) Start ISE Project Navigator
2) Click on 'New Project'
Enter project name and destination path.
Select under 'Top Level Source Type': Schematic
Click on NEXT
3) Under Project Settings you can select the target device.
Select as Family 'XC9500XL CPLDs'.
Select as device 'XC9572XL'
Click on NEXT.
4) Click on FINISH.
5) 'Project/New Source'
Highlight 'Schematic'.
Enter schematic name.
Click on NEXT.
Click on FINISH.
6) Click on DESIGN.
In the moment i have problems to translate the code !
It is simple enough, just Boolean equations, very like assembler
FIELD allows groups of bits to be collected into a single name. Here Qc is now 7 bits wide.
Boolean operators are
! -> NOT
& -> AND
# -> OR
$ -> XOR
Suffixes are .CK, .D, OR, .T (& also .J .K ) ( self explanatory)
The line Qc.d = !SRn & 'b'0000000 # SRn & [Qc5..Qc0,John_D];
just says
When SRn is LOW, Sync load 0000000, else when Hi, create a Shift-Left-register, fed by Johnson_D term.
This code compiles in under 1 second.
I'll do a PLCC84 version, since that seems a active part.
Another advantage of text entry over schematics, is I can do this
Comments
Silverado_1.pdf is P8X32A_1 and Silverado_4.pdf P8X32A_3.
The CD4017 is a johnson decade counter, works this too ?
Any suggestions for a better power supply ?
As the 174 is already on the BOM, why not just use that ?
Yes, that gives the /4 and 100.7MHz operation (over clocked) - many report Prop operating fine at 100MHz, and if you ensure the Vcc is tightly regulated that has less risk. (and keep it cool... )
I'd suggest test first at /5, and certainly have /4 as an option
I put thermal grease and a aluminium heatsink on his top !
I have decide to use a LTC1147CS8-3.3 and a LTC1147CS8-5.
Two Step-Down Switching Regulators.
New designed power supply: Silverado_5.pdf
Updated Silverado_2_alpha.pdf, now with Johnson Counter (U31). P8X32A_2 clock speed 100.7MHz.
This is the schematic for the thirst CPLD, she controls the addressbus and the controllines.
The target device is a Xilinx XC9536XL-10PC44.
The schematic was used as top module for the CPLD programming.
You might want to check the Johnson wiring ? : with a MR to ensure no illegal states, usually you just make a ring with a single inverter for even divides, or if you want to /5, a NOR gate option.
The 9572XL is getting long in the tooth, and has high Icc ? - your Xilinx flows probably also support XC2C64A ?
( or Lattice LC4064V or LC4064Zx)
http://osp.mans.edu.eg/cs212/FF_Applications.htm
Frequency in = 25.175MHz, after first flip-flop = 12.5875MHz = after second flip-flop = 6.29375MHz
I can connect MR with 3,3V if it isn't needed !
Yes the XC2C64A is supported !
Why is the XC2C64A a better solution as the XC9572XL-7PC44 ?
Is my power supply design now better ?
The 174 has a common clock, and usually a Johnson or ring counter, is a shift-register, with an inverter, or NOR feedback.
The XC2C64A is lower power, and cheaper, but one minor drawback, is it does need a 1.8V core supply (low current) I/Os are 3.3v.
Also check out the Lattice MachXO2 - more logic again, my main peeve with the XO2, is the lack of middle ground packages.
They have one part in QFN32, which can fit a good amount, provided you need only 21io, and then they leap to TQFP100.?!
(BGA parts are not easy to handle in moderate volumes or on 2 layer PCBs)
They should do 44/48 pin gull wing variants to allow retrofit of CPLD footprints - clearly the die can fit.
I suspect some turf-war inside Lattice is the reason for this silliness.
Adding : To give a feel for what fits in the QFN32, MachXO2, here are some tests I did for Multiple Quadrature counters :
I can programm 3.3V and 5V CPLD's.
I fixed my comment a little : The XC2C64 core Vcc is 1.8v (sub 5mA), but the I/O and programming is 3.3v
The target device is a Xilinx XC9572XL-10PC44.
The schematic was used as top module for the CPLD programming.
http://uk.farnell.com/productimages/farnell/standard/42627954.jpg
Is the pin distance of this sockets the same like the dip sockets has ?
PLCC sockets are fine for CPLDs, and they have 0.1" pin pitch, if that was what you meant.
XC9572XL looks pretty good. $3.50 at futurlec in a PLCC.
I wonder if anyone has done this before?
Hmm - it appears they have http://propeller.wikispaces.com/Propeller_CPLD
But that is a smaller ram chip and I think there are good reasons why the large SDRAM's are going to be better.
Re PLCC sockets - I like these too. And with sockets you can plug chips in and out and are less likely to cook a chip when soldering.
Addit: I think there might be equivalent chips that can be soldered that have more pins eg XC9572XLVQ64-7C. If there are not enough pins on the 44 pin version. And futurlec sell a PLCC 84 pin one for $6.90. The XC9572XL seems a very flexible choice.
I think the PLCC84 are dinosaurs now...
The next logical step up from 44 pins, is probably to TQFP100, and then you can get the MachXO2 family
LCMXO2-256HC-4TG100C 256 LUTS 56 I/O 3.3V 1: $4.25
LCMXO2-640HC-4TG100C 640 LUTS, 79 I/O, 3.3V 1: $5.85
LCMXO2-1200HC-4TG100C 1280 LUTS 80 I/O 3.3V 1: $7.35
LCMXO2-2000HC-4TG100C 2112 LUTS, 80 I/O, 3.3V 1: $10.20
(and they do have a QFN32 LCMXO2-256HC-4SG32C 256 LUTS, 22 I/O, 3.3V 1: $2.80 )
( & you can get going with LCMXO2-7000HE-B-EVN MACHXO2-7000HE BREAKOUT BOARD 1: $26.23)
and those cover a wide range of choices. The 640 and up, include Block rams, so can start to buffer writes.
Even the -256 would be able to manage the Pixel Start command in hardware,and it could also do the Line and Frame....
For absolute price tho, it is hard to beat LV174's ~20c/100+
They are so big, physically, and yet restrict the pin count. I have a couple of old PCBs that I will lever off some of the CPLDs, this time they are all Altera types (still obsolete stuff, Flex and Max, as is usual for me) and SM. I can do down to 0.5mm PCBs but 0.4mm isn't pretty, and that is to be Prop2 pitch :-(
In a later stage they give me the possibilty to replace a lot of logic chips with one CPLD.
I keep coming back to the old school PLCC xilinx chips. I know the datasheet says they are obsolete, but they do seem about the right mix of simplicity and cost for this sort of project.
Also - been downloading the xilinx software all day. It is a 6GB file. Hope it is worth much of my monthly download limit!
If you like PLCC84, for one still with a (some? **) pulse, Newark show 395 pcs of stock of Atmel ATF1508ASV-15JU84 , at 1-9 : $3.42 (128 macrocells) and Digikey show 900.
The Atmel WinCUPL software is about a ~20MB download (and much faster than Xilinx to compile and fit)
** The ATF1508ASV-15JU84 seems to be a still valid part code, as those stock levels indicate.
Data sheet indicates ATF1508ASV-15JU84 (PLCC84) and TATF1508ASV-15AU100 (TQFP100)
Later, on the final pcb.
All datalines must have the same length, the same for the addresslines ?
I like the simplicity to programm the CPLD through a schematic drawing !
At 25MHz, you do not need to be too paranoid.
Schematics are not tools-portable, and need care to avoid extra logic getting into the mix from MSI Block use.
Boolean equation entry is quite readable, for this sort of work.
Here is a Generic Johnson Counter, set for /5 :
FIELD Qc = [Qc6..Qc0]; John_D = !(Qc2 # Qc1); /* NOR gives 2H 3L */ Qc.d = !SRn & 'b'0000000 # SRn & [Qc5..Qc0,John_D];and the Pin-map section, for a 16V8
Pin 13, 15, 17, 19 = output ?
FIELD Qc = [Qc6..Qc0];
John_D = !(Qc2 # Qc1); /* NOR gives 2H 3L */
Qc.d = !SRn & 'b'0000000 # SRn & [Qc5..Qc0,John_D];
In the moment i have problems to translate the code !
That should be a program that takes a few megabytes. Bloatware++ !
I'm not interested in C for this purpose. If I wanted to use C to program a chip, I'd have used a Propeller
Can this xilinx program draw schematics to program a XC9572 or have I got the wrong program?
1) Start ISE Project Navigator
2) Click on 'New Project'
Enter project name and destination path.
Select under 'Top Level Source Type': Schematic
Click on NEXT
3) Under Project Settings you can select the target device.
Select as Family 'XC9500XL CPLDs'.
Select as device 'XC9572XL'
Click on NEXT.
4) Click on FINISH.
5) 'Project/New Source'
Highlight 'Schematic'.
Enter schematic name.
Click on NEXT.
Click on FINISH.
6) Click on DESIGN.
Not sure where you pulled that from ?
It is simple enough, just Boolean equations, very like assembler
FIELD allows groups of bits to be collected into a single name. Here Qc is now 7 bits wide.
Boolean operators are
! -> NOT
& -> AND
# -> OR
$ -> XOR
Suffixes are .CK, .D, OR, .T (& also .J .K ) ( self explanatory)
The line Qc.d = !SRn & 'b'0000000 # SRn & [Qc5..Qc0,John_D];
just says
When SRn is LOW, Sync load 0000000, else when Hi, create a Shift-Left-register, fed by Johnson_D term.
This code compiles in under 1 second.
I'll do a PLCC84 version, since that seems a active part.
Another advantage of text entry over schematics, is I can do this
$IFDEF DivideBy5
John_D = !(Qc2 # Qc1); /* NOR gives 2H 3L */
$ENDIF
$IFDEF DivideBy6 /* gives 3H 3L */
John_D = !Qc2;
$ENDIF
From the 16V8 pin map section !
I meant the input/output groupings you gave, not in the original ??
Those are 16v8 pins, not some other device - in this case, they are all outputs.