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The unofficial P2 documentation project

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  • cgraceycgracey Posts: 14,151
    edited 2012-12-24 06:58
    ctwardell wrote: »
    I noticed that the multitasking section list REPS/REPD as NOT supporting multitasking, however the REPS/REPD section give a multitasking example.

    I see in the latest copy of Chip's txt file that REPS/REPD are no longer listed as not supporting multitasking, so I assume the example showing them supporting mutlitasking is correct and we can remove REPS/REPD from the list of excluded instructions for multitasking.

    Can Chip verify this?

    Thanks,

    C.W.


    In the last Verilog iteration, I made REPS and REPD work with multitasking by having it react only to the task that initiated it. The limitation is that only one task can use it at a time. One thing I overlooked, though, was making JMPTASK kill any REPS/REPD in progress for a task affected by JMPTASK. The remedy is to do a 'REPS #1,#1' before the JMPTASK. This will cause any REPS/REPD in progress to effectively cancel, as executing one instruction once will never causing a jump-back to occur.
  • jmgjmg Posts: 15,173
    edited 2012-12-24 16:34
    Are there notes yet on the Quadrature mode for Cog counters, and how they can capture external edges ?
  • TubularTubular Posts: 4,702
    edited 2012-12-26 17:15
    Peter,
    I'm back at work after a good break. Now, what needs doing?
    cheers
    Lachlan
  • BEEPBEEP Posts: 58
    edited 2012-12-27 12:40
    Prop2_Docs.txt to Prop2_Docs_Arial.pdf

    pdf is obsolete and removed.
  • David BetzDavid Betz Posts: 14,516
    edited 2012-12-27 12:44
    BEEP wrote: »
    Prop2_Docs.txt to Prop2_Docs_Arial.pdf
    Thanks for the PDF!
  • SeairthSeairth Posts: 2,474
    edited 2013-01-02 06:11
    Supposing the the following operation:

    ABS INDA, var

    The first two bits of the conditions field will be encoded as a modifier for the INDA field. What about the other two bits? Must they be %00 for non-INDx registers, or can they be any value?
  • cgraceycgracey Posts: 14,151
    edited 2013-01-02 09:40
    Seairth wrote: »
    Supposing the the following operation:

    ABS INDA, var

    The first two bits of the conditions field will be encoded as a modifier for the INDA field. What about the other two bits? Must they be %00 for non-INDx registers, or can they be any value?

    They will be ignored, so they can be any value. I changed my doc's to state that. Thanks for asking about this.
  • Peter JakackiPeter Jakacki Posts: 10,193
    edited 2013-01-03 01:21
    Tubular wrote: »
    Peter,
    I'm back at work after a good break. Now, what needs doing?
    cheers
    Lachlan
    I'm kinda back at work again but still need a good break! At the moment we need to take stock of what everyone is doing as everybody seems to be doing their own bits and pieces (I think). This makes it more work to integrate into the online live document but maybe we could add links in the document to these other documents so that bit by bit we can get all this information together in the one place. The assembler reference section has been broken off into it's own document which is being taken care of by Seairth.

    Maybe all those who know of changes required to the Google docs can post and let us know.
  • SeairthSeairth Posts: 2,474
    edited 2013-01-03 04:19
    If I recall correctly, some of the instructions can implicitly make use of the value currently latched in the ALU (e.g. as a timeout for WAITPNE). Since I am unfamiliar with the internal hardware, which instructions modify the ALU value? And is the value latched by the ALU regardless of effects flags?
  • cgraceycgracey Posts: 14,151
    edited 2013-01-03 16:38
    I've added a section on branch instructions, which is not done yet, though all the non-obvious stuff is now documented:

    Prop2_Docs.txt
    txt
    txt
    Prop2_Docs.txt
    65K
  • SapiehaSapieha Posts: 2,964
    edited 2013-01-03 16:57
    Hi Chip

    Thanks

    Incorporated in my PDF

    cgracey wrote: »
    I've added a section on branch instructions, which is not done yet, though all the non-obvious stuff is now documented:

    Prop2_Docs.txt
  • SapiehaSapieha Posts: 2,964
    edited 2013-01-03 17:08
    Hi Chip.

    I see one new instruction that we don't have its BIT pattern.

    TASKSW, TASKSWD
  • cgraceycgracey Posts: 14,151
    edited 2013-01-03 17:10
    Sapieha wrote: »
    Hi Chip.

    I see one new instruction that we don't have its BIT pattern.

    TASKSW, TASKSWD

    I hope to finish that part tonight.

    TASKSW: $1F8FEDF6
    TASKSWD: $5F8FEDF6
  • SapiehaSapieha Posts: 2,964
    edited 2013-01-03 17:13
    Hi Chip.

    Thanks
  • SeairthSeairth Posts: 2,474
    edited 2013-01-04 04:39
    Seairth wrote: »
    If I recall correctly, some of the instructions can implicitly make use of the value currently latched in the ALU (e.g. as a timeout for WAITPNE). Since I am unfamiliar with the internal hardware, which instructions modify the ALU value? And is the value latched by the ALU regardless of effects flags?

    I just read some material in the Prop2_Docs.txt file that clarifies this. From the WAITPEQ instruction: "the last-written D value becomes a CNTL timeout target, with C returning 0 if the WAITPEQ condition was met, or 1 if the timeout occurred first." Based on the example, I am assuming that the timeout is effectively a CMPCNT. However, precise timing is a little ambiguous here. CMPCNT indicates that C = ! D[31], which would indicate that the the flag would be set (for SUBCNT and CMPCNT) when CNTx is greater than or equal to the test value. (Note: the documentation uses the word "exceeded",)

    So, in the following example (assuming single task):
    GETCNT ticks   ' CNT = 1, ticks = 1
CMPCNT ticks   ' CNT = 2, ticks = 1, CNT - ticks = 1

GETCNT ticks   ' CNT = 3, ticks = 3
ADD ticks, #1  ' CNT = 4, ticks = 4
CMPCNT ticks   ' CNT = 5, ticks = 4, CNT - ticks = 1

GETCNT ticks   ' CNT = 6, ticks = 6
ADD ticks, #2  ' CNT = 7, ticks = 8
CMPCNT ticks   ' CNT = 8, ticks = 8, CNT - ticks = 0

    The C flag will be set all three examples. For any larger value of ticks, the flag would not be set. Now, assuming that WAITPEQ works the same way:
    GETCNT ticks             ' CNT = 1, d-field = 1
WAITPEQ value, mask WC   ' CNT = 2, d-field = 1

GETCNT ticks             ' CNT = 3, d-field = 3
ADD ticks, #1            ' CNT = 4, d-field = 4
WAITPEQ value, mask WC   ' CNT = 5, d-field = 4

GETCNT ticks             ' CNT = 6, d-field = 6
ADD ticks, #2            ' CNT = 7, d-field = 8
WAITPEQ value, mask WC   ' CNT = 8, d-field = 8

GETCNT ticks             ' CNT = 9, d-field = 9
ADD ticks, #3            ' CNT = 10, d-field = 12
WAITPEQ value, mask WC   ' CNT = 11, d-field = 12

    What happens if the pins *are* equal for the first three examples? Does C get set? And does the last example block for one cycle if the pins are not equal?
  • BEEPBEEP Posts: 58
    edited 2013-01-05 09:36
    Prop2_Docs.txt to Prop2_Docs.pdf

    pdf is obsolete and removed.
  • cgraceycgracey Posts: 14,151
    edited 2013-01-09 15:38
    Here is the latest doc's file. The section on branching instructions is now done:

    Prop2_Docs.txt

    Next I'll work on the counter documentation.
    txt
    txt
    Prop2_Docs.txt
    70K
  • SapiehaSapieha Posts: 2,964
    edited 2013-01-09 17:27
    Hi Chip.

    Thanks
    cgracey wrote: »
    Here is the latest doc's file. The section on branching instructions is now done:

    Prop2_Docs.txt

    Next I'll work on the counter documentation.
  • BEEPBEEP Posts: 58
    edited 2013-01-10 05:43
    Prop2_Docs.txt to Prop2_Docs.pdf

    (Prop2_Docs.pdf deleted)
  • Ahle2Ahle2 Posts: 1,179
    edited 2013-01-10 13:08
    @Chip
    Can't wait for the counter modules documentation! :)
    Thank you for this awesome chip, Chip!
  • TubularTubular Posts: 4,702
    edited 2013-01-10 15:31
    Ahle2 wrote: »
    @Chip
    Can't wait for the counter modules documentation! :)
    Thank you for this awesome chip, Chip!

    Yes, counters are going to be awesome. I was looking back over some notes from a Nov 2010 Prop2 presentation. I'm looking forward to playing with the hardware Goertzel feature, that will make all sorts of things possible. There were many other automated "background" features that will make them really useful, especially combined with the task switching.
  • jmgjmg Posts: 15,173
    edited 2013-01-10 18:18
    Tubular wrote: »
    Yes, counters are going to be awesome. I was looking back over some notes from a Nov 2010 Prop2 presentation. I'm looking forward to playing with the hardware Goertzel feature, that will make all sorts of things possible. There were many other automated "background" features that will make them really useful, especially combined with the task switching.

    I have fingers crossed for atomic control of external edge time-capture on two timers ....
  • Cluso99Cluso99 Posts: 18,069
    edited 2013-01-10 20:34
    Chip: For your instructions document posted above...

    For the QUAD GETTOPS instruction, I could not find the byte order described.
  • Cluso99Cluso99 Posts: 18,069
    edited 2013-01-10 22:31
    Here is the latest update to my P2 Instruction Summary (Excel spreadsheet zipped). If you want to print it out, change or remove the darkblue shading (shows updates confirmed to Chips file a few posts back.

    P2_Instructions(14).zip
    zip
    zip
    P2_Instructions(14).zip
    86K
  • cgraceycgracey Posts: 14,151
    edited 2013-01-11 03:31
    Cluso99 wrote: »
    Chip: For your instructions document posted above...

    For the QUAD GETTOPS instruction, I could not find the byte order described.

    The tops bytes of the QUADs get packed into a single long in the order {QUAD3[31..24], QUAD2[31..24], QUAD1[31..24], QUAD0[31..24]}.
  • AribaAriba Posts: 2,690
    edited 2013-01-11 05:13
    cgracey wrote: »
    The tops bytes of the QUADs get packed into a single long in the order {QUAD3[31..24], QUAD2[31..24], QUAD1[31..24], QUAD0[31..24]}.

    What is the purpose of this instruction ? I guess it has to do with graphics.

    Andy
  • jmgjmg Posts: 15,173
    edited 2013-01-21 18:33
    cgracey wrote: »
    Next I'll work on the counter documentation.

    Is this thread where Counter Docs will be updated, or is some DOC on a link going to quietly tick-over ?
    It's nearly 2 weeks since Chip posted the 'next...' - maybe I've missed it ?
  • TubularTubular Posts: 4,702
    edited 2013-01-21 19:11
    Perhaps the counters are so good and powerful they require a book to describe them ... there's clearly a fair bit to them on the P2
  • cgraceycgracey Posts: 14,151
    edited 2013-01-22 10:10
    Sorry it's been taking me so long. I've been getting the DE0-Nano and DE2-115 add-on boards set up and configured in the FPGA tool.

    I'll spend today on the counter doc's. It is a pain to describe the counters, but if they don't get documented, they might as well not exist.
  • David BetzDavid Betz Posts: 14,516
    edited 2013-01-24 10:03
    cgracey wrote: »
    Sorry it's been taking me so long. I've been getting the DE0-Nano and DE2-115 add-on boards set up and configured in the FPGA tool.

    I'll spend today on the counter doc's. It is a pain to describe the counters, but if they don't get documented, they might as well not exist.
    I'm looking forward to the DE2-115 add-on board with the SPI flash chip on it so I can start working on XMM for P2!
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