Personally I think it's time to get the prop II as is into production and out into the market place. From what I've seen of the other chips on the market the prop II will be revolutionary not evolutionary!! I'm looking forward to getting my hands onto a gadget gangster type board and seeing what I can do with it!
Leave the 40nm 1GHZ 16cog microcontroller with 2meg of hub ram for the prop III! At some point a product has to come to market!
Kind of makes sense though, given how the device operates. Those synthesis tools are very interesting Chip! Amazing software really. So many optimizations in such a small amount of time. Thanks for the color image. Intriguing...
I often see similar artifacts on mechanical CAD simulation, and or fluids. What we think is optimal, so often isn't. Simulation software can yield surprising results, and the most interesting part about it is once they are seen, the people then can make much better mental predictive decisions. Valuable stuff. Another area that always exhibits this quality is plastic mold injection simulation. What makes good common sense, often isn't! The flow dynamics of the plastic, and the thermal edge effects play out in ways often hard to just visualize without first running a simulation or two.
This is the first time I've seen it play out on chips, and am expressing the same intrigue Heater is! I'll bet you learn a lot on that simulation Chip! Thanks for sharing the process with us. Appreciated.
Did those guys have any comments, BTW? Would be really interesting to hear what they thought of how the simulation played out, or if they saw similar organic things appear on other devices?
Re: Capital and control.
Frank nailed it! I'll bet they could get the money, but then again, there would be some significant expectations attached to it, not all of which would align with how Chip and Parallax prefer to work. There are distinct advantages to keeping a company held private, and this is one of them.
Typically, a investment of that kind would require a percentage company ownership, IP management, and a person placed in a position of power at Parallax to manage the return on that investment.
Frank, it wasn't my intent to question P-Semi's decisions. Just make a comparison on what VC's are and aren't willing to fund.
Did not take it as such. If I could dump some money in there I would, but not without strings. Many out there are not as familiar with how the game works as evidenced by various postings across the forum and time.
I could develop serious envy of Chip and the ability to play and get paid for it. I know reality is much more complex, but then again my job is serious play as well and I enjoy what I do too. So my play time is a bit restricted.....
My comments weren't directed at anyone in particular. I was just pointing that it's important to release the prop II as is and after it's in production start work on the prop III!
Questions on the current design (if you have time to answer)
1. Does the current design actually have a full 128KB of hub sram but ~2KB of that is inaccessable because of ~2KB of ROM? If so, could not the ROM be mapped out after boot to give this up to the sram, or alternately sit in top of hub (i.e. A0-16=128KB, so A17=0 for ram and A17=1 for ROM or visaversa, so ROM will just repeat every ~2KB. Hate to waste 2KB ram for a few gates.
Current floor plan
I guess the rectangular approach we expect are from our human approach to put things into a block so we can duplicate that block. But once you get to a certain complexity it takes forever. Conceptually, they are the same sort of issues from a PCB design point of view. Without human constraints, very expensive and intelligent software can do these things very fast. Perhaps not to the same level that a human can, but with the complexities nowadays the human would take many man years. So reality steps in. The pie shape is not all that unusal in retrospect.
40nm version PIII (dreaming)
If I were to do a 40nm version, I would be opting for some master cogs. Think of these cogs as an ultra-fast processing cogs. Let the normal cogs do the I/O work. Give the master cogs just basic timers, no access to I/O pins, 2x hub accesses, and with the space saved put more of them. With this concept it could be possible to have 8 of these cogs instead of the extra 4 standard cogs. BTW 2MB of hub ram would be a dream (less ~2K ROM)
Venture Capital
We went down this line in the mid 90's. It is easy in the USA but we would have to move there from Oz. They want control of the company although they do provide the excellent support to permit the designers to just get on with the design without having to run the company too. In Parallax's case, they already have a nice company which is able to fund, albeit not as much as venture capital, their new designs. Chip & co control the company in the way they like. Really, why would you want to do this and give up control. It would become more of a chore than a hobby (because all Parallax staff seem to treat their work as enjoyable).
Forum Funding for Prop II Lets look at this realistically. If 100 forumistas put in $100 that is only $10K. Even if we found 1,000 it is still only $100K. What might we want for that... maybe a prototype chip (not the shuttle because they are very low volume and expensive??) and a first run chip. Now, would that help Parallax... not likely. The issues are man hours and we cannot buy another Chip Gracey. At this late stage any extra help in addition to Beau would most likely slow down, not speed up the design process at this late stage. So, unfortunately, unless some were willing to throw serious money to move to a smaller die geometry such as 90nm (whatever the technical term is) then the whole question is really moot. Nice suggestion but not practical. And lastly, perhaps the work in pad design around the chip edges, and the hub ram and cog ram may have to be redone for a smaller geometry???
Reduced cost disabled chips
This question always starts arguments. It was used extensively in the mini and mainframe computer business very successfully. It enabled a company to sell cheaper computers (with less profit) to boost sales while not taking away from them the core business, giving them more economies of scale. maintenance was also more efficient as engineers needed to carry less spares.
The main reason companies do not disclose this fact is because of user anger as they do not understand the internal business models.
In chips, sometimes it is a yield problem. The company can now sell an otherwise useless part. Or it may be a speed issue. The cost of testing for the higher spec would weed out the better chips which could be sold for a premium. Once the required higher speed yield was reached, the remainder would not be tested for the higher speed. The result was pot luck on the lower speed devices as to whether they could go at a higher speed. Do not knock the concept. If Parallax sees an opportunity to boost volume for lower return on the extras, they will decide with their business model. This is business realities guys.
Blimey, haven't got the Prop II out the door yet and there is all this Prop III speculation arising.
Prop III will of course be 64 bit. That then allows for up to 32MB of COG space. There would be no need for on chip HUB RAM but rather use some serious COG to COG links. Which would also transparently link to COGs on othe chips for potentially huge arrays of processors. All running at 2 to 4 GHz naturally.
Blimey, haven't got the Prop II out the door yet and there is all this Prop III speculation arising.
Prop III will of course be 64 bit. That then allows for up to 32MB of COG space. There would be no need for on chip HUB RAM but rather use some serious COG to COG links. Which would also transparently link to COGs on othe chips for potentially huge arrays of processors. All running at 2 to 4 GHz naturally.
There, can that put an end to it?
With the lead times for new products it's not unusual for a company to start work on the replacement for a product that hasn't even made to market yet.
That is true. If you are an Intel or such you probably have multiple teams working on multiple generations at the same time, pipeline fashion. Not to mention teams working on ventures that never pan out, like Intel's 432 or 960 or Itaniums.
But this is Paralax with one small team to work on one thing at a time. Besides where is the fun in it for Chip to have a team designing the thing for him?
That is true. If you are an Intel or such you probably have multiple teams working on multiple generations at the same time, pipeline fashion. Not to mention teams working on ventures that never pan out, like Intel's 432 or 960 or Itaniums.
But this is Paralax with one small team to work on one thing at a time. Besides where is the fun in it for Chip to have a team designing the thing for him?
From what I can tell Parallax is to small of a company to have multiple design teams working on future generations. In the case of the prop II it's been a long time in the making and if Chip/Parallax continues to redesign the prop II with every change in technology there will never be a prop II. It sounds like the design of the prop II is pretty much set (I missed the webinar earlier this week) and about ready to go into production. Rather then continue to add more features and go with 40nm technology, etc, etc I say they should release what they have as the prop II and look into the 40nm technology, 16 cogs running at 1GHZ, megabytes of hub ram, etc for the prop III!!
16 COGs is not a good idea. It halves the bandwidth into HUB memory effectively stealing half your clock speed. As you have more memory then it would be better to have more bandwidth to get at it with.
Hence my dream Prop III with wider COG registers 40 to 64 bit, allowing huge COG space. No HUB hence no bandwidth issues competing with other cogs for access. High speed COG to COG interconnect instead.
I like the update and the opportunities that have been canvased.
If I had a couple of $M available I'd seriously consider investing in the opportunity. I can see immense potential.
My thoughts on the discussion;
- Finish the Prop II as is, before deciding on the next path. I agree that there are wonderful possibilities with the 40nm technology, hub ram being one of them! However there are still learnings to be gathered from the current plan that should be completed before deviation. Please don't get distracted by something shiney, I see too many technical people never completing what they do because of these temptations.
- Funding. I don't know the regulatory and overhead costs of a private company seeking to raise funding, I've heard listing fees at stock exchanges are prohibitive. However, if they sought to raise capital today, I'd be excited to invest in Parralax Semiconductor to raise money for the 40nm technology. Though this would be a serious financial investment into Parallax Semiconductor (and it's intellectual property), not be a gift, nor would it be to buy a proto copy of the chip. If they were not able to be traded (ie. could not have a way to resell them) then I'd expect a regular dividend from the investment should the profitability of the company increase from the investment (some kind of agreed legal binding formular based on performance would be needed in the proposal). In regards to control of Parallax, I'd be fine for these to be "non-voting" shares leaving the running of the company to the Graceys - fine job they've been doing over the last 20+ years. Maybe they could consider a Parallax Semiconductor IPO? Under my current financial circumstances I'd probably invest about $1K in such an enterprise (maybe more based on the proposition), though it would be dependent on my financial circumstances at the time (as we've seen, situations can change rapidly). I could see this funding other things like the Prop I-B (there is still a lot of puff in the current work-horse, it's just short of pins to capitalize on it's capabilities, and it just runs on 3.3V). To protect my investment, one thing I would require in the IPO is that Parallax Semiconductor develop a code security strategy, as this may be a problem for sales in the future.
One cost-reduced design possibility would be 48 I/O's, 4 cogs, 64KB ram. It would be 1/2 the die size, and fit TQFP-64
Such cost-down variants usually come along later.
A better trade-off in my opinion would be a variant with less COGS, allowing more precious RAM, and with a Multi-thread option on the COGS.
(that would allow a 180MHz.512W COG, to also act as two 90MHz 256W COGs (or even 384/128 COGs etc )
This softens a drawback in Prop, which is the inability to share resource and lack of 'soft edges' in limits.
As I understand the Prop II design today, the outer perimeter of the chip is cast in stone. That is all the I/O routing and all the I/O pin design. Also, I understand the blocks of hub ram are done (although adding/removing blocks is possible) as are the cog ram blocks (although rearranging the rectangular/square attributes can be modified).
That just leaves the cogs including the instruction set and counters and the interfacing to the hub and interfacing to the I/Os. This has been done in Verilog and has been the source of the recent delays due to critical paths and the computer routing. it seems this is now well advanced.
I would presume there are no real hardware changes contemplated.
The 40nm discussion was just a nice sidetrack question raised by Chip to the layout people. We can speculate all we want (as I have done) but in reality, its not going to happen. I would even think that if I were to put $3M on the table (I dont have it!) with no strings attached, it would make no difference.
I am just in awe of what can be done with smaller geometry, and not really significant cash.
A better trade-off in my opinion would be a variant with less COGS, allowing more precious RAM, and with a Multi-thread option on the COGS.
(that would allow a 180MHz.512W COG, to also act as two 90MHz 256W COGs (or even 384/128 COGs etc )
This softens a drawback in Prop, which is the inability to share resource and lack of 'soft edges' in limits.
Cogs already have the capability of multi-threading by using JMPRET
Depends what you mean by multi-threading.
Coopertive threading can be done in many ways and JMPRET is a quick and convenient way on the prop. However it does rely on the programmer sprinkling his code with JMPRETs appropriately. It also means not using WAITxxx which would hang all threads. And that means external events may not get handled as quickly or predictably as you would like.
Preemptive scheduling can also be done in many ways. One simple technique is to execute a single instruction from each thread in a round robin fashion. Each of N threads gets 1/N of the available MIPS, has know fixed latency to events and can use WAITxxx. Also performance is higher as no extra JMPRET instructions are needed which in the worst case eats half your MIPs.
All in all such hardware threading is a neat, simple solution. Rather like the round robin HUB access idea.
For fun, I asked the company that is doing our synthesis work to pass our design through a 40nm-process design flow (TSMC 45G, which I mistakenly called '45nm' in the webinar). I was interested to hear how fast the design could run at 40nm. I was thinking it would top out at ~600MHz. It turns out that it closes timing at 1GHz! That's 1,000 MIPS per cog. Imagine 1,000 instructions every microsecond. If we were to build a version of the Propeller in this 40nm process, it would probably have 16 cogs and 2MB of hub RAM. Imagine 16,000 MIPS per chip! That's 100x the performance of the current Propeller chip. The only big roadblock to realizing this is the $3M required for the mask set.
What no one else seems to have asked yet, is, how many Prop-2s would you need to sell to make up for the Prop2 R&D and produce this? (Prop2-A vs Prop2-U; See AVR32-A vs AVR32-U for source of naming convention)
Preemptive scheduling can also be done in many ways. One simple technique is to execute a single instruction from each thread in a round robin fashion. Each of N threads gets 1/N of the available MIPS, has know fixed latency to events and can use WAITxxx. Also performance is higher as no extra JMPRET instructions are needed which in the worst case eats half your MIPs.
All in all such hardware threading is a neat, simple solution. Rather like the round robin HUB access idea.
Yes, that is pretty much what I had in mind. Simple time-slot stuff, likely limited to a single word load to configure.
16 bits would allow 8 time slots to 'any of 4' threads, 24 bits would allow 8 time slots to 'any of 8' threads + 8 semaphores => 1 word.
'Any of 8' would allow up to 1/8 : 7/8 skews on two tasks, or 8 identical 1/8 MaxMIP threads (etc)
Total code limit does not change.
You know, if Makerbot can get $10M in venture capital for their burned plywood printers, why can't Parallax get a measly $3M for a possible game-changing silicon IP? I guess it really does boil down to "who you know".
i heard rumor about the recent webinar being posted for all us late bloomers.. . where might that be? the webinars posted @ parallaxes website are stale like moldy bread (like 2009 last posted)
i heard rumor about the recent webinar being posted for all us late bloomers.. . where might that be? the webinars posted @ parallaxes website are stale like moldy bread (like 2009 last posted)
That makes two of us who are looking for the webinar, so I'll find out where it is. I had to leave when Andy was talking about the PropBOE so I want to watch it now, along with Chip's presentation.
Speaking of information regarding the PropII, I thought I heard Chip mention that we were clear to post the PropII Assembly Instructions...
Was that the case? Can someone do it please :-)
Thanks,
Red
Hi Red,
I wouldn't hold your breath. I haven't caught up with the full webinar discussions yet, so I'm not sure what Chip actually committed to - but I seem to remember he promised the Prop II instruction set after the previous webinar as well (maybe six or nine months ago?) and it never eventuated then either. Yes, I know he has lots to do, and we would all rather he got on and just finished the Prop II ... but still ... :frown:
Comments
Leave the 40nm 1GHZ 16cog microcontroller with 2meg of hub ram for the prop III! At some point a product has to come to market!
Unfortunately, I fell asleep for the last hour (Midnight to 1:00 AM here)
Will catch up when the Webinar is posted.
Jim
Kind of makes sense though, given how the device operates. Those synthesis tools are very interesting Chip! Amazing software really. So many optimizations in such a small amount of time. Thanks for the color image. Intriguing...
I often see similar artifacts on mechanical CAD simulation, and or fluids. What we think is optimal, so often isn't. Simulation software can yield surprising results, and the most interesting part about it is once they are seen, the people then can make much better mental predictive decisions. Valuable stuff. Another area that always exhibits this quality is plastic mold injection simulation. What makes good common sense, often isn't! The flow dynamics of the plastic, and the thermal edge effects play out in ways often hard to just visualize without first running a simulation or two.
This is the first time I've seen it play out on chips, and am expressing the same intrigue Heater is! I'll bet you learn a lot on that simulation Chip! Thanks for sharing the process with us. Appreciated.
Did those guys have any comments, BTW? Would be really interesting to hear what they thought of how the simulation played out, or if they saw similar organic things appear on other devices?
Re: Capital and control.
Frank nailed it! I'll bet they could get the money, but then again, there would be some significant expectations attached to it, not all of which would align with how Chip and Parallax prefer to work. There are distinct advantages to keeping a company held private, and this is one of them.
Typically, a investment of that kind would require a percentage company ownership, IP management, and a person placed in a position of power at Parallax to manage the return on that investment.
Did not take it as such. If I could dump some money in there I would, but not without strings. Many out there are not as familiar with how the game works as evidenced by various postings across the forum and time.
I could develop serious envy of Chip and the ability to play and get paid for it. I know reality is much more complex, but then again my job is serious play as well and I enjoy what I do too. So my play time is a bit restricted.....
Work to play, and play to work...
Frank
My comments weren't directed at anyone in particular. I was just pointing that it's important to release the prop II as is and after it's in production start work on the prop III!
Questions on the current design (if you have time to answer)
1. Does the current design actually have a full 128KB of hub sram but ~2KB of that is inaccessable because of ~2KB of ROM? If so, could not the ROM be mapped out after boot to give this up to the sram, or alternately sit in top of hub (i.e. A0-16=128KB, so A17=0 for ram and A17=1 for ROM or visaversa, so ROM will just repeat every ~2KB. Hate to waste 2KB ram for a few gates.
Current floor plan
I guess the rectangular approach we expect are from our human approach to put things into a block so we can duplicate that block. But once you get to a certain complexity it takes forever. Conceptually, they are the same sort of issues from a PCB design point of view. Without human constraints, very expensive and intelligent software can do these things very fast. Perhaps not to the same level that a human can, but with the complexities nowadays the human would take many man years. So reality steps in. The pie shape is not all that unusal in retrospect.
40nm version PIII (dreaming)
If I were to do a 40nm version, I would be opting for some master cogs. Think of these cogs as an ultra-fast processing cogs. Let the normal cogs do the I/O work. Give the master cogs just basic timers, no access to I/O pins, 2x hub accesses, and with the space saved put more of them. With this concept it could be possible to have 8 of these cogs instead of the extra 4 standard cogs. BTW 2MB of hub ram would be a dream (less ~2K ROM)
Venture Capital
We went down this line in the mid 90's. It is easy in the USA but we would have to move there from Oz. They want control of the company although they do provide the excellent support to permit the designers to just get on with the design without having to run the company too. In Parallax's case, they already have a nice company which is able to fund, albeit not as much as venture capital, their new designs. Chip & co control the company in the way they like. Really, why would you want to do this and give up control. It would become more of a chore than a hobby (because all Parallax staff seem to treat their work as enjoyable).
Forum Funding for Prop II
Lets look at this realistically. If 100 forumistas put in $100 that is only $10K. Even if we found 1,000 it is still only $100K. What might we want for that... maybe a prototype chip (not the shuttle because they are very low volume and expensive??) and a first run chip. Now, would that help Parallax... not likely. The issues are man hours and we cannot buy another Chip Gracey. At this late stage any extra help in addition to Beau would most likely slow down, not speed up the design process at this late stage. So, unfortunately, unless some were willing to throw serious money to move to a smaller die geometry such as 90nm (whatever the technical term is) then the whole question is really moot. Nice suggestion but not practical. And lastly, perhaps the work in pad design around the chip edges, and the hub ram and cog ram may have to be redone for a smaller geometry???
Reduced cost disabled chips
This question always starts arguments. It was used extensively in the mini and mainframe computer business very successfully. It enabled a company to sell cheaper computers (with less profit) to boost sales while not taking away from them the core business, giving them more economies of scale. maintenance was also more efficient as engineers needed to carry less spares.
The main reason companies do not disclose this fact is because of user anger as they do not understand the internal business models.
In chips, sometimes it is a yield problem. The company can now sell an otherwise useless part. Or it may be a speed issue. The cost of testing for the higher spec would weed out the better chips which could be sold for a premium. Once the required higher speed yield was reached, the remainder would not be tested for the higher speed. The result was pot luck on the lower speed devices as to whether they could go at a higher speed. Do not knock the concept. If Parallax sees an opportunity to boost volume for lower return on the extras, they will decide with their business model. This is business realities guys.
Prop III will of course be 64 bit. That then allows for up to 32MB of COG space. There would be no need for on chip HUB RAM but rather use some serious COG to COG links. Which would also transparently link to COGs on othe chips for potentially huge arrays of processors. All running at 2 to 4 GHz naturally.
There, can that put an end to it?
With the lead times for new products it's not unusual for a company to start work on the replacement for a product that hasn't even made to market yet.
But this is Paralax with one small team to work on one thing at a time. Besides where is the fun in it for Chip to have a team designing the thing for him?
From what I can tell Parallax is to small of a company to have multiple design teams working on future generations. In the case of the prop II it's been a long time in the making and if Chip/Parallax continues to redesign the prop II with every change in technology there will never be a prop II. It sounds like the design of the prop II is pretty much set (I missed the webinar earlier this week) and about ready to go into production. Rather then continue to add more features and go with 40nm technology, etc, etc I say they should release what they have as the prop II and look into the 40nm technology, 16 cogs running at 1GHZ, megabytes of hub ram, etc for the prop III!!
Hence my dream Prop III with wider COG registers 40 to 64 bit, allowing huge COG space. No HUB hence no bandwidth issues competing with other cogs for access. High speed COG to COG interconnect instead.
If I had a couple of $M available I'd seriously consider investing in the opportunity. I can see immense potential.
My thoughts on the discussion;
- Finish the Prop II as is, before deciding on the next path. I agree that there are wonderful possibilities with the 40nm technology, hub ram being one of them! However there are still learnings to be gathered from the current plan that should be completed before deviation. Please don't get distracted by something shiney, I see too many technical people never completing what they do because of these temptations.
- Funding. I don't know the regulatory and overhead costs of a private company seeking to raise funding, I've heard listing fees at stock exchanges are prohibitive. However, if they sought to raise capital today, I'd be excited to invest in Parralax Semiconductor to raise money for the 40nm technology. Though this would be a serious financial investment into Parallax Semiconductor (and it's intellectual property), not be a gift, nor would it be to buy a proto copy of the chip. If they were not able to be traded (ie. could not have a way to resell them) then I'd expect a regular dividend from the investment should the profitability of the company increase from the investment (some kind of agreed legal binding formular based on performance would be needed in the proposal). In regards to control of Parallax, I'd be fine for these to be "non-voting" shares leaving the running of the company to the Graceys - fine job they've been doing over the last 20+ years. Maybe they could consider a Parallax Semiconductor IPO? Under my current financial circumstances I'd probably invest about $1K in such an enterprise (maybe more based on the proposition), though it would be dependent on my financial circumstances at the time (as we've seen, situations can change rapidly). I could see this funding other things like the Prop I-B (there is still a lot of puff in the current work-horse, it's just short of pins to capitalize on it's capabilities, and it just runs on 3.3V). To protect my investment, one thing I would require in the IPO is that Parallax Semiconductor develop a code security strategy, as this may be a problem for sales in the future.
Frank
Such cost-down variants usually come along later.
A better trade-off in my opinion would be a variant with less COGS, allowing more precious RAM, and with a Multi-thread option on the COGS.
(that would allow a 180MHz.512W COG, to also act as two 90MHz 256W COGs (or even 384/128 COGs etc )
This softens a drawback in Prop, which is the inability to share resource and lack of 'soft edges' in limits.
That just leaves the cogs including the instruction set and counters and the interfacing to the hub and interfacing to the I/Os. This has been done in Verilog and has been the source of the recent delays due to critical paths and the computer routing. it seems this is now well advanced.
I would presume there are no real hardware changes contemplated.
The 40nm discussion was just a nice sidetrack question raised by Chip to the layout people. We can speculate all we want (as I have done) but in reality, its not going to happen. I would even think that if I were to put $3M on the table (I dont have it!) with no strings attached, it would make no difference.
I am just in awe of what can be done with smaller geometry, and not really significant cash.
Cogs already have the capability of multi-threading by using JMPRET
Mickster
Coopertive threading can be done in many ways and JMPRET is a quick and convenient way on the prop. However it does rely on the programmer sprinkling his code with JMPRETs appropriately. It also means not using WAITxxx which would hang all threads. And that means external events may not get handled as quickly or predictably as you would like.
Preemptive scheduling can also be done in many ways. One simple technique is to execute a single instruction from each thread in a round robin fashion. Each of N threads gets 1/N of the available MIPS, has know fixed latency to events and can use WAITxxx. Also performance is higher as no extra JMPRET instructions are needed which in the worst case eats half your MIPs.
All in all such hardware threading is a neat, simple solution. Rather like the round robin HUB access idea.
Was that the case? Can someone do it please :-)
Thanks,
Red
Yes, that is pretty much what I had in mind. Simple time-slot stuff, likely limited to a single word load to configure.
16 bits would allow 8 time slots to 'any of 4' threads, 24 bits would allow 8 time slots to 'any of 8' threads + 8 semaphores => 1 word.
'Any of 8' would allow up to 1/8 : 7/8 skews on two tasks, or 8 identical 1/8 MaxMIP threads (etc)
Total code limit does not change.
Why not post the 1 GHz Propeller II on http://www.kickstarter.com/ ? hahaha =D
That makes two of us who are looking for the webinar, so I'll find out where it is. I had to leave when Andy was talking about the PropBOE so I want to watch it now, along with Chip's presentation.
Ken Gracey
http://forums.parallax.com/showthread.php?128723-Propeller-Meetup-Group-Invite
Hi Red,
I wouldn't hold your breath. I haven't caught up with the full webinar discussions yet, so I'm not sure what Chip actually committed to - but I seem to remember he promised the Prop II instruction set after the previous webinar as well (maybe six or nine months ago?) and it never eventuated then either. Yes, I know he has lots to do, and we would all rather he got on and just finished the Prop II ... but still ... :frown:
Ross.