Please keep us updated, Tor. Once you have the dracblade soldered you can experiment with big C programs and also there should be some very interesting things you can do with the FPGA and the propeller.
My CycloneII dev board arrived today (the version with all the bells&whistles (RAM/VGA/etc). Now I just have to figure out how to actually use the hardware! It didn't come with any printed docu, but I got a download link for 50 compressed megs of demo projects and data sheets for the parts. No actual user manual afaict, but I just quickly looked it over. For now I think I must put it on the side while I use my limited evening time to finish soldering my Dracblade.
-Tor
Enjoy your new FPGA board. It's fun to learn on these stuff.
Also - please take note of the Quartus 2 settings - on the Assignment->Device->Device and Pin Options->Unused Pins, please select "As input tri-stated with weak pull-ups", or just "As input tri-stated". You don't want to let the board to get too hot because the thing takes in current at all times.
P.S: your name sounded like "Thor". Could it be related?
Yeah, I noted that concern in your earlier posting, thanks for giving the specifics for how to avoid it - I dont want to start my FPGA career by frying my board!
As for my name, Thor and Tor are just different spellings of the same name, Tor is the most common spelling in Norway but there are some named "Thor" too (e.g. Thor Hushovd, the pro cyclist - last year's world champion), Thor is, I think, the more common spelling in Denmark. It's that old norse thunder god name in any event. It was the third most popular boy's name back when I was born, decades ago, so statistically speaking I almost had to get that name.
Yeah, I noted that concern in your earlier posting, thanks for giving the specifics for how to avoid it - I dont want to start my FPGA career by frying my board!
-Tor
And remember to read some Verilog or VHDL tutorials and literature on the way too. The "Rapid Prototyping of Digital Systems" book is a good read. And of course, a digital electronics book for some reference too.
As for my name, Thor and Tor are just different spellings of the same name, Tor is the most common spelling in Norway but there are some named "Thor" too (e.g. Thor Hushovd, the pro cyclist - last year's world champion), Thor is, I think, the more common spelling in Denmark. It's that old norse thunder god name in any event. It was the third most popular boy's name back when I was born, decades ago, so statistically speaking I almost had to get that name.
Hmm I see. I just read some previews of fantasy novels. Many of them likes to make references to Scandinavian heroes, so there are the "Thor" and "Odin" which I remembered most.
I said earlier that I didn't think that my Mini board supported PLLs, but I was wrong. I just tried a PLL generating a 200 MHz clock from the 50 MHz oscillator on the board and it worked OK, with my LED display cycling four times as fast. The board isn't ideal, though, for use with the PLLs, as they really need more decoupling than is provided.
You need to use the altpll MegaWizard function. This is what it looks like:
@Leon: Didn't want to hijack your R-Pi thread. So I figured I'd hijack this one.
Gotta say that the Cyclone IV is one crazy chip: 22,320 rather fancy logic elements, 66 hardware multipliers, 500,000+ bytes of RAM. Meanwhile, the DE0-Nano is the cutest eval board ever. Together, it's an exceptional combination.
The Cornell tutorials you link at the beginning of this thread are excellent, too. Best I've seen. All together, it is like the ultimate Lego set for the digital nerd.
Recently I read the account of an HDL competition that I thought was delightful. You may have already seen it, but if anyone hasn't, it's a fun read.
Yes, the Cyclone IV is a nice device, and the DE0-Nano is very sexy. The Cyclone V is even better, but costs a lot more and is very hard to get hold of.
Here is another low-cost Cyclone IV board that I bought before the DE0-Nano:
Tools are different, but you can have a single source file target imported into 2 or 3 Projects, if you want to compare the builds.
For learning, the ispLever tools that pair with LC4256ZE, I think have better reporting - you get Boolean Equation outputs so can actually see what your code creates.
Using this, I have seen cases where code compiles without errors, but rather scrambled my intention.
So a re-phrase was needed to sync what I really wanted, and what the tools could do correctly.
For learning, the ispLever tools that pair with LC4256ZE, I think have better reporting - you get Boolean Equation outputs so can actually see what your code creates.
That's what I loved about tools like ABEL...you could see what the logic reduced to. Never once did I pass up the opportunity to inspect the results.
Edit: I have a nagging question I've never found the answer to. How many times can an FPGA be blasted? I know that with my NXP ARM chips, the onboard FLASH is guaranteed for only about 17,000 (iirc) write cycles. But the serial EEPROMs used for Props can take a million or more. Any concern about wearing out an FPGA simply through too many design iterations?
Edit #2: Has anyone ever heard of making a ring oscillator out of an FPGA? In the case of the Cyclone IV, it would consist of 22,319 LE's configured for pass-thru. The 22,320th would be inverting. And of course the output of the chain would be fed to the input. Wonder what frequency that would oscillate at? I'm guessing about 5kHz.
Edit: I have a nagging question I've never found the answer to. How many times can an FPGA be blasted? I know that with my NXP ARM chips, the onboard FLASH is guaranteed for only about 17,000 (iirc) write cycles. But the serial EEPROMs used for Props can take a million or more. Any concern about wearing out an FPGA simply through too many design iterations?
ispMACH 4000ZE Family Data Sheet says Erase/Reprogram Cycle > 1,000 — Cycles
MachXO2 Family Data Sheet is more expansive
Symbol Parameter Min. Max.#1 Units
NPROGCYC Flash Programming cycles per tRETENTION — 10,000 Cycles
Flash functional programming cycles — 100,000
tRETENTION
Data retention at 100°C junction temperature 10 — Years
Data retention at 85°C junction temperature 20 —
#1. Maximum Flash memory reads are limited to 7.5E13 cycles over the lifetime of the product.
I think they are saying 10,000 still meets lifetime, and 100,000 is ok for bench testing, but do not expect full life.
The finite READ limit is unusual, suggest some stress mechanism on Read ?
Many of the Flash FPGA/CPLDs actually use a Flash-loader, so they could load the logic bit-stream without programming the flash, for iterative testing (non power cycling).
I'm not sure how many offer that as an option, but that would sidestep wear of the flash.
Edit #2: Has anyone ever heard of making a ring oscillator out of an FPGA? In the case of the Cyclone IV, it would consist of 22,319 LE's configured for pass-thru. The 22,320th would be inverting. And of course the output of the chain would be fed to the input. Wonder what frequency that would oscillate at? I'm guessing about 5kHz.
Sure, ring oscillators are a common test item. I've not seen one with 22k elements ever attempted tho !!
Usually you add enough to get down to guaranteed clock levels, and then divide-by-N.
Thanks for the great info, jmg. Everything you posted makes sense. I'm sure that even if the Altera Cyclone IV is only rated for 1000 cycles, it is not that the chip will fail to program on the 1001st attempt. It's just that tunneling slowly damages the SiO2 insulator, leakage current rises, and finally the chip can longer make the rated retention time. Same thing with temp...the tiny floating-gate charges leak a lot faster at higher temperatures.
So it's very comforting to know that one can probably reprogram his FPGA indefinitely, just as long as he realizes that after a while, it won't stay programmed forever. So, the more you use it, the more you have to use it.
Regarding the ring oscillator. Yeah, I worded that very badly. One would certainly not need to use 22k elements to make a ring oscillator! In fact I've never heard of such a thing. But that sort of silliness illustrates why I was concerned about wearing the device out - I've got lots of things to try.
I notice that the DE0-Nano board has a 32M SDRAM on the backside, along with a very nice assortment of other chips: ADC, accelerometer, etc. I'd like to use the DRAM as a frame buffer for displaying fractal images. Perhaps the eight cogs of a Prop could perform the actual calculations. Anyway, it's going to keep me busy for a while.
Cyclone IV is one crazy chip: 22,320 rather fancy logic elements, 66 hardware multipliers
...fractal images. Perhaps the eight cogs of a Prop could perform the actual calculations
Looks like you could build a much faster CPU on the FPGA, than any Prop for doing all that fractal calculation.
The challenge might be not to run fractal code on a CPU built on the FPGA but design a dedicated fractal engine using all those multipliers in parallel. That is impliment Mandlebrot in VHDL or Verilog directly.
You guys have got be going now, I really, really need one of those DE0-Nano boards. Having put together the ZOG emulation of a ZPU processor on the Prop I really should get into puting ZPU on an FPGA as it was intended.
I'm intrigued by various FPGA-based FORTH engines. No doubt at all you could create a great ZPU engine, Heater. You might even fit several into one chip.
You don't need the Prop, you can implement a faster processor on the FPGA.
I understand this. Using the Prop is just a personal thing. I guess that's the difference between a job and a hobby. A frame buffer with the depth and resolution I have in mind will be challenge enough for now, anyway.
The author subsequently used dedicated hardware on the FPGA for much higher performance.
That's a great project. Thanks for the link.
Edit:
Here is another low-cost Cyclone IV board that I bought before the DE0-Nano:
Near as I can tell, the Altera USB-Blaster isn't included, and would cost another $13. Or you can get them bundled and save some on freight.
Most FPGAs can be reconfigured indefinitely. The configuration chip will have a limited number of reprogramming cycles, though.
Right you are. I was under the false impression that FPGAs were FLASH-based. But most (including Cyclone IV) are SRAM-based, like the Propeller. Should I ever have to replace anything, it would only be U9.
The Cyclone IV, and FPGAs in general, are so cosmic that they really ought to be sold with a sedative Rx. I'm utterly blown away at what can be accomplished with so little effort and knowledge. Altera, for example, has a whole passel of building blocks that have already been optimized for speed and area, and yet provide all sorts of easy-to-select options.
For example, you can throw together a 32 x 32 multiplier, pipelined or not, without hardly having to know a scrap of Verilog. Then you can add simple glue logic to allow you to interface the multiplier to the Prop in almost any way you can conceive. This is just one little example of the possibilities. The libraries are vast and flexible. Meanwhile, even something like the aforementioned multiplier hardly makes a dent in the resources of the particular FPGA I'm using.
If I hadn't grovelled for years designing and implementing digital logic in old-fashioned ways, modern FPGAs might not seem so revolutionary. As it is, I need a Valium drip.
Unlike my other Altera boards which have a separate connector for programming the flash memory using the Active Serial mode, the DE0-Nano only has a single JTAG connector, which makes programming the flash much more involved. One has to convert the .sof file to a .jic file, which is rather complicated, and the actual programming procedure is more difficult. The whole process is described in the User Manual, but it seems to have been written for an older version of the tools, which makes things even more difficult. I've heard of people not being able to get it working, but I managed it OK.
BTW, my DE0-Nano has a 64 Mbit Altera EPCS64 configuration memory - an upgrade from the earlier boards which only had a 16 Mbit EPCS16. Terasic has said that a Spansion 64 MBit device was to be provided in the upgrade, but they seem to have changed their mind and fitted the Altera chip instead.
You make a good case for the USB Blaster being separate from the FPGA board. Until now, I considered that a liability. Still, loading Nios II code to flash memory has been made easy. I have no experience loading Flash for any other purpose.
FWIW, Terasic must have ultimately made the config memory upgrade. I see that my board has the Spansion chip.
I see a lot of references here to Lattice devices and I am particularly interested in the MachX02 versions.
However I see that the Lattice forums are dead in the water and in fact will be shut down shortly, for someone who will presumably need a lot of community support at first this is not very comforting.
Trouble is I really like the features of the MachX02 but if there's no support that may be a problem.
Any thoughts on this?
Should I move to the "big two" (Altera or Xilinx)?
How does Lattice stack up against them WRT hardware/support/tools?
I'm a very experiences hardware designer, will I even need much support?
When I first started playing with programmable logic many years ago I used Lattice CPLDs, but I switched to Xilinx and Altera when I wanted to get into FPGAs. Anyway, I've never needed any support, so you shouldn't have a problem if you stick with Lattice.
I see a lot of references here to Lattice devices and I am particularly interested in the MachX02 versions.
However I see that the Lattice forums are dead in the water and in fact will be shut down shortly, for someone who will presumably need a lot of community support at first this is not very comforting.
The Lattice starter board has recently bumped to the XO2-7000 device (was the 1200)
I have found it useful to have both XO2 and MacH4000 tool flows, as the Mach4000 has better reporting, and you can better follow what the tools actually did with your code.
My main grumble with the XO2 series, is the package blindspot, where others CPLDs are.
QFN32 is nice and small, but becomes pin-bound quickly. BGA is too many PCB layers. TQFP100 is too large for many apps.
Ice40 are OTP, & Multi-Rail so are more suited to stable, high volume designs. - and Tools are yet another large download...
That said, the Digikey price indications on the ICE40LP384-SG32 (100 $1.31250) do have my attention - if they are correct.
The Lattice on-line store, seems to think differently.
I'm a very experiences hardware designer, will I even need much support?
Probably not that much. The Lattice tools do seem to work - HDLs are rather slow to compile, relative to other tools, but if you start with a 'known working' example and iterate from there, you cannot get too lost.
Thanks guys, I'm slowly wading through the mire that is the vast number of CPLD/FPGA options.
At present I am tossing up between CRII and Lattice MachX02, totally different beasts I know but they both have good features.
CRII has a really good spread of packages which I like, X02 is really only available in 100 and 144 TFQP if you are looking at hand soldering. As it happens they are the two sizes I need to start but having smaller and larger options would be nice. 44/48 and 208 TQFP options would round out the range nicely, CRII has them.
I prefer the granularity of FPGAs and like the embedded "hard" devices in the X02, are they any good? Also as can be seen in Ale's Prop Cog thread you can pack a lot into an X02, Still 15% free and it's only a 1200.
CRII has much more community support but as has been noted maybe that will not be required, then again maybe it will I've just asked some questions of Lattice support, we'll see how responsive they are.
Meanwhile any further input is appreciated.
Leon, I hope I'm not hijacking this thread. I guess this is part of the getting started process.
Comments
Enjoy your new FPGA board. It's fun to learn on these stuff.
Also - please take note of the Quartus 2 settings - on the Assignment->Device->Device and Pin Options->Unused Pins, please select "As input tri-stated with weak pull-ups", or just "As input tri-stated". You don't want to let the board to get too hot because the thing takes in current at all times.
P.S: your name sounded like "Thor". Could it be related?
As for my name, Thor and Tor are just different spellings of the same name, Tor is the most common spelling in Norway but there are some named "Thor" too (e.g. Thor Hushovd, the pro cyclist - last year's world champion), Thor is, I think, the more common spelling in Denmark. It's that old norse thunder god name in any event. It was the third most popular boy's name back when I was born, decades ago, so statistically speaking I almost had to get that name.
-Tor
And remember to read some Verilog or VHDL tutorials and literature on the way too. The "Rapid Prototyping of Digital Systems" book is a good read. And of course, a digital electronics book for some reference too.
Hmm I see. I just read some previews of fantasy novels. Many of them likes to make references to Scandinavian heroes, so there are the "Thor" and "Odin" which I remembered most.
You need to use the altpll MegaWizard function. This is what it looks like:
Gotta say that the Cyclone IV is one crazy chip: 22,320 rather fancy logic elements, 66 hardware multipliers, 500,000+ bytes of RAM. Meanwhile, the DE0-Nano is the cutest eval board ever. Together, it's an exceptional combination.
The Cornell tutorials you link at the beginning of this thread are excellent, too. Best I've seen. All together, it is like the ultimate Lego set for the digital nerd.
Recently I read the account of an HDL competition that I thought was delightful. You may have already seen it, but if anyone hasn't, it's a fun read.
Yes, the Cyclone IV is a nice device, and the DE0-Nano is very sexy. The Cyclone V is even better, but costs a lot more and is very hard to get hold of.
Here is another low-cost Cyclone IV board that I bought before the DE0-Nano:
http://www.ebay.co.uk/itm/FPGA-CORE-Board-EP4CE6E22-with-SDRAM-Powerful-Cyclone-IV-/290738985130?pt=LH_DefaultDomain_0&hash=item43b164d8aa
It's not as well designed as the DE0-Nano but is a lot cheaper.
http://www.latticestore.com/searchresults.aspx?supplieruvid=55850000&searchstring=ICE40HX1K-BLINK-EVN
and they also have the MachXO2 breakout at $29
http://www.latticestore.com/searchresults.aspx?supplieruvid=55850000&searchstring=LCMXO2-1200ZE-B-EVN
and the simpler CPLD model, at $26
http://www.latticestore.com/searchresults.aspx?supplieruvid=55850000&searchstring=LC4256ZE-B-EVN
Tools are different, but you can have a single source file target imported into 2 or 3 Projects, if you want to compare the builds.
For learning, the ispLever tools that pair with LC4256ZE, I think have better reporting - you get Boolean Equation outputs so can actually see what your code creates.
Using this, I have seen cases where code compiles without errors, but rather scrambled my intention.
So a re-phrase was needed to sync what I really wanted, and what the tools could do correctly.
That's what I loved about tools like ABEL...you could see what the logic reduced to. Never once did I pass up the opportunity to inspect the results.
Edit: I have a nagging question I've never found the answer to. How many times can an FPGA be blasted? I know that with my NXP ARM chips, the onboard FLASH is guaranteed for only about 17,000 (iirc) write cycles. But the serial EEPROMs used for Props can take a million or more. Any concern about wearing out an FPGA simply through too many design iterations?
Edit #2: Has anyone ever heard of making a ring oscillator out of an FPGA? In the case of the Cyclone IV, it would consist of 22,319 LE's configured for pass-thru. The 22,320th would be inverting. And of course the output of the chain would be fed to the input. Wonder what frequency that would oscillate at? I'm guessing about 5kHz.
ispMACH 4000ZE Family Data Sheet says
Erase/Reprogram Cycle > 1,000 — Cycles
MachXO2 Family Data Sheet is more expansive
Symbol Parameter Min. Max.#1 Units
NPROGCYC Flash Programming cycles per tRETENTION — 10,000 Cycles
Flash functional programming cycles — 100,000
tRETENTION
Data retention at 100°C junction temperature 10 — Years
Data retention at 85°C junction temperature 20 —
#1. Maximum Flash memory reads are limited to 7.5E13 cycles over the lifetime of the product.
I think they are saying 10,000 still meets lifetime, and 100,000 is ok for bench testing, but do not expect full life.
The finite READ limit is unusual, suggest some stress mechanism on Read ?
Many of the Flash FPGA/CPLDs actually use a Flash-loader, so they could load the logic bit-stream without programming the flash, for iterative testing (non power cycling).
I'm not sure how many offer that as an option, but that would sidestep wear of the flash.
Sure, ring oscillators are a common test item. I've not seen one with 22k elements ever attempted tho !!
Usually you add enough to get down to guaranteed clock levels, and then divide-by-N.
So it's very comforting to know that one can probably reprogram his FPGA indefinitely, just as long as he realizes that after a while, it won't stay programmed forever. So, the more you use it, the more you have to use it.
Regarding the ring oscillator. Yeah, I worded that very badly. One would certainly not need to use 22k elements to make a ring oscillator! In fact I've never heard of such a thing. But that sort of silliness illustrates why I was concerned about wearing the device out - I've got lots of things to try.
I notice that the DE0-Nano board has a 32M SDRAM on the backside, along with a very nice assortment of other chips: ADC, accelerometer, etc. I'd like to use the DRAM as a frame buffer for displaying fractal images. Perhaps the eight cogs of a Prop could perform the actual calculations. Anyway, it's going to keep me busy for a while.
You don't need the Prop, you can implement a faster processor on the FPGA.
I'm working on an add-on board with VGA, and other stuff.
Looks like you could build a much faster CPU on the FPGA, than any Prop for doing all that fractal calculation.
The challenge might be not to run fractal code on a CPU built on the FPGA but design a dedicated fractal engine using all those multipliers in parallel. That is impliment Mandlebrot in VHDL or Verilog directly.
You guys have got be going now, I really, really need one of those DE0-Nano boards. Having put together the ZOG emulation of a ZPU processor on the Prop I really should get into puting ZPU on an FPGA as it was intended.
http://markbowers.org/home/fpga-mandelbrot
It uses the NIOS II processor.
The author subsequently used dedicated hardware on the FPGA for much higher performance:
http://markbowers.org/home/fpga-mandelbrot-2
The Cyclone IV should do even better.
I just tried building ZPU using the Altera Quartus II software. A dual-port RAM needs to be implemented; it should be quite straightforward, though.
Edit: Near as I can tell, the Altera USB-Blaster isn't included, and would cost another $13. Or you can get them
bundled and save some on freight. Right you are. I was under the false impression that FPGAs were FLASH-based. But most (including Cyclone IV) are SRAM-based, like the Propeller. Should I ever have to replace anything, it would only be U9.
http://alvie.com/zpuino/index.html
The ZPU is running at 100 MHz.
Thanks for reminding me about zpuino, looks like Alvaro has done a great job on that project since I last checked it.
For example, you can throw together a 32 x 32 multiplier, pipelined or not, without hardly having to know a scrap of Verilog. Then you can add simple glue logic to allow you to interface the multiplier to the Prop in almost any way you can conceive. This is just one little example of the possibilities. The libraries are vast and flexible. Meanwhile, even something like the aforementioned multiplier hardly makes a dent in the resources of the particular FPGA I'm using.
If I hadn't grovelled for years designing and implementing digital logic in old-fashioned ways, modern FPGAs might not seem so revolutionary. As it is, I need a Valium drip.
BTW, my DE0-Nano has a 64 Mbit Altera EPCS64 configuration memory - an upgrade from the earlier boards which only had a 16 Mbit EPCS16. Terasic has said that a Spansion 64 MBit device was to be provided in the upgrade, but they seem to have changed their mind and fitted the Altera chip instead.
FWIW, Terasic must have ultimately made the config memory upgrade. I see that my board has the Spansion chip.
http://www.latticesemi.com/index.cfm
Don'f forget FPGA 4 FUN:
http://www.fpga4fun.com/
and their related store which has some nice little FPGA boards:
http://www.knjn.com/
I see a lot of references here to Lattice devices and I am particularly interested in the MachX02 versions.
However I see that the Lattice forums are dead in the water and in fact will be shut down shortly, for someone who will presumably need a lot of community support at first this is not very comforting.
Trouble is I really like the features of the MachX02 but if there's no support that may be a problem.
Any thoughts on this?
Should I move to the "big two" (Altera or Xilinx)?
How does Lattice stack up against them WRT hardware/support/tools?
I'm a very experiences hardware designer, will I even need much support?
______
Rob
You get around
Any particular reason you swapped over from Lattice?
I'm still researching but I like the look of the Lattice MachX02 so far. Things like the Spartan 3E needing 3 PSUs put me off.
______
Rob
The Lattice starter board has recently bumped to the XO2-7000 device (was the 1200)
http://www.latticesemi.com/products/developmenthardware/developmentkits/machxo2breakoutboard.cfm
I have found it useful to have both XO2 and MacH4000 tool flows, as the Mach4000 has better reporting, and you can better follow what the tools actually did with your code.
My main grumble with the XO2 series, is the package blindspot, where others CPLDs are.
QFN32 is nice and small, but becomes pin-bound quickly. BGA is too many PCB layers. TQFP100 is too large for many apps.
Ice40 are OTP, & Multi-Rail so are more suited to stable, high volume designs. - and Tools are yet another large download...
That said, the Digikey price indications on the ICE40LP384-SG32 (100 $1.31250) do have my attention - if they are correct.
The Lattice on-line store, seems to think differently.
Yes, I saw the LPC forum cock-up. I run the LPC2000 Yahoo group which is a lot more popular than NXP's forums. They even mention it on their web site.
It was many years ago when I abandoned Lattice! I think it was when Xilinx and Altera made their free tools available.
Probably not that much. The Lattice tools do seem to work - HDLs are rather slow to compile, relative to other tools, but if you start with a 'known working' example and iterate from there, you cannot get too lost.
Ale is doing some Prop related work on LatticeXO2 boards, take a look at
http://forums.parallax.com/showthread.php/146345-A-simpler-COG?p=1175588&viewfull=1#post1175588
At present I am tossing up between CRII and Lattice MachX02, totally different beasts I know but they both have good features.
CRII has a really good spread of packages which I like, X02 is really only available in 100 and 144 TFQP if you are looking at hand soldering. As it happens they are the two sizes I need to start but having smaller and larger options would be nice. 44/48 and 208 TQFP options would round out the range nicely, CRII has them.
I prefer the granularity of FPGAs and like the embedded "hard" devices in the X02, are they any good? Also as can be seen in Ale's Prop Cog thread you can pack a lot into an X02, Still 15% free and it's only a 1200.
CRII has much more community support but as has been noted maybe that will not be required, then again maybe it will
Meanwhile any further input is appreciated.
Leon, I hope I'm not hijacking this thread. I guess this is part of the getting started process.
______
Rob