I had been looking a FPGAs, thought they would be too expensive (SW) and did not know how to start. The eBay store you pointed has amazingly affordable product to start. I appreciate the write up on your personal page and the time you have taken to share. Certainly posting it in General Discussion appears to be the right place to be less contentious.
I think like most of us, we have fun solving problems. Your FPGA-Prop post is very useful to allow folks to offload difficult tasks to the FPGA (ie. image processing).
In regards to SW radios. A friend of mine was telling me about a SW radio built on a high end FPGA programmed via a spreadsheet! That sounds very interesting!
I've just designed a PCB for the EP2C5 Mini board that will act as a simple front panel for the little processor in Hamblen et al's book and am getting 10 boards made very cheaply by ITead Studios. Some years ago I implemented that processor on a Flex10K FPGA using a similar interface - there are two buttons for clock/data and a single display that cycles through the data. It performs the same function as the switches and lights on the old mini-computers.
I just bought the FPGA training board from the ebay store Leon has suggested.
I compiled a code in Verilog, and to multiplex a 7-segment display. I have multiplexed three of them, and had used 300Hz refresh rate, and not sure whether that high refresh rate is neccessary or the my compilation is not efficient.
However, I do not know whether to draw designs using Verilog, or just to use the digital logic blocks in the Quartus 2 drawing board. For now I heard that Verilog sometimes produce nasty code which does not give good emulation. I may be wrong though.
I doubt if it can be built much cheaper than the assembled boards, though.
My boards are on their way to me, they only took four days to be made. I went for registered air mail delivery because it seemed a bit silly to pay $35 to DHL for something costing $10.
I doubt if it can be built much cheaper than the assembled boards, though.
My boards are on their way to me, they only took four days to be made. I went for registered air mail delivery because it seemed a bit silly to pay $35 to DHL for something costing $10.
The board is not that "mini breakout board" you suggested earlier - it is a whole board with switches, Altera Cyclone 2 (and with 8000 of little things called logic cells inside), one SDRAM, one flash memory, and some ports and other supporting peripherals like VGA and PS/2 port all inside.
I'm planning to write something complex like an 8-bit adder inside or something like that, but surely, in Verilog, I can't just write a .v file contains "take in A and B and add them up with '+'" only. As last seen in my digital logic book, I have to draw all the gates up first and do it one-by-one, like pasting the AND gates and the stuff onto the Quartus 2 drawing board and lump them up as a symbol later.
I will order some breakout boards once I have grasped the fundamentals and might be combining with a Prop.
I got a Digilent/Xilinx Spartan-3 board some years ago which is similar to that one you've got. I think they start at $109, but a Xilinx cable is also required which pushes the cost up. Here it is:
You can do an adder in Verilog, it should be very easy. Here is an adder/subtractor written in VHDL that I found on the Altera web site:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
PACKAGE my_package IS
CONSTANT ADDER_WIDTH : integer := 5;
CONSTANT RESULT_WIDTH : integer := 6;
SUBTYPE ADDER_VALUE IS integer RANGE 0 TO 2 ** ADDER_WIDTH - 1;
SUBTYPE RESULT_VALUE IS integer RANGE 0 TO 2 ** RESULT_WIDTH - 1;
END my_package;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.my_package.ALL;
ENTITY addsub IS
PORT
(
a: IN ADDER_VALUE;
b: IN ADDER_VALUE;
addnsub: IN STD_LOGIC;
result: OUT RESULT_VALUE
);
END addsub;
ARCHITECTURE rtl OF addsub IS
BEGIN
PROCESS (a, b, addnsub)
BEGIN
IF (addnsub = '1') THEN
result <= a + b;
ELSE
result <= a - b;
END IF;
END PROCESS;
END rtl;
It's very simple, you can probably find one there written in Verilog.
VHDL and Verilog are very high-level languages, you can do anything with them.
I believe those VHDL and Verilog are then converted into equivalent logic hardware once it's compiled, isn't it?
By the way, I 'downloaded' my code into the board, it only works when I turned it on. When I shut it off, it is back to the default program that the factory uploaded inside. I think I may be putting the code into the RAM inside?
Leon,
A five bit adder. You are going to end up with a funky CPU:)
Why are there two subtypes for ADDER_VALUE and ADDER_RESULT both the same?
I must find time to get into FPGA's. Just now I only have GHDL to play with simulations under Linux.
John A. Zoidburg,
Yes you will have to get your binary loaded into the FLASH some how to make it "stick". Rather like with the Prop programming isn't it.
Which makes me think. Designing hardware functions in VHDL/Verilog is not like normal sequential program writing. There will be a lot of little parallel actions going on. They generally want to be synchronised with clocks.
But those who have become familiar with parallel programming on the Prop, lots of little parallel actions going on, might have an easier time getting to grips with FPGA.
I believe those VHDL and Verilog are then converted into equivalent logic hardware once it's compiled, isn't it?
Yes, the process is called "synthesis". The synthesised code is then placed and routed, and can then be loaded into the device.
By the way, I 'downloaded' my code into the board, it only works when I turned it on. When I shut it off, it is back to the default program that the factory uploaded inside. I think I may be putting the code into the RAM inside?
You are writing to the FPGA RAM, so the configuration is lost when power is removed. You need to use the Quartus II Programmer function to write a .pof file to the configuration device on the board, You use the AS connector instead of the JTAG connector and Active Serial mode. If you select the AS mode and load the .pof file you should see the file and the configuration device in the upper window of the programmer dialogue box, instead of the .sof file and the FPGA you see when using JTAG. It can then be written to the configuration device.
Using an HDL isn't really programming; one is designing hardware, which is inherently parallel. I remember an occam Users Group conference many years ago when David May said that hardware engineers find parallel processing much easier than software people. The same probably applies to FPGAs.
Leon,
A five bit adder. You are going to end up with a funky CPU:)
Why are there two subtypes for ADDER_VALUE and ADDER_RESULT both the same?
I must find time to get into FPGA's. Just now I only have GHDL to play with simulations under Linux.
I think that the subtypes are 1 bit less to allow for a sign bit.
You can download the Quartus II software and use the simulator with actual FPGA targets, such as the one on the board I have, even if you don't have any FPGA hardware.
Sorry, didn't notice, the result type is 1 bit wider presumeably to allow for carry. Still a 5 bit input with no carry in.
GHDL is great for experiments. The difficulty is in knowing which VHDL features and constructs are not going to be synthesizable into a real device.
--
-- hello_world.vhd
--
-- The ?Hello World? example for FPGA programming.
--
-- Author: Martin Schoeberl (martin@jopdesign.com)
--
-- 2006-08-04 created
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity hello_world is
port (
clk : in std_logic;
led : out std_logic
);
end hello_world;
architecture rtl of hello_world is
constant CLK_FREQ : integer := 50000000;
constant BLINK_FREQ : integer := 10;
constant CNT_MAX : integer := CLK_FREQ/BLINK_FREQ/2-1;
signal cnt : unsigned(24 downto 0);
signal blink : std_logic;
begin
process(clk)
begin
if rising_edge(clk) then
if cnt=CNT_MAX then
cnt <= (others => '0');
blink <= not blink;
else
cnt <= cnt + 1;
end if;
end if;
end process;
led <= blink;
end rtl;
It works on my EP2C5 Mini Board.
Quartus II makes all unused pins as outputs connected to Gnd by default, which could damage those pins on some boards. It's a good idea to configure them as inputs with a weak pull-up - double-click on the device in the Hierarchy window, click on Device and Pin Options, and select "As input tri-stated with weak pull-up". You will get a warning about if, anyway.
--
-- hello_world.vhd
--
-- The ?Hello World? example for FPGA programming.
--
-- Author: Martin Schoeberl (martin@jopdesign.com)
--
-- 2006-08-04 created
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity hello_world is
port (
clk : in std_logic;
led : out std_logic
);
end hello_world;
architecture rtl of hello_world is
constant CLK_FREQ : integer := 50000000;
constant BLINK_FREQ : integer := 10;
constant CNT_MAX : integer := CLK_FREQ/BLINK_FREQ/2-1;
signal cnt : unsigned(24 downto 0);
signal blink : std_logic;
begin
process(clk)
begin
if rising_edge(clk) then
if cnt=CNT_MAX then
cnt <= (others => '0');
blink <= not blink;
else
cnt <= cnt + 1;
end if;
end if;
end process;
led <= blink;
end rtl;
It works on my EP2C5 Mini Board.
Quartus II makes all unused pins as outputs connected to Gnd by default, which could damage those pins on some boards. It's a good idea to configure them as inputs with a weak pull-up - double-click on the device in the Hierarchy window, click on Device and Pin Options, and select "As input tri-stated with weak pull-up". You will get a warning about if, anyway.
I almost destroy the whole board because of the default settings. The whole board gets hot and I had to shut it down and let it cool down instead. Thank goodness I checked out online, and turn them with tri-stated instead. It runs cooler after that option.
By the way, some of the warnings I had during compilation is "Output pins are tied to VCC or GND". I'm not sure why it said so, despite having them tri-stated already.
I've not seen that warning about outputs tied to Vcc or Gnd. Select it and try the on-line Help. It should give some more info and how to avoid the problem.
Please keep working on the tutorial - I'm finding this thread absolutely fascinating.
One thing I'm a little unclear about is how many 'gates' equates to how many 'equivalent 74xx logic chips', and also the differences with all the FPGA chips. For instance, will a microprocessor emulation like a 8051 or a Z80 run on all the FPGA's in this series, or only the high end ones?
Altera provides some 74xx devices as symbols that can be added to a schematic. I'm not sure how to find the gate equivalent of them, though.
8-bit CPUs like a Z80 will easily fit in a small device like the EP2C5T144, including VGA output and keyboard and mouse interfaces. John Kent has implementations of various MPUs on his web site:
This is fascinating stuff. Ok, this is my 'ideal' micro setup, which is slowly coming together on the propeller, and maybe it can be done of FPGA as well? Or a hybrid:
1) Low power consumption - ideally chip is warm but not hot (no heatsinks on chips). My android pandapad is great but fails on this count.
2) Display with a decent resolution and number of pixels eg 320x240 8 bit color, or more. (video ram 100k and up)
3) SD card access with drivers that are easy to use (like on the propeller)
4) Keyboard, mouse, serial port, general purpose I/O pins
5) Ability to run large programs where you can get on with coding without having to run out of memory. (chips that can't do this include the picaxe, propeller with spin (32k is too small), and CP/M (48k is too small)). Ram = hundreds of kilobytes to megabytes, and ideally a single chip (jazzed's 32mb ram chip, or the 512k sram we use in many prop projects). I'd name C and Basic as two languages I like to code in, but other languages would be fine too (even "big spin", if it existed).
I see on that link above to John Kent's page, a number of micro emulations. This opens up lots of possibilities as you could select the right micro emulation to do the job.
I'm trying to get my head around how these FPGAs are different. eg on a Z80 board, a "serial" device is a uart chip with a crystal. On a Propeller, a serial device is some code in a cog. On a FPGA, is a serial device a uart in software that you connect up to your micro of choice? Or do you pick a micro emulation that already includes the serial device?
4) Keyboard, mouse, serial port, general purpose I/O pins
Likewise
5) Ability to run large programs
Just get an FPG board with a load of RAM, as discussed above on this thread.
...a number of micro emulations.
Enter ZOG. Well no actually the ZPU design from Zylin, the smallest 32 bit CPU design for FPGA's in the world (or so they claim).
Of course there are many others but the ZPU is a good small simple place to start and the is even a head start with the ZPUINO here: http://zpuino.blogspot.com/
Looks like the Zpuino already does all of what you want already:)
Now, regarding how you hook up "software" processors, UARTS, RAM, timers etc conceptually it is the same as you do in real hardware.
Consider an old CP/M S100 bus based system like an Altair. It has a 8080 CPU, it has UARTS, TIMERS, RAM etc all connected via that S100 bus.
So it is with a system designed on VHDL/VERILOG. You create software objects that implement CPU, UARTS, TIMERS, RAM etc. AND you create a software object that implements the BUS that links them all together.
If your BUS is designed to a commonly accepted standard then you can mix and match peripheral components designed by others. Such a standard bus spec is "wishbone" as used by opencores.org.
I'm also following the thread with great interest. And that other thread about specific, cheap FPGA dev. boards. I know next to nothing about fpga, except what you can do with them on a theoretical level. Thanks to Dr_Acula for coming up with those questions so that I won't have to! :-)
I'm also wondering about how universal these are - I know the names Altera, and Xilinx, for example, but are they interchangable? I mean, if you start out with, say, Altera, are you then somehow 'commited' to Altera, or can you move your designs over to something else later?
That other thread as well as this one have links to several different dev. boards, e.g. "Altera CycloneII EP2C5T144 FPGA Mini Development Board", "Altera CycloneII EP2C8Q208 NIOS II SOPC FPGA Main Board", and except for the differences in externals (RAM and so on), they apparently use different FPGAs too. Ditto other boards/FPGAs that have been mentioned here and there. When looking at specs, what should utter beginners look for? What numbers will limit what we can do with them, if we, say, want to try some 6502 or 65816 cores, or, to make it more generic - which FPGAs would you use for that kind of stuff v.s. FPGAs for doing just I/O for some CPU?
This is fascinating stuff. Things like the 'wishbone' bus, and, of course Zog.
It sounds like FPGAs can do an awful lot of clever things. Maybe they can do 'everything', but assuming they can't, could one consider a hybrid FPGA and Propeller circuit? Say for instance, you had your nifty spin/pasm object and you know it works and you want to drop it into a board without recoding it. I wonder what would be a good hybrid solution. Maybe devote 10 prop pins for a fast byte-wide +2 control parallel bus between the FPGA and the Prop? That would leave plenty of pins free on both for other things.
This could be as simple as a Gadget Gangster add-on board that takes 10 of the prop pins and takes them to a 10 way header ready for a short cable to the FPGA. Maybe some series 1k resistors to prevent shorts etc. Do FPGAs run on 3V or 5V?
A design for an X device can be ported to an A chip, and the actual HDL code should work on either. However, things like RAM and generated functions such as those created by Altera's Mega-Function facility will need some work.
The FPGAs on those two boards you mentioned are both Cyclone IIs, but are different in size and number of pins. The smaller EP2C5T144 is fine for implementing an 8-bit CPU like a Z80, and ZOG should be feasible. I'd use a CPLD if I just needed some I/O, I've put them on home-made single-sided PCBs.
Dr_A,
Further to Heater's excellent response to your questions, here is a VHDL UART:
Ale has designed a PCB for a hybrid Propeller-FPGA system, using a Xilinx Spartan-3 XC3S200 device, he gave me one to play with. He had several boards made and mentioned the project here, but no one was interested. It's a nice board.
Modern FPGAs require at least two supplies - the Cyclone II requires 1.2V for the core, and,something like 3.3V or less for the I/Os. Different I/O banks can have different voltages for different I/O standards. None of the current devices offer 5V.
I've just received the little PCBs I ordered for the CPU user I/F for my EP2C5T144 Mini board. I received 11 boards, so I can make them available to anyone who wants one (free).
I did a search on Ale Propeller FPGA and came up with a forum post from 2009 that looks intriguing. Maybe such a hybrid needs to show how to do something that can't be done easily with the prop - eg a video driver with half a meg of sram.
Are most FPGAs in physical chips with those tiny pads that are close together? There are so many to choose from, and by limiting the choice to boards like the one at the beginning of this link that brings things out to 0.1" headers it would make the chips more accessable. Then I guess you have to look at price vs performance. I'm still dreaming of adding external video to a propeller but I'm also very open to doing the same thing with a FPGA.
All the current devices are in either fine-pitch QFP (0.5 mm lead spacing) or BGA. The latest Xilinx Spartan-6 devices are only available in BGA.
The older Cyclone II on those low-cost boards has more performance than you are likely to need. A typical design should be capable of being clocked at over 250 MHz, but those cheap boards don't provide access to the PLL, so you are restricted to 50 MHz max. from the on-board oscillator.
I've been testing the FPGA by writing a program of a simple clock, inspired by the Sanyo's LM8560. Up to that, I know what is going on the block diagram of the clock chip, but to think of the counters and the gates and bit by bit, it can be tedious.
So I ended up writing in a "Behavioural" description instead of a "Structural" - would a "Behavioural" description produces unoptimized logic circuitry?
I wonder how the IC designers planned their circuits before they gonna fabricate them in HDL. Unfortunately, I do not know anyone who worked in any customised IC sector.
Tor: For begineers, get a board with the peripherals like VGA port and SDRAM. You may spend less time wiring them and more time to concentrate on the development of the HDL.
Comments
This is most helpful :-)
I had been looking a FPGAs, thought they would be too expensive (SW) and did not know how to start. The eBay store you pointed has amazingly affordable product to start. I appreciate the write up on your personal page and the time you have taken to share. Certainly posting it in General Discussion appears to be the right place to be less contentious.
I think like most of us, we have fun solving problems. Your FPGA-Prop post is very useful to allow folks to offload difficult tasks to the FPGA (ie. image processing).
In regards to SW radios. A friend of mine was telling me about a SW radio built on a high end FPGA programmed via a spreadsheet! That sounds very interesting!
Thank you for sharing.
Cheers,
Dave
I compiled a code in Verilog, and to multiplex a 7-segment display. I have multiplexed three of them, and had used 300Hz refresh rate, and not sure whether that high refresh rate is neccessary or the my compilation is not efficient.
However, I do not know whether to draw designs using Verilog, or just to use the digital logic blocks in the Quartus 2 drawing board. For now I heard that Verilog sometimes produce nasty code which does not give good emulation. I may be wrong though.
You seem to be the first person here to get one of those boards.
An HDL such as Verilog or VHDL is the usual way to design an FPGA application. IIRC, those logic blocks are converted to VHDL!
ITead Studio who are making that PCB of mine sells a bare PCB for that FPGA board:
http://iteadstudio.com/store/index.php?main_page=product_info&cPath=19_21&products_id=259
I doubt if it can be built much cheaper than the assembled boards, though.
My boards are on their way to me, they only took four days to be made. I went for registered air mail delivery because it seemed a bit silly to pay $35 to DHL for something costing $10.
The board is not that "mini breakout board" you suggested earlier - it is a whole board with switches, Altera Cyclone 2 (and with 8000 of little things called logic cells inside), one SDRAM, one flash memory, and some ports and other supporting peripherals like VGA and PS/2 port all inside.
I'm planning to write something complex like an 8-bit adder inside or something like that, but surely, in Verilog, I can't just write a .v file contains "take in A and B and add them up with '+'" only. As last seen in my digital logic book, I have to draw all the gates up first and do it one-by-one, like pasting the AND gates and the stuff onto the Quartus 2 drawing board and lump them up as a symbol later.
I will order some breakout boards once I have grasped the fundamentals and might be combining with a Prop.
http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,799&Prod=S3BOARD
You can do an adder in Verilog, it should be very easy. Here is an adder/subtractor written in VHDL that I found on the Altera web site:
It's very simple, you can probably find one there written in Verilog.
VHDL and Verilog are very high-level languages, you can do anything with them.
By the way, I 'downloaded' my code into the board, it only works when I turned it on. When I shut it off, it is back to the default program that the factory uploaded inside. I think I may be putting the code into the RAM inside?
A five bit adder. You are going to end up with a funky CPU:)
Why are there two subtypes for ADDER_VALUE and ADDER_RESULT both the same?
I must find time to get into FPGA's. Just now I only have GHDL to play with simulations under Linux.
Yes you will have to get your binary loaded into the FLASH some how to make it "stick". Rather like with the Prop programming isn't it.
Which makes me think. Designing hardware functions in VHDL/Verilog is not like normal sequential program writing. There will be a lot of little parallel actions going on. They generally want to be synchronised with clocks.
But those who have become familiar with parallel programming on the Prop, lots of little parallel actions going on, might have an easier time getting to grips with FPGA.
Yes, the process is called "synthesis". The synthesised code is then placed and routed, and can then be loaded into the device.
You are writing to the FPGA RAM, so the configuration is lost when power is removed. You need to use the Quartus II Programmer function to write a .pof file to the configuration device on the board, You use the AS connector instead of the JTAG connector and Active Serial mode. If you select the AS mode and load the .pof file you should see the file and the configuration device in the upper window of the programmer dialogue box, instead of the .sof file and the FPGA you see when using JTAG. It can then be written to the configuration device.
Using an HDL isn't really programming; one is designing hardware, which is inherently parallel. I remember an occam Users Group conference many years ago when David May said that hardware engineers find parallel processing much easier than software people. The same probably applies to FPGAs.
I think that the subtypes are 1 bit less to allow for a sign bit.
You can download the Quartus II software and use the simulator with actual FPGA targets, such as the one on the board I have, even if you don't have any FPGA hardware.
GHDL is great for experiments. The difficulty is in knowing which VHDL features and constructs are not going to be synthesizable into a real device.
I had synthesized a 3-digit 7-segment decoder multiplexer altogether with the Verilog.
Also, I'm just getting used to the program flow which is in parallel... I need to cook up new ways to write Verilog instead of C.
http://www.amazon.com/Verilog-HDL-Synthesis-Practical-Primer/dp/0965039153/ref=sr_1_5?s=books&ie=UTF8&qid=1312194481&sr=1-5
I've ordered a used copy of the VHDL version.
Here is a nice LED flasher written in VHDL:
It works on my EP2C5 Mini Board.
Quartus II makes all unused pins as outputs connected to Gnd by default, which could damage those pins on some boards. It's a good idea to configure them as inputs with a weak pull-up - double-click on the device in the Hierarchy window, click on Device and Pin Options, and select "As input tri-stated with weak pull-up". You will get a warning about if, anyway.
I almost destroy the whole board because of the default settings. The whole board gets hot and I had to shut it down and let it cool down instead. Thank goodness I checked out online, and turn them with tri-stated instead. It runs cooler after that option.
By the way, some of the warnings I had during compilation is "Output pins are tied to VCC or GND". I'm not sure why it said so, despite having them tri-stated already.
What is the actual board that you got?
I'm still testing the PS2 and the vga ports as I worry that the outputs may get fried when it's getting a bit too hot.
The other things like the SDRAM and the flash memory, I would worry about them later. The rest of the switches and the 7-segs are okay though.
One thing I'm a little unclear about is how many 'gates' equates to how many 'equivalent 74xx logic chips', and also the differences with all the FPGA chips. For instance, will a microprocessor emulation like a 8051 or a Z80 run on all the FPGA's in this series, or only the high end ones?
8-bit CPUs like a Z80 will easily fit in a small device like the EP2C5T144, including VGA output and keyboard and mouse interfaces. John Kent has implementations of various MPUs on his web site:
http://members.optusnet.com.au/jekent/FPGA.htm#Section5.12
I've run his System09 on my Spartan-3 board, with VGA output and keyboard input.
I've compiled the MIPS 32-bit processor in Hamblen et al's book, it required an EP2C15AF484C8 with 484 pins. Here is the flow summary:
Total combinational functions 1,713 / 14,448 ( 12 % ) Flow Status Successful - Tue Aug 02 00:40:05 2011
Dedicated logic registers 1,000 / 14,448 ( 7 % ) Quartus II Version 11.0 Build 157 04/27/2011 SJ Web Edition
Revision Name MIPS
Top-level Entity Name MIPS
Family Cyclone II
Device EP2C15AF484C8
Timing Models Final
Total logic elements 1,713 / 14,448 ( 12 % )
Total registers 1000
Total pins 176 / 315 ( 56 % )
Total virtual pins 0
Total memory bits 16,384 / 239,616 ( 7 % )
Embedded Multiplier 9-bit elements 0 / 52 ( 0 % )
Total PLLs 0 / 4 ( 0 % )
The main constraint is the number of pins, it didn't use all that much of the available logic.
1) Low power consumption - ideally chip is warm but not hot (no heatsinks on chips). My android pandapad is great but fails on this count.
2) Display with a decent resolution and number of pixels eg 320x240 8 bit color, or more. (video ram 100k and up)
3) SD card access with drivers that are easy to use (like on the propeller)
4) Keyboard, mouse, serial port, general purpose I/O pins
5) Ability to run large programs where you can get on with coding without having to run out of memory. (chips that can't do this include the picaxe, propeller with spin (32k is too small), and CP/M (48k is too small)). Ram = hundreds of kilobytes to megabytes, and ideally a single chip (jazzed's 32mb ram chip, or the 512k sram we use in many prop projects). I'd name C and Basic as two languages I like to code in, but other languages would be fine too (even "big spin", if it existed).
I see on that link above to John Kent's page, a number of micro emulations. This opens up lots of possibilities as you could select the right micro emulation to do the job.
I'm trying to get my head around how these FPGAs are different. eg on a Z80 board, a "serial" device is a uart chip with a crystal. On a Propeller, a serial device is some code in a cog. On a FPGA, is a serial device a uart in software that you connect up to your micro of choice? Or do you pick a micro emulation that already includes the serial device?
Please keep the tutorials coming!
A worthy goal, I think you'll find FPGA's are a bit power hungry but heat should not be a problem. Apparently quite easy, check this link for a simple 640x480 VGA display driver in VHDL.
http://www.eetimes.com/design/programmable-logic/4015149/Design-Recipes-for-FPGAs--A-Simple-VGA-Interface
That page also references an interesting FPGA cookbook - "Design Recipes for FPGAs" by Peter Wilson Easy I'm sure. Likewise Just get an FPG board with a load of RAM, as discussed above on this thread. Enter ZOG. Well no actually the ZPU design from Zylin, the smallest 32 bit CPU design for FPGA's in the world (or so they claim).
Of course there are many others but the ZPU is a good small simple place to start and the is even a head start with the ZPUINO here:
http://zpuino.blogspot.com/
Looks like the Zpuino already does all of what you want already:)
Now, regarding how you hook up "software" processors, UARTS, RAM, timers etc conceptually it is the same as you do in real hardware.
Consider an old CP/M S100 bus based system like an Altair. It has a 8080 CPU, it has UARTS, TIMERS, RAM etc all connected via that S100 bus.
So it is with a system designed on VHDL/VERILOG. You create software objects that implement CPU, UARTS, TIMERS, RAM etc. AND you create a software object that implements the BUS that links them all together.
If your BUS is designed to a commonly accepted standard then you can mix and match peripheral components designed by others. Such a standard bus spec is "wishbone" as used by opencores.org.
I'm also wondering about how universal these are - I know the names Altera, and Xilinx, for example, but are they interchangable? I mean, if you start out with, say, Altera, are you then somehow 'commited' to Altera, or can you move your designs over to something else later?
That other thread as well as this one have links to several different dev. boards, e.g. "Altera CycloneII EP2C5T144 FPGA Mini Development Board", "Altera CycloneII EP2C8Q208 NIOS II SOPC FPGA Main Board", and except for the differences in externals (RAM and so on), they apparently use different FPGAs too. Ditto other boards/FPGAs that have been mentioned here and there. When looking at specs, what should utter beginners look for? What numbers will limit what we can do with them, if we, say, want to try some 6502 or 65816 cores, or, to make it more generic - which FPGAs would you use for that kind of stuff v.s. FPGAs for doing just I/O for some CPU?
Hm.. you can tell I don't know much, huh? :-)
-Tor
It sounds like FPGAs can do an awful lot of clever things. Maybe they can do 'everything', but assuming they can't, could one consider a hybrid FPGA and Propeller circuit? Say for instance, you had your nifty spin/pasm object and you know it works and you want to drop it into a board without recoding it. I wonder what would be a good hybrid solution. Maybe devote 10 prop pins for a fast byte-wide +2 control parallel bus between the FPGA and the Prop? That would leave plenty of pins free on both for other things.
This could be as simple as a Gadget Gangster add-on board that takes 10 of the prop pins and takes them to a 10 way header ready for a short cable to the FPGA. Maybe some series 1k resistors to prevent shorts etc. Do FPGAs run on 3V or 5V?
A design for an X device can be ported to an A chip, and the actual HDL code should work on either. However, things like RAM and generated functions such as those created by Altera's Mega-Function facility will need some work.
The FPGAs on those two boards you mentioned are both Cyclone IIs, but are different in size and number of pins. The smaller EP2C5T144 is fine for implementing an 8-bit CPU like a Z80, and ZOG should be feasible. I'd use a CPLD if I just needed some I/O, I've put them on home-made single-sided PCBs.
Dr_A,
Further to Heater's excellent response to your questions, here is a VHDL UART:
http://esd.cs.ucr.edu/labs/uart/uart.html
The other labs are interesting:
http://esd.cs.ucr.edu/lab_index.html
They use a Xilinx board.
Ale has designed a PCB for a hybrid Propeller-FPGA system, using a Xilinx Spartan-3 XC3S200 device, he gave me one to play with. He had several boards made and mentioned the project here, but no one was interested. It's a nice board.
Modern FPGAs require at least two supplies - the Cyclone II requires 1.2V for the core, and,something like 3.3V or less for the I/Os. Different I/O banks can have different voltages for different I/O standards. None of the current devices offer 5V.
I've just received the little PCBs I ordered for the CPU user I/F for my EP2C5T144 Mini board. I received 11 boards, so I can make them available to anyone who wants one (free).
I did a search on Ale Propeller FPGA and came up with a forum post from 2009 that looks intriguing. Maybe such a hybrid needs to show how to do something that can't be done easily with the prop - eg a video driver with half a meg of sram.
Are most FPGAs in physical chips with those tiny pads that are close together? There are so many to choose from, and by limiting the choice to boards like the one at the beginning of this link that brings things out to 0.1" headers it would make the chips more accessable. Then I guess you have to look at price vs performance. I'm still dreaming of adding external video to a propeller but I'm also very open to doing the same thing with a FPGA.
The older Cyclone II on those low-cost boards has more performance than you are likely to need. A typical design should be capable of being clocked at over 250 MHz, but those cheap boards don't provide access to the PLL, so you are restricted to 50 MHz max. from the on-board oscillator.
So I ended up writing in a "Behavioural" description instead of a "Structural" - would a "Behavioural" description produces unoptimized logic circuitry?
I wonder how the IC designers planned their circuits before they gonna fabricate them in HDL. Unfortunately, I do not know anyone who worked in any customised IC sector.
Tor: For begineers, get a board with the peripherals like VGA port and SDRAM. You may spend less time wiring them and more time to concentrate on the development of the HDL.
Have a look at the pictures in this document to see how the Motorola 6809 was designed back in the 70's:
http://www.google.com/url?sa=t&source=web&cd=2&ved=0CCEQFjAB&url=http%3A%2F%2Fretro.co.za%2F6809%2Fdocuments%2FByte_6809_Articles.pdf&rct=j&q=motorola%206809%20design%20philosopy&ei=R-M3TrDCD8aQswbzhpQD&usg=AFQjCNHQxRRwsGPTXxRVuP-GV_j2PGkTUA&sig2=Y16tGgqkPflDtTHBeaItow&cad=rja