Open Propeller Project #6: Open Source Verilog for Propeller 1

Ken GraceyKen Gracey Posts: 6,530
edited 2014-08-16 - 23:06:30 in Propeller 1
OPP-Verilog.png


Parallax has released the Verilog code used to design the Propeller 1 (P8X32A) Multicore Microcontroller. Please use this thread for ongoing discussion, sharing code and FPGA variants around this Open Propeller Project.

Start right here please: http://www.parallax.com/microcontrollers/propeller-1-open-source

As we see some initial use of the Verilog we will likely rally behind some efforts, possibly developing a new Propeller chip from contributor efforts.

This post will be revised as a place to put new file downloads created by the community, if desired.

Ken Gracey
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Comments

  • David BetzDavid Betz Posts: 13,592
    edited 2014-08-06 - 13:12:09
    Wow! This is fabulous news! Thanks Parallax!!
  • DL7PNPDL7PNP Posts: 18
    edited 2014-08-06 - 13:17:19
    Awesome, I know why you are my favorite company!
    Thanks Parallax!
  • Roy ElthamRoy Eltham Posts: 2,684
    edited 2014-08-06 - 13:18:36
    This is very cool! Now I wish I was more familiar with Verilog so that I could really play with this properly...
    Of course, I'm so busy with so much stuff right now that I doubt I could find time for anything. So, I'm looking forward to what you all do with this!
  • BaggersBaggers Posts: 2,965
    edited 2014-08-06 - 13:23:51
    This is awesome Ken, Chip, hats off to you both for taking this move, I really hope it helps gets parallax on the map where it belongs :)

    Time to forget what VHDL I know, and replace it with Verilog haha
  • ColeyColey Posts: 968
    edited 2014-08-06 - 13:23:57
    Amazing, this opens up so many possibilities, thanks Parallax.
    If this doesn't inject some impetus and innovation into the Propeller scene then nothing will :D
  • Cluso99Cluso99 Posts: 15,548
    edited 2014-08-06 - 13:26:19
    Congratulations Parallax!

    What a fantastic opportunity to not only be able to run the Propeller code on an FPGA, but to be able to learn and understand the workings, and then modify it as well.

    To new folks reading this thread...

    A number of us have been fortunate enoughto have been able to take part in testing a new version of the Propeller chip, commonly referred to here as the P2. This is open to everyone who has the right FPGA board(s). As a community we have learnt so much from this.

    Please show your support to Parallax by purchasing your FPGA board(s) from Parallax.


    ll.
    My Prop boards: P8XBlade2 , RamBlade , CpuBlade , TriBlade
    P1 Prop OS (also see Sphinx, PropDos, PropCmd, Spinix)
    Website: www.clusos.com
    P1: Tools (Index) , Emulators (Index) , ZiCog (Z80)
    P2: Tools & Code , Tricks & Traps
  • mindrobotsmindrobots Posts: 6,506
    edited 2014-08-06 - 13:27:11
    Thanks, Parallax!

    What an exciting opportunity to learn microcontroller design at this level with an architecture you are already familiar with. This is a bold move and a truly exciting announcement!
    MOV OUTA, PEACE <div>Rick </div><div>"I've stopped using programming languages with Garbage Collection, they keep deleting my source code!!"</div>
  • KeithEKeithE Posts: 955
    edited 2014-08-06 - 13:33:58
    Looking ahead, you might want to consider changes to http://forums.parallax.com/misc.php?do=showrules in case people want to post Verilog code under the GPLv3 license. Or maybe you'll have a separate area for that?

    It will be interesting to see what people do with this.
  • Bill HenningBill Henning Posts: 6,445
    edited 2014-08-06 - 13:45:31
    Congratulations Parallax!

    I hope this move brings you a lot of customers, as it is a very forward thinking move.

    I find it encoraging that it uses only ~15K LE out of 22K on a DE0-Nano, making it easy to try all sorts of Prop1-variants.
    www.mikronauts.com / E-mail: mikronauts _at_ gmail _dot_ com / @Mikronauts on Twitter
    RoboPi: The most advanced Robot controller for the Raspberry Pi (Propeller based)
  • ColeyColey Posts: 968
    edited 2014-08-06 - 13:47:06
    From the other thread....
    [QUOTE=mark
  • potatoheadpotatohead Posts: 9,915
    edited 2014-08-06 - 13:49:45
    Thank You.

    I came back to this stuff after a long detour in mechanical engineering and manufacturing. Chip, Ken, the Propeller and this great community, filled with smart friends has been an outstanding learning experience!

    Now Parallax is taking us all right to the edge!

    Here's to many happy days ahead!

    You guys are awesome, that is all.
    Do not taunt Happy Fun Ball! @opengeekorg ---> Be Excellent To One Another SKYPE = acuity_doug
  • jmgjmg Posts: 14,141
    edited 2014-08-06 - 13:54:18
    Roy Eltham wrote: »
    This is very cool! Now I wish I was more familiar with Verilog so that I could really play with this properly...
    Verilog is not so hard to anyone used to embedded programming and hardware.
    Especially not hard, if you have a starting framework.
  • Bill HenningBill Henning Posts: 6,445
    edited 2014-08-06 - 13:56:46
    Sent...
    Coley wrote: »
    From the other thread....


    I just did this too, the more people do this the more likely Hackaday will take some notice of it....

    send your 'tip' to tips@hackaday.com
    www.mikronauts.com / E-mail: mikronauts _at_ gmail _dot_ com / @Mikronauts on Twitter
    RoboPi: The most advanced Robot controller for the Raspberry Pi (Propeller based)
  • jmgjmg Posts: 14,141
    edited 2014-08-06 - 14:06:11
    cgracey wrote: »
    The entire P1 fits into 2/3 of the DE0-Nano's logic fabric. I had to eliminate the character ROM that sits between $8000..$BFFF, though, to make it fit the DE0-Nano's memory. There's room to grow the logic by 50%!

    So this is really a P1- on the DE0-Nano, which means any P1 code that expects the character ROM, will not work.

    Is the character ROM there as a conditional compile switch ?

    Looks like a matrix / table of what is in, and out, on various FPGA targets is needed.
  • Bob Lawrence (VE1RLL)Bob Lawrence (VE1RLL) Posts: 1,550
    edited 2014-08-06 - 14:16:11
    @Ken Gracey

    Elektor Magazine has been informed. They also run Circuit Cellar.
  • jazzedjazzed Posts: 11,803
    edited 2014-08-06 - 14:24:11
    jmg wrote: »
    So this is really a P1- on the DE0-Nano, which means any P1 code that expects the character ROM, will not work.

    They are aware of that ;-) Hopefully, it does not become painfully aware.

    jmg wrote: »
    Is the character ROM there as a conditional compile switch ?

    Surely all the ROM can be turned off. Then with a small boot section (for maybe a different, non-deterministic loader state machine in verilog), all that saved space if any could be opened to more program code.

    jmg wrote: »
    Looks like a matrix / table of what is in, and out, on various FPGA targets is needed.

    Yes. And a link to the code ;-)


    Hopefully Parallax can make some money on DE0 Nano sales and other board.

    Exciting times ahead indeed.
  • jmgjmg Posts: 14,141
    edited 2014-08-06 - 14:36:49
    jazzed wrote: »
    Surely all the ROM can be turned off. Then with a small boot section (for maybe a different, non-deterministic loader state machine in verilog), all that saved space if any could be opened to more program code.

    That would be the best approach, a few conditionals to allow selective scaling of the ROM.
    ROM should compile into block RAM, so will have less logic impact, but that assumes the block RAM is there and spare. (ie above the 32K needed for a ==P1)

    eg the BEMicro CV I think has 220KB of RAM, so it can do all of the RAM+ROM of P1 and even extend to any mix of 220KB (within any address limits)
    jazzed wrote: »
    Yes. And a link to the code ;-)

    Of course, I would expect a number of target board builds/confirms to be done quite quickly, and they should all be linked, with info on what is in, and out.
  • Willy EkerslykeWilly Ekerslyke Posts: 29
    edited 2014-08-06 - 14:43:54
    You can find the necessary files in the download section. Just search Product Title for "DE0" :)
  • TubularTubular Posts: 3,802
    edited 2014-08-06 - 15:01:20
    This is simply amazing news, thanks Parallax. Time to get very busy

    Regarding the ROM i wonder if there could be enough room for say 48 characters, A-Z uppercase, 0-9 and some punctuation, with a mapping built into the verilog to select the appropriate match

    The other thing to implement asap is the port B, bringing up 64 i/o
  • David BetzDavid Betz Posts: 13,592
    edited 2014-08-06 - 15:07:10
    jazzed wrote: »
    Surely all the ROM can be turned off. Then with a small boot section (for maybe a different, non-deterministic loader state machine in verilog), all that saved space if any could be opened to more program code.
    My reading of Chip's message is that there isn't enough on-chip RAM on the DE0-Nano for the full ROM. If there isn't enough room for the full ROM, I doubt there is enough room to fill that same address space with RAM. I wonder if we could come up with an interface to an external SRAM chip for hub memory? How about that as the first Verilog project? :-)
  • jazzedjazzed Posts: 11,803
    edited 2014-08-06 - 15:07:40
    You can find the necessary files in the download section. Just search Product Title for "DE0" :)


    Thanks. Just to be clear, it's here: http://www.parallax.com/downloads/setup-propeller-1-design-de0-nano
  • cgraceycgracey Posts: 11,950
    edited 2014-08-06 - 15:10:00
    Tubular wrote: »
    This is simply amazing news, thanks Parallax. Time to get very busy

    Regarding the ROM i wonder if there could be enough room for say 48 characters, A-Z uppercase, 0-9 and some punctuation, with a mapping built into the verilog to select the appropriate match

    The other thing to implement asap is the port B, bringing up 64 i/o


    Right now, one line of Verilog gets commented out to eliminate the character ROM from the DE0-Nano compile, in order to make it fit. I tried doing the first half of the character ROM (characters $00..$7F), but there wasn't even room for that.

    The BEMicro CV board is really chip and has plenty of RAM to spare, as well as logic. All one would have to do is make a unique top.qsf file for that board, and compile it with the other files, and they'd be running.

    I think many of you will be kind of surprised at how little Verilog code it takes to make a Propeller 1 chip. The cog.v source file is only 4KB, for example.
  • jazzedjazzed Posts: 11,803
    edited 2014-08-06 - 15:10:02
    David Betz wrote: »
    My reading of Chip's message is that there isn't enough on-chip RAM on the DE0-Nano for the full ROM. If there isn't enough room for the full ROM, I doubt there is enough room to fill that same address space with RAM.


    I thought the ROM was set into RAM space as discussed elsewhere. Could be wrong of course.

    Tubular, yes! Port B!
  • David BetzDavid Betz Posts: 13,592
    edited 2014-08-06 - 15:12:21
    jazzed wrote: »
    I thought the ROM was set into RAM space as discussed elsewhere. Could be wrong of course.

    Tubular, yes! Port B!
    It might be but even so there wasn't enough for the full 32k of ROM so probably not enough for 64k of RAM either.
  • jazzedjazzed Posts: 11,803
    edited 2014-08-06 - 15:17:15
    David Betz wrote: »
    It might be but even so there wasn't enough for the full 32k of ROM so probably not enough for 64k of RAM either.

    So 48KB of HUB RAM is not interesting?

    IIRC, the ROM area is half full of tables and other code that may or may not get used on a custom design.

    Well anyway, there are other FPGAs out there that are big enough to add significantly more value.
  • David BetzDavid Betz Posts: 13,592
    edited 2014-08-06 - 15:20:05
    jazzed wrote: »
    So 48KB of HUB RAM is not interesting?

    IIRC, the ROM area is half full of tables and other code that may or may not get used on a custom design.

    Well anyway, there are other FPGAs out there that are big enough to add significantly more value.
    Yes, it is. I thought you were suggesting to fill the ROM address space with RAM and to then load the ROM font dynamically. If you just want more program space then 48k would be very nice!
  • Ken GraceyKen Gracey Posts: 6,530
    edited 2014-08-06 - 15:21:16
    The first post has been updated with the correct entry page link.

    Ken Gracey
  • jazzedjazzed Posts: 11,803
    edited 2014-08-06 - 15:24:00
    Yay!

    Good job Parallax.

    Ken Gracey wrote: »
    OPP-Verilog.png


    Parallax has released the Verilog code used to design the Propeller 1 (P8X32A) Multicore Microcontroller. Please use this thread for ongoing discussion, sharing code and FPGA variants around this Open Propeller Project.

    Start right here please: http://www.parallax.com/microcontrollers/propeller-1-open-source

    As we see some initial use of the Verilog we will likely rally behind some efforts, possibly developing a new Propeller chip from contributor efforts.

    This post will be revised as a place to put new file downloads created by the community, if desired.

    Ken Gracey
  • Bob Lawrence (VE1RLL)Bob Lawrence (VE1RLL) Posts: 1,550
    edited 2014-08-06 - 15:28:30
    re:The first post has been updated with the correct entry page link.

    The downloaded worked fine and the package unzipped all ok. :cool: 60050-60056-Propeller-1-Design-2014-08-06 .
  • TubularTubular Posts: 3,802
    edited 2014-08-06 - 15:30:01
    The other thing is, we should be able to implement JTAG debug now, shouldn't we?
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