The Prop manual used to have a nice simple 3 transistor RS232 programming circuit, and also any other usb/ttl plug that supports DTR or RTS will work, often with just one small ceramic cap (as I recall)
One question: I have DE2-115 but no Propplug and no possibility to get it fast. Is it possible to use any available rs232 to usb dongle with circuit like this:
I had an account, but resetting a password takes about as much time as it does to just get an account rocking.
Mark Heater's Repository as one I watch.
Load the GitHub for Windows thing, just because it's new, and I don't have anything like that on this computer.
Hit the "Clone To Desktop" button, seen on the Repository page.
GitHub for Windows asks me for a folder, and it already created .../Documents/GitHub so I added one with the repository name
OK.
One minute later, my machine contains exactly what Heater had done. If he updates somehow, in another small amount of time, I can have the same. Should we want to work on something, invites are passed around, and we do that. Or not. Maybe I'll just clone it and do my own thing, whatever.
There is an RS232 in DE2-115. I managed to convert the Propeller FPGA project to a symbol file, so now I can try to connect the Propeller to this port. I started another thread with a detailed question about it.
I will try this as soon as I can find an RS232 cable in all my electronic parts trash.
The Prop manual used to have a nice simple 3 transistor RS232 programming circuit, and also any other usb/ttl plug that supports DTR or RTS will work, often with just one small ceramic cap (as I recall)
I wonder if an fpga guru could do some magic to include sdram support within the existing framework...
Maybe the last 2 longs of cog ram could be used for sdram access.
one to specify address to read or write from, one to specify desired action or something like that...
There is possibility to add sdram support. I expreimented with it on DE2-115.There is a controller available, which can read and write from SDRAM by put a data and then trigger writing.Or trigger reading, then read data.
There is also 2 MB of fast SRAM available on DE2-115. Accessing this will be simpler than SDRAM.
The problem is only lack of pins, but now we can try to activate PortB.
I found that with a lot of Chip's code - no reason it shouldn't be in the Verilog sources too. It may need to be processed into a more friendly format before going to a public repo. (How is he with CR/LF? I'm guessing Windows style here too?)
This tab thing should certainly be fixed before going into any repo. Use spaces instead. And yes fix those line endings as well.
If people start tinkering with this they are going to get into a mess with those tabs. They will fix them up to their liking. That will make doing diffs between different peoples different versions harder. That makes collaboration a pain.
Is there some kind of style guide for Verilog? Perhaps there should be for this code base?
I'm a complete newbie to the git world. In the past when I found a repository that I liked, I just used the "Download Zip" button on github and moved it where I wanted. If a new version became available, I downloaded it and replaced my original. It still isn't clear to me how to work on my code changes and then retain my changes while incorporating changes from the repository. But then, I don't know how to use a makefile, either:)
Perhaps Heater's repository should be named... "the Unofficial Parallax P8X32A_Emulation" and blessed by Ken. After the P2 is released, then maybe Parallax could make an official repository, where we could all follow along.
Rich
I just forked Heater (), then cloned that fork to my laptop. The only reason I forked him first was so I could use my private repo on github between different computers. I often moved from my laptop (Win7) to my main desktop (OSX) to my other laptop (Linux). If I'm working on something, I can push it to Github to save it and then pull it down to the local repo on one of the other systems. It might be the wrong way to do it but it seems to work for me.
I'm uninstalling, downloading and reinstalling the latest Quartus - mine was old and mixed versions. If you are doing this, be prepared to spend a little bit of time waiting for downloads and installs - it is NOT quick!
Hopefully, someday soon when it is all complete, I'll be able to load up a P1 FPGA!
The downloads from Altera do take a smudge of time. But if you just want to get up and running, you just need the programmer, which can be downloaded separately. For the Nano, you load the .jic into the programmer by "add file" click the box in the edit window and you are off to the races.
The downloads from Altera do take a smudge of time. But if you just want to get up and running, you just need the programmer, which can be downloaded separately. For the Nano, you load the .jic into the programmer by "add file" click the box in the edit window and you are off to the races.
Yup! That's how I did all my P2 stuff but since we have the source for this, I wanted a full, fresh tool set to work with.
Ok... this is not a question for Chip... and it is a little premature, but I have noticed a defect in Heater's implementation of the Emulator.
There is no reset... A power cycle is required each time you want to program the Emulator. I notice that there are two little buttons on the Nano...what does it take to make one of them a reset button?
The Github repo is not "Heater's Emulator" (yet) it is the Parallax released version. There was mention of this earlier in one of the threads that the reset does not work and you need to cycle power.
Ok... this is not a question for Chip... and it is a little premature, but I have noticed a defect in Heater's implementation of the Emulator.
There is no reset... A power cycle is required each time you want to program the Emulator. I notice that there are two little buttons on the Nano...what does it take to make one of them a reset button?
Thanks
Rich
There is a reset pin that the PropPlug attaches to. To add a reset button, enter the pin name and location into the top.qsf file, then incorporate it into the top.tdf AHDL file (an Altera language which uses different operators than Verilog).
Power cycling is required to load a new FPGA configuration, but downloading to the emulated P8X32A should not require anything but a reset via the PropPlug.
This tab thing should certainly be fixed before going into any repo. Use spaces instead. And yes fix those line endings as well.
If people start tinkering with this they are going to get into a mess with those tabs. They will fix them up to their liking. That will make doing diffs between different peoples different versions harder. That makes collaboration a pain.
Is there some kind of style guide for Verilog? Perhaps there should be for this code base?
With SPIN, stuff gets compartmentalized some, for example. Often, we really can just run with something, ignore the ugly, and it works. People then do what they feel good about doing. Suddenly, there is a code base where that is far less likely to be true...
Interesting and educational times ahead in Parallax land, it seems. Bring it!
To add a reset button, enter the pin name and location into the top.qsf file, then incorporate it into the top.tdf AHDL file (an Altera language which uses different operators than Verilog).
Or do what I did. Convert AHDL to BDF. Then you have a block with Prop inside and RESn input which you can connect to anything you have on your board.
The minute Heater changed those tabs... it became his;) I would like to add that while Heater was changing all of those tabs... one at a time, I was trying to find a way to automate it for him.
I failed.
Chip,
When we need you, we will ask for you;)
But seriously, THANK YOU. I am outa time today, maybe over the weekend.
You and everyone around you are a true delight, miles of smiles.
And there is "center of gravity" in action. When I participate, I'll use GitHub. No question. After my positive GCC experience, there really wasn't one. Not like I haven't used the tools before. I did in the past, earlier ones not as good, or fairly current ones over command line on much smaller code bodies. This isn't the beast GCC is, but it's big enough and touchy enough to warrant the data management and revision controls.
Maybe it makes sense at some point to stuff a simpler data set into GitHub, and have it be other things, like pictures, zip files, packages, code, text, data. Then step through some scenarios. My experience with the similar PDM (product data management) tools and larger electro-mechanical engineering data sets, is people balk, until they have a good experience. And for that to happen, they need to see it play out a time or two.
Not everybody. Some will just jump in, and others will read the documentation or go through tutorials. But a lot of people, particularly when they have a "local" style working for them, will just need to map it all in their head before it seems worth it.
OK I just found out where my Deo-Nano board was hiding and will see how long it takes to follow the instructions to load the Prob 1 image and get it working. I do have experience with Prop 2 and the Deo-Nano board so it shouldn't be so bad. So for the first step - download the instructions. LOL 2:34
Edit - Update: It's running 2:44 . No problems everything just worked . :cool: The hardest part was finding my camera app on my Tablet so I could take a picture. LOL
Hardware design (Verilog) is above my knowledge...however, someone needs to make a BEMicro CV (nice price) P1, with more speed, more COGS, more hub memory, 16 to 32 bit VGA, and hubexec...that would rock.
Comments
I had an account, but resetting a password takes about as much time as it does to just get an account rocking.
Mark Heater's Repository as one I watch.
Load the GitHub for Windows thing, just because it's new, and I don't have anything like that on this computer.
Hit the "Clone To Desktop" button, seen on the Repository page.
GitHub for Windows asks me for a folder, and it already created .../Documents/GitHub so I added one with the repository name
OK.
One minute later, my machine contains exactly what Heater had done. If he updates somehow, in another small amount of time, I can have the same. Should we want to work on something, invites are passed around, and we do that. Or not. Maybe I'll just clone it and do my own thing, whatever.
I spent 5 minutes on this.
I will try this as soon as I can find an RS232 cable in all my electronic parts trash.
Maybe the last 2 longs of cog ram could be used for sdram access.
one to specify address to read or write from, one to specify desired action or something like that...
There is also 2 MB of fast SRAM available on DE2-115. Accessing this will be simpler than SDRAM.
The problem is only lack of pins, but now we can try to activate PortB.
For example the cog.v file here https://github.com/ZiCog/P8X32A_Emulation/blob/master/P8X32A_DE0_Nano/cog.v
It's a mess in my editors locally also.
I hate having to dick around with tab settings all the time to get every file I look at to present itself correctly.
If people start tinkering with this they are going to get into a mess with those tabs. They will fix them up to their liking. That will make doing diffs between different peoples different versions harder. That makes collaboration a pain.
Is there some kind of style guide for Verilog? Perhaps there should be for this code base?
For example that Smile does not work as code snippets in this forum, not the tabs or the line endings:
// register ram wire ram_ena = m[0] || m[1] || m[2] || m[3] && cond && i[wr]; wire ram_w = m[3] && alu_wr; wire [8:0] ram_a = m[2] ? px : m[0] ? i[sh:sl] : i[dh:dl]; wire [31:0] ram_q; cog_ram cog_ram_ ( .clk (clk_cog), .ena (ram_ena), .w (ram_w), .a (ram_a), .d (alu_r), .q (ram_q) );https://github.com/NetFPGA/netfpga/wiki/VerilogCodingGuidelines
// register ram wire ram_ena = m[0] || m[1] || m[2] || m[3] && cond && i[wr]; wire ram_w = m[3] && alu_wr; wire [8:0] ram_a = m[2] ? px : m[0] ? i[sh:sl] : i[dh:dl]; wire [31:0] ram_q; cog_ram cog_ram_ ( .clk (clk_cog), .ena (ram_ena), .w (ram_w), .a (ram_a), .d (alu_r), .q (ram_q) );In the "terminal", you just cd into the folder you want the repository to reside in and then execute this:
git clone https://github.com/ZiCog/P8X32A_Emulation.git
I'm a complete newbie to the git world. In the past when I found a repository that I liked, I just used the "Download Zip" button on github and moved it where I wanted. If a new version became available, I downloaded it and replaced my original. It still isn't clear to me how to work on my code changes and then retain my changes while incorporating changes from the repository. But then, I don't know how to use a makefile, either:)
Perhaps Heater's repository should be named... "the Unofficial Parallax P8X32A_Emulation" and blessed by Ken. After the P2 is released, then maybe Parallax could make an official repository, where we could all follow along.
Rich
That is faster than Ebola... (too soon?)
Rich
I'm uninstalling, downloading and reinstalling the latest Quartus - mine was old and mixed versions. If you are doing this, be prepared to spend a little bit of time waiting for downloads and installs - it is NOT quick!
Hopefully, someday soon when it is all complete, I'll be able to load up a P1 FPGA!
Yup! That's how I did all my P2 stuff but since we have the source for this, I wanted a full, fresh tool set to work with.
There is no reset... A power cycle is required each time you want to program the Emulator. I notice that there are two little buttons on the Nano...what does it take to make one of them a reset button?
Thanks
Rich
There is a reset pin that the PropPlug attaches to. To add a reset button, enter the pin name and location into the top.qsf file, then incorporate it into the top.tdf AHDL file (an Altera language which uses different operators than Verilog).
Power cycling is required to load a new FPGA configuration, but downloading to the emulated P8X32A should not require anything but a reset via the PropPlug.
Now you all know why I despise tabs.
With SPIN, stuff gets compartmentalized some, for example. Often, we really can just run with something, ignore the ugly, and it works. People then do what they feel good about doing. Suddenly, there is a code base where that is far less likely to be true...
Interesting and educational times ahead in Parallax land, it seems.
Or do what I did. Convert AHDL to BDF. Then you have a block with Prop inside and RESn input which you can connect to anything you have on your board.
The minute Heater changed those tabs... it became his;) I would like to add that while Heater was changing all of those tabs... one at a time, I was trying to find a way to automate it for him.
I failed.
Chip,
When we need you, we will ask for you;)
But seriously, THANK YOU. I am outa time today, maybe over the weekend.
You and everyone around you are a true delight, miles of smiles.
Rich
Now, it looks like it's time to hook up an EEPROM so I can F11!
This could be more fun than we're allowed to have!!!
Thanks Heater.
I'm itching to get into this, but have so many other things to do. At least by the time I'm ready I know you have a reasonable opensource repository.
Maybe it makes sense at some point to stuff a simpler data set into GitHub, and have it be other things, like pictures, zip files, packages, code, text, data. Then step through some scenarios. My experience with the similar PDM (product data management) tools and larger electro-mechanical engineering data sets, is people balk, until they have a good experience. And for that to happen, they need to see it play out a time or two.
Not everybody. Some will just jump in, and others will read the documentation or go through tutorials. But a lot of people, particularly when they have a "local" style working for them, will just need to map it all in their head before it seems worth it.
IMHO, of course.
Edit - Update: It's running 2:44 . No problems everything just worked . :cool: The hardest part was finding my camera app on my Tablet so I could take a picture. LOL
Hardware design (Verilog) is above my knowledge...however, someone needs to make a BEMicro CV (nice price) P1, with more speed, more COGS, more hub memory, 16 to 32 bit VGA, and hubexec...that would rock.