For sure that is not "my implementation" of anything. It's only a copy of what has been offered. I have not had time to even try it out myself yet!
Jazzed,
Now you all know why I despise tabs.
Good on you.
You would think that in a world where people use white space for semantics in their programming language (Spin) they would have figured this out years ago.
rjo__
The minute Heater changed those tabs... it became his..
Oh all right. It's mine, it's all mine...mine I tell you....
I would like to add that while Heater was changing all of those tabs... one at a time, I was trying to find a way to automate it for him.
Do be serious. Do you really think I was replacing those tabs one at a time by hand?!!
Thing is you cannot simply use sed or whatever to replace tabs with four spaces. That screws everything up. You have to be a bit smarter:)
That Hackaday page really under plays the magnitude of this.
"Parallax has embraced open source hardware by...."
No, what they have done is put a bomb under the Open Source Hardware movement. Exposing it for the sham it is.
As the AdaFruit guys pointed out, Open Source Hardware is a myth. Sure, like the Arduino and such the schematics of the board are open, and even the board design files are open. But it uses an AVR micro-controller that is anything but open source. Any monkey can put that AVR on a PCB, you don't even need the PCB to use those AVRs.
BUT, with the release of the P1 design files we witness the first time in history that is possible to even actually have an open source hardware design based on a processor in current production.
Everything from the application software, to the processor it runs on, to the board schematic and layout can now be truly open.
You can really take that total design and get it made, by Altera or Xylinx or as an ASIC or whatever you like.
Can/would someone compare the Altera Cyclone V 5CEBA2xxxC8N F484 with the Xilinx Spartan 6 XC6SLX25-2xxxxxxC for use as a P1 development ???
Both have BGA 256 and 484 pin versions and about 25K LUTs.
Distributed RAM seems similar at about 220KB
Block RAM needs further investigation - Altera quote 196 and Xilinx 52 but I think they are different bases - I need to look deeper.
Both support SDRAM.
Does anyone know about the FPGA software from both Altera and Xilinx - Are these chips supported with the free downloadable versions?
I took a long look at the Verilog code last night.
Think I understand what needs to be done to...
make the PC (program counter) 16+ bits
add a new CALL/JMP/RET instruction (using one of the 4 free instructions)
to include a 16-18 bit immediate absolute goto address
add PortB - ie 64 I/O
make 48KB hub ram with the top 16KB double mapped
But before I start I am going to download Quartus on my wife's faster laptop. Have to do the download at my son's since I have limited download data (mobile only).
So nothing is going to happen here for a few days at least.
Does anyone know about the FPGA software from both Altera and Xilinx - Are these chips supported with the free downloadable versions?
I am no guru, but I have been frantically reading all.day.long on what is available. From what I read the free Web version for the Altera supports all the V series except the top of the line -9 version.
I am looking at this board to play with...
Terasic DE1-SoC Board for $199.00
Cyclone V SoC 5CSEMA5F31C6 Device
Dual-core ARM Cortex-A9 (HPS)
85K Programmable Logic Elements
4,450 Kbits embedded memory
6 Fractional PLLs
2 Hard Memory Controllers
64MB (32Mx16) SDRAM on FPGA
1GB (2x256Mx16) DDR3 SDRAM on HPS
Micro SD Card Socket on HPS
Two Port USB 2.0 Host (ULPI interface with USB type A connector)
USB to UART (micro USB type B connector)
10/100/1000 Ethernet
PS/2 mouse/keyboard
IR Emitter/Receiver
Two 40-pin Expansion Headers
One 10-pin ADC Input Header
8 channel 12bit ADC
1280x1024 VGA (24bit)
One LTC connector (One Serial Peripheral Interface (SPI) Master ,one I2C and one GPIO interface )
and a lot more goodies to boot.
The ARM side can run Linux... Hmmm, Prop IDE running there? My Raspberry Pi does
I took a long look at the Verilog code last night.
Think I understand what needs to be done to...
make the PC (program counter) 16+ bits
add a new CALL/JMP/RET instruction (using one of the 4 free instructions)
to include a 16-18 bit immediate absolute goto address
add PortB - ie 64 I/O
make 48KB hub ram with the top 16KB double mapped
But before I start I am going to download Quartus on my wife's faster laptop. Have to do the download at my son's since I have limited download data (mobile only).
So nothing is going to happen here for a few days at least.
Again, we need a way to load 32 bit constants. That could be in the form of:
mov r1, #my_constant
rdlong r0, r1
...
my_constant long $12345678
However, that approach takes three longs, two for instructions and one for the constant itself where the AUGS solution takes only two longs.
Everything from the application software, to the processor it runs on, to the board schematic and layout can now be truly open.
Actually, no.
The FPGA tools are certainly NOT open, and the FPGAs themselves are NOT open, and most of the FPGA boards are NOT open.
All you have done, is move some hardware, into software. Open Source Hardware is still a myth.
However, semantics aside, this does have great educational and niche use potential.
Actually, no.
The FPGA tools are certainly NOT open, and the FPGAs themselves are NOT open, and most of the FPGA boards are NOT open.
All you have done, is move some hardware, into software. Open Source Hardware is still a myth.
However, semantics aside, this does have great educational and niche use potential.
I take a different view. The Propeller is open source, so any programs I write to run on it can be open source from top to bottom. If I want to make a derivative Propeller then it's no longer fully open source (since, as you pointed out, it runs on a closed source FPGA). But my Propeller chips themselves are now open.
And the more important bit here is that you know exactly what it's doing. And if you can't source a Prop Chip, you can emulate one, and or get it fabbed, whatever. Lots of options now, trusted ones.
Trusted by US. Not somebody else selling "trusted" things that only trust them. To some people, this is important.
And the more important bit here is that you know exactly what it's doing. And if you can't source a Prop Chip, you can emulate one, and or get it fabbed, whatever. Lots of options now, trusted ones.
Trusted by US. Not somebody else selling "trusted" things that only trust them. To some people, this is important.
Of course, fabbing the chip will require you to use proprietary libraries as well. There may be no way to get to the bottom of this. :-(
Again, we need a way to load 32 bit constants. That could be in the form of:
mov r1, #my_constant
rdlong r0, r1
...
my_constant long $12345678
However, that approach takes three longs, two for instructions and one for the constant itself where the AUGS solution takes only two longs.
David,
Could we get by with a 16 bit constant (for 64KB hub) which could be expanded to an 18bit constant for 256KB hub?
Why? Well we have 4 unused P1 instructions plus the ability to expand the SYSOP instruction while totally keeping backward compatibility.
So, one will be the CALL/JMP/RET with 16-18 bit constant (absolute address) - I am thinking just using the D&S bits gives us 18 bits. Using KISS means that the lowest 2 bits will always be 00.
BTW The way Chip has coded the P1, he keeps the instruction set completely regular. So you have to be careful if we try to use the zcri or cccc bits for anything other purpose.
So, CALL/JMP/RET will use a fixed register $1EF (or later maybe $1EC-1EF by using the lower 2 bits of S).
BTW this is already complex enough because we have to add wait states for the hub access, and this is going to cause possible delays in the completion of the previous instructions writeback.
For the constant, which is better...
LOAD #16-18_bit_address 'loads 16 bits into fixed register, say $1EE, zeroing the upper bits
or
RDLONGX #16-18_bit_address 'loads 32 bits from address into fixed register, say $1EE
The second one is much more difficult as there is wait states to take care of.
One needs to be some form of load address, so maybe the same as the CALL format using D&S for 16-18 bits.
Everything from the application software, to the processor it runs on, to the board schematic and layout can now be truly open.
Actually, no.
The FPGA tools are certainly NOT open, and the FPGAs themselves are NOT open, and most of the FPGA boards are NOT open.
All you have done, is move some hardware, into software. Open Source Hardware is still a myth.
However, semantics aside, this does have great educational and niche use potential.
With these semantics, even Linux is not open sourced because it only runs on closed sourced chips.
So, the only truly open sourced chip is the propeller chip. Anything else on the pcb is proprietary. That means the regulator, the eeprom (or the chip involved in downloading and the device which did the downloading), and even the capacitors on the boards.
And stretching this even further, the factories that make chips are closed source - you cannot make the chips yourself.
David: At least making the transistors yourself is possible. But I don't think I would like to be doing that many
Let's get past the myth, and just appreciate what Parallax has done, and get back on topic please
I read through the first 60 odd comments in reply to Potaohead's story and I don't think I found one that was factually correct or had the slightest idea what they were talking about.
Slashdot is a faint shadow of it's former glory, such as it was, back in the late 1990's when nerdy geeks would bicker about technical stuff that they at least had some knowledge of.
Slashdot today at least dares not display it's old catch phrase "News for nerds, stuff that matters".
Now a days I think of it more as "Spews and turds, stuff that splatters".
Actually, no.
The FPGA tools are certainly NOT open, and the FPGAs themselves are NOT open, and most of the FPGA boards are NOT open. All you have done, is move some hardware, into software. Open Source Hardware is still a myth.
Actually yes.
When I publish my C code it is open source. No matter if there exists an open source C compiler to make it into executables or not. You are free to do with it what you like. Compile it how you like. Run it on whatever machine you like.
In the worst case you would have to translate my C into assembler manually, you know, with a pencil and paper. Perhaps you would then have to translate that assembler into HEX or binary manually. Then you have a program you can load into your machine and run. A machine, by the way, that I may never have heard of when I wrote my C code.
Similarly that Verilog is a description of a machine, a Propeller MCU. It is not dependant on Altera or FPGAs at all. You could use Xylinx tools and devices. You could get your own ASIC or whatever silicon made. With a bit of sweat you could manually translate that Verilog into a circuit diagram, using pencil and paper, for a circuit built out of 74 series logic chips or discrete transistors or even vacuum tubes!
The fact that the platform presented to implement that Verilog on is a closed FPGA from Altera does not detract from the openness of the Verilog.
With these semantics, even Linux is not open sourced because it only runs on closed sourced chips.
Except that is not true. Linux runs on OpenRISC an open source processor design you will find on opencores.org.
You are right about the semantics.
My source code can be open source even if there is no compiler yet written that can compile it or no hardware that can run it.
If you think that is crazy remember Ada Lovelace was writing code for a machine Babbage never managed to build!
The point about being open is that he user can see it, change it, rearrange it, share it. The details of how it might actually get built is irrelevant and is up to the user.
What we need is to put the OpenRisc CPU and the Propeller into the same FPGA or whatever chip.
Then we have that mythical beast of a computer capable of running a full up Linux OS coupled to a Propeller for handling those fiddly real time interfacing tasks.
David,
Could we get by with a 16 bit constant (for 64KB hub) which could be expanded to an 18bit constant for 256KB hub?
Why? Well we have 4 unused P1 instructions plus the ability to expand the SYSOP instruction while totally keeping backward compatibility.
So, one will be the CALL/JMP/RET with 16-18 bit constant (absolute address) - I am thinking just using the D&S bits gives us 18 bits. Using KISS means that the lowest 2 bits will always be 00.
BTW The way Chip has coded the P1, he keeps the instruction set completely regular. So you have to be careful if we try to use the zcri or cccc bits for anything other purpose.
So, CALL/JMP/RET will use a fixed register $1EF (or later maybe $1EC-1EF by using the lower 2 bits of S).
BTW this is already complex enough because we have to add wait states for the hub access, and this is going to cause possible delays in the completion of the previous instructions writeback.
For the constant, which is better...
LOAD #16-18_bit_address 'loads 16 bits into fixed register, say $1EE, zeroing the upper bits
or
RDLONGX #16-18_bit_address 'loads 32 bits from address into fixed register, say $1EE
The second one is much more difficult as there is wait states to take care of.
One needs to be some form of load address, so maybe the same as the CALL format using D&S for 16-18 bits.
RDLONGX would generate denser code since it wouldn't need to be followed by a RDLONG. It's too bad it would have to load to a fixed address though. What about a limited version of AUGS that just added 9 bits to the existing 9 bits in the S field of the next instruction? Then you could load any register?
When I publish my C code it is open source. No matter if there exists an open source C compiler to make it into executables or not. You are free to do with it what you like. Compile it how you like. Run it on whatever machine you like.
Agreed, But you were talking about open source hardware. not software.
The fact that the platform presented to implement that Verilog on is a closed FPGA from Altera does not detract from the openness of the Verilog.
We actually agree.
The Software source code is open source, the hardware (and the software needed to RUN that HW) is not.
So best limit the discussions to "the openness of the Verilog." and not try to claim open source hardware pathways..
RDLONGX would generate denser code since it wouldn't need to be followed by a RDLONG. It's too bad it would have to load to a fixed address though. What about a limited version of AUGS that just added 9 bits to the existing 9 bits in the S field of the next instruction? Then you could load any register?
The way its currently coded, this is a lot of work for me. At least for now, I want to keep any changes very simple.
I think the load will be the simplest to start off with, rather than call/jmp/ret.
Interesting results from Chip ["It turns out that even though this Cyclone V -A2 part has 25k LE's, the P8X32A takes 85% of them! That's 33% more LE's than it takes on the Cyclone IV. Plus, it took 3x longer to compile. Oh, and Fmax is still over 80MHz, but slower than Cyclone IV. Only good thing is, these Cyclone V FPGA's cost half what the Cyclone IV devices cost in similar (higher) densities."]
The way its currently coded, this is a lot of work for me. At least for now, I want to keep any changes very simple.
I think the load will be the simplest to start off with, rather than call/jmp/ret.
ozpropdev, added.
I suppose it isn't such a big deal that the constant always gets loaded into the same location since the LOAD# instruction will likely always be followed by a RDxxxx, WRxxxx, JMP, or CALL indirect through that location.
I totally agree that the design and workings of an FPGA from Altera are closed technology. As are the synthesis tools they offer.
That verilog though is independent of that.
The mere fact that one can switch from Altera to Xylinx to ASIC to whatever full chip design and no longer be dependent on Parallax emphasises the point.
I'm in Brazil, not in Australia, but Verical is announcing the BeMicro CV at a substantial discount price, ~US$ 35,xx. Leon had pointed this out in another thread:
Since they sell it in numbers departing from two units, it can be a good chance for a group buy!
Sad I'm in Brazil, but my youngest daughter lives in Sidney! Perhaps she wants to find a good gift for a distant living daddy!
Comments
Go and flood the comments with useful information!
For sure that is not "my implementation" of anything. It's only a copy of what has been offered. I have not had time to even try it out myself yet!
Jazzed, Good on you.
You would think that in a world where people use white space for semantics in their programming language (Spin) they would have figured this out years ago.
rjo__ Oh all right. It's mine, it's all mine...mine I tell you.... Do be serious. Do you really think I was replacing those tabs one at a time by hand?!!
Thing is you cannot simply use sed or whatever to replace tabs with four spaces. That screws everything up. You have to be a bit smarter:)
"Parallax has embraced open source hardware by...."
No, what they have done is put a bomb under the Open Source Hardware movement. Exposing it for the sham it is.
As the AdaFruit guys pointed out, Open Source Hardware is a myth. Sure, like the Arduino and such the schematics of the board are open, and even the board design files are open. But it uses an AVR micro-controller that is anything but open source. Any monkey can put that AVR on a PCB, you don't even need the PCB to use those AVRs.
BUT, with the release of the P1 design files we witness the first time in history that is possible to even actually have an open source hardware design based on a processor in current production.
Everything from the application software, to the processor it runs on, to the board schematic and layout can now be truly open.
You can really take that total design and get it made, by Altera or Xylinx or as an ASIC or whatever you like.
This, I believe, is a world first.
Can/would someone compare the Altera Cyclone V 5CEBA2xxxC8N F484 with the Xilinx Spartan 6 XC6SLX25-2xxxxxxC for use as a P1 development ???
Both have BGA 256 and 484 pin versions and about 25K LUTs.
Distributed RAM seems similar at about 220KB
Block RAM needs further investigation - Altera quote 196 and Xilinx 52 but I think they are different bases - I need to look deeper.
Both support SDRAM.
Does anyone know about the FPGA software from both Altera and Xilinx - Are these chips supported with the free downloadable versions?
Think I understand what needs to be done to...
- make the PC (program counter) 16+ bits
- add a new CALL/JMP/RET instruction (using one of the 4 free instructions)
- to include a 16-18 bit immediate absolute goto address
- add PortB - ie 64 I/O
- make 48KB hub ram with the top 16KB double mapped
But before I start I am going to download Quartus on my wife's faster laptop. Have to do the download at my son's since I have limited download data (mobile only).So nothing is going to happen here for a few days at least.
I am no guru, but I have been frantically reading all.day.long on what is available. From what I read the free Web version for the Altera supports all the V series except the top of the line -9 version.
I am looking at this board to play with...
Terasic DE1-SoC Board for $199.00
- Two Port USB 2.0 Host (ULPI interface with USB type A connector)
- USB to UART (micro USB type B connector)
- 10/100/1000 Ethernet
- PS/2 mouse/keyboard
- IR Emitter/Receiver
- Two 40-pin Expansion Headers
- One 10-pin ADC Input Header
- 8 channel 12bit ADC
- 1280x1024 VGA (24bit)
- One LTC connector (One Serial Peripheral Interface (SPI) Master ,one I2C and one GPIO interface )
and a lot more goodies to boot.The ARM side can run Linux... Hmmm, Prop IDE running there? My Raspberry Pi does
mov r1, #my_constant rdlong r0, r1 ... my_constant long $12345678However, that approach takes three longs, two for instructions and one for the constant itself where the AUGS solution takes only two longs.
Actually, no.
The FPGA tools are certainly NOT open, and the FPGAs themselves are NOT open, and most of the FPGA boards are NOT open.
All you have done, is move some hardware, into software. Open Source Hardware is still a myth.
However, semantics aside, this does have great educational and niche use potential.
I take a different view. The Propeller is open source, so any programs I write to run on it can be open source from top to bottom. If I want to make a derivative Propeller then it's no longer fully open source (since, as you pointed out, it runs on a closed source FPGA). But my Propeller chips themselves are now open.
Trusted by US. Not somebody else selling "trusted" things that only trust them. To some people, this is important.
Or, one could do it the way Chip initially did P1. Draw every single polygon, then you know for sure. The code = the spec.
Could we get by with a 16 bit constant (for 64KB hub) which could be expanded to an 18bit constant for 256KB hub?
Why? Well we have 4 unused P1 instructions plus the ability to expand the SYSOP instruction while totally keeping backward compatibility.
So, one will be the CALL/JMP/RET with 16-18 bit constant (absolute address) - I am thinking just using the D&S bits gives us 18 bits. Using KISS means that the lowest 2 bits will always be 00.
BTW The way Chip has coded the P1, he keeps the instruction set completely regular. So you have to be careful if we try to use the zcri or cccc bits for anything other purpose.
So, CALL/JMP/RET will use a fixed register $1EF (or later maybe $1EC-1EF by using the lower 2 bits of S).
BTW this is already complex enough because we have to add wait states for the hub access, and this is going to cause possible delays in the completion of the previous instructions writeback.
For the constant, which is better...
LOAD #16-18_bit_address 'loads 16 bits into fixed register, say $1EE, zeroing the upper bits
or
RDLONGX #16-18_bit_address 'loads 32 bits from address into fixed register, say $1EE
The second one is much more difficult as there is wait states to take care of.
One needs to be some form of load address, so maybe the same as the CALL format using D&S for 16-18 bits.
So, the only truly open sourced chip is the propeller chip. Anything else on the pcb is proprietary. That means the regulator, the eeprom (or the chip involved in downloading and the device which did the downloading), and even the capacitors on the boards.
And stretching this even further, the factories that make chips are closed source - you cannot make the chips yourself.
David: At least making the transistors yourself is possible. But I don't think I would like to be doing that many
Let's get past the myth, and just appreciate what Parallax has done, and get back on topic please
What cesspit that is.
I read through the first 60 odd comments in reply to Potaohead's story and I don't think I found one that was factually correct or had the slightest idea what they were talking about.
Slashdot is a faint shadow of it's former glory, such as it was, back in the late 1990's when nerdy geeks would bicker about technical stuff that they at least had some knowledge of.
Slashdot today at least dares not display it's old catch phrase "News for nerds, stuff that matters".
Now a days I think of it more as "Spews and turds, stuff that splatters".
When I publish my C code it is open source. No matter if there exists an open source C compiler to make it into executables or not. You are free to do with it what you like. Compile it how you like. Run it on whatever machine you like.
In the worst case you would have to translate my C into assembler manually, you know, with a pencil and paper. Perhaps you would then have to translate that assembler into HEX or binary manually. Then you have a program you can load into your machine and run. A machine, by the way, that I may never have heard of when I wrote my C code.
Similarly that Verilog is a description of a machine, a Propeller MCU. It is not dependant on Altera or FPGAs at all. You could use Xylinx tools and devices. You could get your own ASIC or whatever silicon made. With a bit of sweat you could manually translate that Verilog into a circuit diagram, using pencil and paper, for a circuit built out of 74 series logic chips or discrete transistors or even vacuum tubes!
The fact that the platform presented to implement that Verilog on is a closed FPGA from Altera does not detract from the openness of the Verilog.
Except that is not true. Linux runs on OpenRISC an open source processor design you will find on opencores.org.
You are right about the semantics.
My source code can be open source even if there is no compiler yet written that can compile it or no hardware that can run it.
If you think that is crazy remember Ada Lovelace was writing code for a machine Babbage never managed to build!
The point about being open is that he user can see it, change it, rearrange it, share it. The details of how it might actually get built is irrelevant and is up to the user.
What we need is to put the OpenRisc CPU and the Propeller into the same FPGA or whatever chip.
Then we have that mythical beast of a computer capable of running a full up Linux OS coupled to a Propeller for handling those fiddly real time interfacing tasks.
Open source all the way through.
Anyone got the code to run on a BeMicro CV ?
Anyone in Oz purchased a BeMicro CV ?
Where did you get it, cost, shipping, and time to ship?
Group buy for Oz?
Anyone worked out how much hub ram we can have? Looks like we could get >64KB on this.
Count me in!
IIRC Tubular was tinkering with a BEMicro CV board
Cheers
Brian
Agreed, But you were talking about open source hardware. not software.
We actually agree.
The Software source code is open source, the hardware (and the software needed to RUN that HW) is not.
So best limit the discussions to "the openness of the Verilog." and not try to claim open source hardware pathways..
I think the load will be the simplest to start off with, rather than call/jmp/ret.
ozpropdev, added.
Chip now has
http://forums.parallax.com/showthread.php/156794-Just-ordered-a-BE-Micro-CV-for-60-delivered?p=1284213&viewfull=1#post1284213
Attachment not found.
Interesting results from Chip
["It turns out that even though this Cyclone V -A2 part has 25k LE's, the P8X32A takes 85% of them! That's 33% more LE's than it takes on the Cyclone IV. Plus, it took 3x longer to compile. Oh, and Fmax is still over 80MHz, but slower than Cyclone IV. Only good thing is, these Cyclone V FPGA's cost half what the Cyclone IV devices cost in similar (higher) densities."]
I totally agree that the design and workings of an FPGA from Altera are closed technology. As are the synthesis tools they offer.
That verilog though is independent of that.
The mere fact that one can switch from Altera to Xylinx to ASIC to whatever full chip design and no longer be dependent on Parallax emphasises the point.
I'm in Brazil, not in Australia, but Verical is announcing the BeMicro CV at a substantial discount price, ~US$ 35,xx. Leon had pointed this out in another thread:
http://forums.parallax.com/showthread.php/156794-Just-ordered-a-BE-Micro-CV-for-60-delivered?p=1284191&viewfull=1#post1284191
Since they sell it in numbers departing from two units, it can be a good chance for a group buy!
Sad I'm in Brazil, but my youngest daughter lives in Sidney! Perhaps she wants to find a good gift for a distant living daddy!
Yanomani