Open Propeller Project #6: Open Source Verilog for Propeller 1
Ken Gracey
Posts: 7,392
Parallax has released the Verilog code used to design the Propeller 1 (P8X32A) Multicore Microcontroller. Please use this thread for ongoing discussion, sharing code and FPGA variants around this Open Propeller Project.
Start right here please: http://www.parallax.com/microcontrollers/propeller-1-open-source
As we see some initial use of the Verilog we will likely rally behind some efforts, possibly developing a new Propeller chip from contributor efforts.
This post will be revised as a place to put new file downloads created by the community, if desired.
Ken Gracey
600 x 250 - 98K
610 x 250 - 166K
Comments
Thanks Parallax!
Of course, I'm so busy with so much stuff right now that I doubt I could find time for anything. So, I'm looking forward to what you all do with this!
Time to forget what VHDL I know, and replace it with Verilog haha
If this doesn't inject some impetus and innovation into the Propeller scene then nothing will
What a fantastic opportunity to not only be able to run the Propeller code on an FPGA, but to be able to learn and understand the workings, and then modify it as well.
To new folks reading this thread...
A number of us have been fortunate enoughto have been able to take part in testing a new version of the Propeller chip, commonly referred to here as the P2. This is open to everyone who has the right FPGA board(s). As a community we have learnt so much from this.
Please show your support to Parallax by purchasing your FPGA board(s) from Parallax.
ll.
What an exciting opportunity to learn microcontroller design at this level with an architecture you are already familiar with. This is a bold move and a truly exciting announcement!
It will be interesting to see what people do with this.
I hope this move brings you a lot of customers, as it is a very forward thinking move.
I find it encoraging that it uses only ~15K LE out of 22K on a DE0-Nano, making it easy to try all sorts of Prop1-variants.
[QUOTE=mark
I came back to this stuff after a long detour in mechanical engineering and manufacturing. Chip, Ken, the Propeller and this great community, filled with smart friends has been an outstanding learning experience!
Now Parallax is taking us all right to the edge!
Here's to many happy days ahead!
You guys are awesome, that is all.
Especially not hard, if you have a starting framework.
So this is really a P1- on the DE0-Nano, which means any P1 code that expects the character ROM, will not work.
Is the character ROM there as a conditional compile switch ?
Looks like a matrix / table of what is in, and out, on various FPGA targets is needed.
Elektor Magazine has been informed. They also run Circuit Cellar.
They are aware of that ;-) Hopefully, it does not become painfully aware.
Surely all the ROM can be turned off. Then with a small boot section (for maybe a different, non-deterministic loader state machine in verilog), all that saved space if any could be opened to more program code.
Yes. And a link to the code ;-)
Hopefully Parallax can make some money on DE0 Nano sales and other board.
Exciting times ahead indeed.
That would be the best approach, a few conditionals to allow selective scaling of the ROM.
ROM should compile into block RAM, so will have less logic impact, but that assumes the block RAM is there and spare. (ie above the 32K needed for a ==P1)
eg the BEMicro CV I think has 220KB of RAM, so it can do all of the RAM+ROM of P1 and even extend to any mix of 220KB (within any address limits)
Of course, I would expect a number of target board builds/confirms to be done quite quickly, and they should all be linked, with info on what is in, and out.
Regarding the ROM i wonder if there could be enough room for say 48 characters, A-Z uppercase, 0-9 and some punctuation, with a mapping built into the verilog to select the appropriate match
The other thing to implement asap is the port B, bringing up 64 i/o
Thanks. Just to be clear, it's here: http://www.parallax.com/downloads/setup-propeller-1-design-de0-nano
Right now, one line of Verilog gets commented out to eliminate the character ROM from the DE0-Nano compile, in order to make it fit. I tried doing the first half of the character ROM (characters $00..$7F), but there wasn't even room for that.
The BEMicro CV board is really chip and has plenty of RAM to spare, as well as logic. All one would have to do is make a unique top.qsf file for that board, and compile it with the other files, and they'd be running.
I think many of you will be kind of surprised at how little Verilog code it takes to make a Propeller 1 chip. The cog.v source file is only 4KB, for example.
I thought the ROM was set into RAM space as discussed elsewhere. Could be wrong of course.
Tubular, yes! Port B!
So 48KB of HUB RAM is not interesting?
IIRC, the ROM area is half full of tables and other code that may or may not get used on a custom design.
Well anyway, there are other FPGAs out there that are big enough to add significantly more value.
Ken Gracey
Good job Parallax.
The downloaded worked fine and the package unzipped all ok. :cool: 60050-60056-Propeller-1-Design-2014-08-06 .