Phil Pilgrim (PhiPi) wrote: »
PoS = Piece of $#|+.
The thing is, Opera+OS/X works flawlessly for almost everything else, including this forum. Opera is widely recognized for being standards-compliant. Unless the two sites I'm having trouble with use some non-standard Ajax techniques or bleeding-edge HTML5, I would expect it to handle them without issue.
Mike Green wrote: »
Here is the Prop II page of the Propeller Wiki.
Leon wrote: »
If anyone feels the urge to design their own chips, a perpetual license for Laker starts at $45,000.
Beau, this is awesome stuff. Even though I can't understand most of it, I do kind of get a little bit. It's neat to see. Thanks.
Of course Microsoft would never intentionally create such mischief. But if it happened unintentionally, well, some things can't be helped.
Could we get a tentative spec sheet or list? At first I wanted more cogs, but with more memory and more speed instead it will be the cat's pajamas!
Is this going to drive down the cost of Prop 1?
It's absolutely fantastic that Parallax allows this sort of post. Just shows how open you all are, totally unlike all the other chip companies out there.
I presume the test chip will also have a cog and the new counter/video/xxx block.
Have you & Chip figured out how the Sram / SDram interface is going to work yet ?
To come back on Prop II, any change we will have 16 cogs when it will be out?
Or definitvely not in the roadmap?
Thanks for the link Mr.Green.
I was hoping to see more COG ram, But after watching the videos to make all of this happen,I would have ended up with about 8 bits and then killed my self! (just kidding) I never realized the effort needed to develop the silicon.This looked grooling to me.I have an even higher level of respect for Mr.Chip G. and Mr.Beau S.now that I've seen the intensive amount of work needed to make the Prop!
I think now matter what, The Prop II we'll be awesome.
I have updated the TOP link of this thread with a General Floorplan outline that shows the relative size of each COG.
Can you tell me a bit about the software and Operating System I'm seeing?
Looks like Linux, but maybe not.
I would like to go do some reading, so I can understand better what was just presented in the videos.
I'm stunned at the number of structures and the speed with which they are manupulated and displayed!
A DRC run like that used to take 10 minutes, but I finally figured out what the computer wanted and was able to optimize my setup with a new machine.
I basically have a Linux (Fedora 10) native boot quad core 2.4GHz 64-Bit machine with 6 Gigs of RAM on a Dual Head machine. One Head runs Linux, while the other Head runs Windows XP through VMWare.
In addition I have a 1 Terra Byte Drive (internal) with another 1 Terra Byte Drive (external)
I have another drive (150Gig Solid State Drive) which ultimately contributes to the processing speed and acts like an overflow when I go beyond the 6 Gigs so it doesn't actually HASH my hard drive. I have this drive configured in Linux as external RAM and not a drive. It's not exactly a swap drive... I'll have to dig into my notes for the details on how I set it up, but basically the system sees it as memory and not a drive at all.
The software for the Layout is called 'Laker' from Silicon Canvas and is very much like 'Virtuoso Layout Editor'. This is a Linux based editor.
The software for the Schematics we use is S-Edit from Tanner and runs on the Windows XP system
Development costs are high, because the application complexity is high, and the application is higher end, because it's pushing the boundaries of whatever discipline being addressed with a software solution.
Quite simply, there are problems to be solved, and those just take a lot of man hours.
Of course, that results in a fairly high ratio of end users -vs- development, which drives the cost.
@Beau: Thanks! And yes, solid state disks as RAM are a great innovation. Can't wait for the next round of cost / scale developments to hit. A lot of compute applications will benefit --some very significantly.
IMHO, Linux has been such a good thing. Large memory model computing has traditionally been SO expensive. Costly enough to make that 40K seem like chump change. Now, it's possible to get a ton of compute power, and big memory models for very modest sums, by comparison.
Am I to understand then, things are done in layers. Blocks, on blocks, on blocks, then structures, then higher level assembly, followed by the glue and interconnect means and methods needed?
The "test chip" isn't really a prop, but more like a collection of things, cases, and other bits needed to realize what's going to need to happen for the final design, and what can happen for the final design...
Small things can be built, simulated, and vetted using simulators, FPGA, etc...
That gets the logic, timing, etc... done. Planning happens that way, it seems.
Put a coupla COGs on there, some RAM, then sprinkle I/O, Video, etc... in various contexts to verify the design expectations are in line with what the silicon is going to really do?
Build up a real prop with that data, and do a shuttle?
Any higher level comments on how that goes would be very interesting to me.
I think I'm beginning to appreciate how much analysis and core understanding is required here. Actually running something is so expensive! Getting to a working design is a huge accomplishment.
No erratta on Prop I, means something now that it didn't before. (sweet!)
Anyway, cool videos, Beau! Dunno how you keep track of all those little gates!
Don't think I could have answered that better myself. What you have asked is basically exactly how it works down to 'test chip', simulation, and planning as you outlined. The layout is very hierarchically oriented.
Unfortunately it seems we are now down to 128KB of hub RAM ?
I guess with 92 I/Os we can put video memory into a SDRAM using say using ~18 I/Os so we will have >=64 I/Os free for other things after SD.
IIRC someone recently sait there was ~7,000 transistors in a whole Z80 chip - the Prop II has ~6,800 transistors for each I/O Pin... WOW !
I heard the days of drawing chips by hand is over. Does it have to be this way? Does it have to be impossible for a lot of people? The price makes it difficult for start up companies.
If one does otherwise, it's a derivative, and that's owned by somebody somewhere. A great analogy is music. Works in much the same way.
As for the costs, there are a lot of options. CAD can, or used to be a similar thing. Very expensive. These days it's not so much, though it still is, if you want some real power.
If one just wants to start up, it's gonna hurt. On the other hand, if one makes a few friends... stuff can happen. That's how a ton of people do it. (how I did it, and am in the industry I'm in)
That's how people will do it going forward.
In the end, this isn't always on the straight up side, but if there is success, people buy in, and all seems to be forgiven.
I have noted educational / student opportunities are on the rise for a lot of this stuff. I think the generation that got in the old school way is having some influence now. Once people learn and do, they buy stuff. Interestingly, they buy the stuff they could get their hands on.
"I think the generation that got in the old school way is having some influence now." - wouldn't that be sweet?!
As far as CAD goes, your right, if you want the power your going to have to pay for it.
Case and point ... I won't mention any company names, other than Laker that we are using now.
We did try another company for their layout tool for the very reason that it was considerably cheaper.
When running an LVS (Layout Versus Schematic) and comparing apples to apples between Laker and another companies software, Laker had completed the verification before the other software had even acquired a license. Keep in mind that both tools were required to obtain a local license from either a dongle or a file on the disk.
As far as needing the Speed for the actual layout, just about any editor capable of generating a GDSii (or Calma Database) file will work until you get to the really big blocks and work your way up in the hierarchy. Then the rendering/database retrieval/display engine really needs to be efficient.
Most of the power however is needed during the actual verification process which is very interactive and needs to happen frequently as the design is put together. In other words, it's not a good idea to put a lot of stuff down in layout without checking it along the way even on a block by block basis.
In 11 years of doing custom IC layout there are but only a few times I can claim that I put a block together and it was completely DRC and LVS clean right off the bat without some little something that needed to be adjusted.
Hey, I just noted "Dual Head"
+1 serious geek cred for effective use of the X window system. :yeah::yeah:
There are days when I think that tech is all but forgotten. This is OT, but I left serious computing because MCAD and most ordinary business tools centered on the single user GUI model.
Windows is actually multi-user capable, so long as you don't want it to display anything, or you are bold and use X. (I've done that, with a application that actually was written for it during a time of transition --it was funny to watch the MSCE try to wrap their head around that)
X was a real gift, and very forward looking. It being modular, multi-user in the classic UNIX sense, and network aware was so potent!! Used to be, I would balance hardware, applications, storage, compute, etc... for the workgroup, then weave a user environment together with X, designed to largely eliminate admin tasks, often centering on ONE copy of the software used by the group. Setup is a PITA, but fun, admin over time is cake.
(we don't have effective SUID and symbolic links in windows, and that hurts about as much as no X does)
Hearing that made me happy today.
Only then would you risk getting into the real design. OR you could go with a hardcoded GA.
I really take my hat off to Chip and Beau. For such a small company to go it alone with their own chip (Chip with Prop I and now Chips and Beau with Prop II) is simply amazing. It just shows that a small team of 2 can really challenge a big team of 20. Remember, this is a chip retailing for ~$10. A small company may design their own chip if they were going to use it in a product worth many thousands or tens of thousands or more.
We all await the Prop II with baited breath :smilewinkgrin: