Maybe just tie it to to the P2 reset pin? If the P2 reset pin is like the P1 reset pin, that'd reset on power-up, brownout and external reset. Software reset would have to reset the eMMC in software though (is that even possible?)
which is sampling the rx pin containing the old data byte. New data byte appears after the loop exits. Which in turn is picked up by your posted BlockByteLoop3 loop. And it continues picking up the old/prior bytes - same as my suggestion above - but it clocks one too many as a result.
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Maybe optimistic there Rayman. Inner loop is sysclock/14:
BlockByteLoop2 rep @.end_read,n1 drvl pinClk '2 nop '4 waitx #2 '8 drvh pinClk '10 nop '12 wfbyte inb '14 .end_read28 MBytes/s, without overheads, would need sysclock of 411 MHz.
BTW: It wouldn't take much to tighten that loop to sysclock/8. Something like:
BlockByteLoop2 drvl pinClk '2 nop '4 drvh pinClk '6 rep @.end_read,#511 drvl pinClk '10 nop '12 drvh pinClk '14 wfbyte inb '16 .end_read waitx #4 wfbyte inbHmm... Been a while, not sure how I messed that up...
Maybe I never posted the fast version...
Just looked and the inner assembly loop is like this:
BlockByteLoop3 rep @.end_read,n1 drvl pinClk drvh pinClk waitx #2 wfbyte inb .end_readAh, that's writing the flash, not reading. Err, no. But that won't work as is. Not enough lag compensation. Or it might just, at slowest sysclocks.
Oh, I see what's going on, you're clocking 513 bytes, which likely doesn't hurt. It starts with this:
WaitStartBit3 drvl pinClk drvh pinClk nop testp pinBase wc if_nc jmp #DoReadBlock3 jmp #WaitStartBit3which is sampling the rx pin containing the old data byte. New data byte appears after the loop exits. Which in turn is picked up by your posted BlockByteLoop3 loop. And it continues picking up the old/prior bytes - same as my suggestion above - but it clocks one too many as a result.
A comment in the code says:
' 04JUN20: Multi-block read speed up to 28 MB/s with 300 MHz clock
Yep, sysclock/10 is close to best. You should be able to do this:
BlockByteLoop3 rep @.end_read,#511 drvl pinClk ' 8, low going clocks out from flash nop '2 10 drvh pinClk '4 12 wfbyte inb '6 14 .end_read waitx #4 wfbyte inbTo do any better than sysclock/8 requires frequency calibration. Like what gets done with the PSRAMs.