@rogloh said:
The risk in doing this that that is can alter the signal integrity of the PSRAM banks back to the P2 with more capacitive load. It will reduce your highest speed performance. Didn't we all find some time back that more than two loads is not idea for the PSRAM bus and we had to clock it slower for your 96MB/s board to work. How much PSRAM are you planning on this bus?
His 24MB board is fine and that has 3 banks on a single lane. Yet the previous SimpleP2 boards with just 2 banks on 4 lanes are not fine and fail in fast mode (sysclk/2). Not sure if that's an issue with the RAMs themselves or just that the P2 is running closer to the edge. They also tend to find ways to fail in slow mode. Very cool symptoms from testing with my emulators: booting up with dead VGA channels (blue or cyan only signal), booting up with corrupted screen, USB driver randomly stops working, audio driver randomly stops working, screen corruption, and of course any number of hard crashes.
@Rayman said:
Did try thicker copper on previous board and made zero difference .
That's because it wasn't spreading the heat all the way out across the PCB.
But, there are two things going on here…. Immediate start and long term stamina.
Long term can be fixed with cooling. Seems to be no solution to immediate start issues other than copying eval..
Agreed on the short term stability.
Once you're pushing 340-360 MHz and trying to use all cores then the cooling needs do climb quickly. Leaving a square of ground plane on the underside as bare copper or solder finished could be great for clamping to a formed aluminium case as additional heat sinking. This would still benefit from thicker copper I believe. Bottom side at least.
@VonSzarvas said:
What about clock source? Are you thinking of using a simple crystal like on the Eval board, or a MEMS oscillator like on the Edge modules ?
IIRC the edge modules use a Epson TCXO, with a Nexperia 74LVC2G04 buffer ?
TG2520SMN 20.000 ECGNNM
C: ±0.5 × 10-6 Max 500ppb
G: -40 °C to +85 °C
JMG,
That is a rather vague way of saying MEMS is the wrong term to use here, as it's classed as a resonator. Whereas a crystal, or crystal oscillator, is the one thing not classed as a resonator.
@evanh said:
JMG,
That is a rather vague way of saying MEMS is the wrong term to use here, as it's classed as a resonator. Whereas a crystal, or crystal oscillator, is the one thing not classed as a resonator.
All other factors to one side (which seem open for debate, comparing that ED article and the marketing section toward the end of the datasheet)... It seems the relative current consumption of the MEMS devices continues to be a bugbear; ~4.5mA MEMS vs 1.5mA TCXO.
Back to P2 Edge.... Can't recall now why we chose the 1.8V TCXO + buffer, instead of the 3.3V TCXO directly. Hmm.. maybe part-supply issue, XI/XO thresholds, overall power consumption, or something else subtle. I'll dig into that a little. Would be neat to simplify / modernise the clock source if possible.
@VonSzarvas said:
BTW: I had MEMS on my mind as I'm currently working on a refresh of the FLiP module, which uses a SiTime MEMS part: https://www.sitime.com/datasheet/SiT8918
Is that still the best choice ?
5MHz and small is not an easy target, or one that attracts volume ?
TCXO's come down to 10MHz , but you can get the programmable oscillators under that
Epson have a new SG-8201/SG-8200 family, that gives improved ppm and jitter for a prog oscillator, (CMOS out, 1.2 MHz to 170 MHz ) with good data specs :
The SG8201 is getting close to TCXO curves. Price indications for blank parts look to be ~63c/1k for ±50ppm and ~71c/1k for ±15ppm, I'd call these 'light TCXO'
Addit: The YXC YSO110TR family look similar jitter, I can find prices of ~31c/100 in 2016 for 4MHz and 10MHz variants with 1.8V~3.3V ±10ppm ±20ppm
Their data is not nearly as good as Epson.
It seems the relative current consumption of the MEMS devices continues to be a bugbear; ~4.5mA MEMS vs 1.5mA TCXO.
MEMS are inherently more complex but the 1.5mA is for clipped sine, so you need to ad buffer current, which can easily add 3mA
Back to P2 Edge.... Can't recall now why we chose the 1.8V TCXO + buffer, instead of the 3.3V TCXO directly. Hmm.. maybe part-supply issue, XI/XO thresholds, overall power consumption, or something else subtle.
It will likely have been mostly supply. P2 has both 3v3 and 1v8, so no added cost there.
The high volume, high stability TCXO are pretty much all clipped sine, so a simple buffer is needed.
I'll dig into that a little. Would be neat to simplify / modernise the clock source if possible.
TCXO are modern.
There was a supply hiccup a couple of years back, when some FAB was lost, but the vendors affected seem to all have new silicon and new part codes now.
500ppb TCXO can come as small as 1612 now, but at less choices in MHz and higher prices.
As an ex-EMC engineer, I vote fill with the supply that most chips are directly connected to. You want it to be as "stiff" as possible to reduce RF noise on it.
If appropriate, several supplies could be flood filled in the areas they are used in
Other than academic reasons, I'm a little surprised that this thread is still going. I know for certain that there is a hard stop of around 350MHz with 180nm technology and I have mentioned this several times. This is at the silicon level and has to do with the substrate leakage and parasitic capacitive properties forming essentially a low pass filter with 350MHz being the cutoff... that said, based on normal random distribution, there will be some chips that will be on the extreme boundary, maybe as much as +/-20MHz . Sure you can cool your board to very low temps and maybe gain a few more MHz... Even the PCB layout could make a difference.... I would stay away from inductive loops, that could be seen as a short within the IC making it work harder than it needs to ... this includes FILL ... If you must add fill, then create a small slit, that prevents it from making a complete loop encompassing the IC.
One of the chips that I designed at NSC with 180nm technology allowed for Gigabit Ethernet speeds... The "trick" in achieving greater than 350MHz was to pipeline the data with four staggered phases of 250MHz ... 250MHz left plenty of overhead to the 350MHz limit. Additionally, the oscillator section was constructed using a double NWELL to minimize any substrate effects that could attenuate the clock signal.
@"Beau Schwabe" said:
Other than academic reasons, I'm a little surprised that this thread is still going. I know for certain that there is a hard stop of around 350MHz with 180nm technology and I have mentioned this several times. This is at the silicon level and has to do with the substrate leakage and parasitic capacitive properties forming essentially a low pass filter with 350MHz being the cutoff... that said, based on normal random distribution, there will be some chips that will be on the extreme boundary, maybe as much as +/-20MHz . Sure you can cool your board to very low temps and maybe gain a few more MHz...
I wouldn't know anything about how and why, but I'm getting quite a linear graph of temperature vs MHz. I should be able to make the Prop2 run at 400 MHz stable ... at 0 degC and a light work load that is. The Cogs can go faster still but the bus to hubRAM can't.
Guess just bothersome that my boards don’t perform as well as Parallax ones. Make me feel like need to up game…
Have reasonable confidence this time is the end ( Got the Eval B/C layout and not afraid to use it!)
(Ok, actually am afraid of 5 mil vias, not doing that...)
Comments
Did try thicker copper on previous board and made zero difference .
But, there are two things going on here…. Immediate start and long term stamina.
Long term can be fixed with cooling. Seems to be no solution to immediate start issues other than copying eval..
His 24MB board is fine and that has 3 banks on a single lane. Yet the previous SimpleP2 boards with just 2 banks on 4 lanes are not fine and fail in fast mode (sysclk/2). Not sure if that's an issue with the RAMs themselves or just that the P2 is running closer to the edge. They also tend to find ways to fail in slow mode. Very cool symptoms from testing with my emulators: booting up with dead VGA channels (blue or cyan only signal), booting up with corrupted screen, USB driver randomly stops working, audio driver randomly stops working, screen corruption, and of course any number of hard crashes.
Ok, @Wuerfel_21 Hope you can keep me on my toe with this. Also want to move PSRAM from bottom layer to top.
Maybe the top two layers could be used for power and ground. https://epc-co.com/epc/design-support/gan-first-time-right/schematic-and-layout
That's because it wasn't spreading the heat all the way out across the PCB.
Agreed on the short term stability.
Once you're pushing 340-360 MHz and trying to use all cores then the cooling needs do climb quickly. Leaving a square of ground plane on the underside as bare copper or solder finished could be great for clamping to a formed aluminium case as additional heat sinking. This would still benefit from thicker copper I believe. Bottom side at least.
Awesome
With that "trick", make certain all the caps are 0402 (not larger package size)
Nice.
What about clock source? Are you thinking of using a simple crystal like on the Eval board, or crystal oscillator like on the Edge modules ?
Edited: To reflect jmg/evanh comments below. Indeed, a crystal oscillator would be a better choice for this application than a MEMS oscillator.
There's a nice and concise comparison here: https://www.electronicdesign.com/technologies/embedded/article/21263965/q-tech-corp-mems-vs-crystal-oscillators-its-all-in-the-application
Done. Going to be as faithful as possible to Eval Rev.B core.
Contemplating switching to USB-C for power/serial. Seems like the new normal...
As long as it stays backward compatible with Type-A equipment as well. As in it's just a socket change, it doesn't actually use USB-C function. Ie: Works using something like this - https://www.pbtech.co.nz/product/CABMIX18714/Xiaomi-Mi-USB-C-to-USB-A-High-Quality-Braided-Cabl
IIRC the edge modules use a Epson TCXO, with a Nexperia 74LVC2G04 buffer ?
TG2520SMN 20.000 ECGNNM
C: ±0.5 × 10-6 Max 500ppb
G: -40 °C to +85 °C
JMG,
That is a rather vague way of saying MEMS is the wrong term to use here, as it's classed as a resonator. Whereas a crystal, or crystal oscillator, is the one thing not classed as a resonator.
Indeed, a crystal oscillator would be a better choice for this application than a MEMS oscillator.
There's a nice and concise comparison here: https://www.electronicdesign.com/technologies/embedded/article/21263965/q-tech-corp-mems-vs-crystal-oscillators-its-all-in-the-application
BTW: I had MEMS on my mind as I'm currently working on a refresh of the FLiP module, which uses a SiTime MEMS part: https://www.sitime.com/datasheet/SiT8918
All other factors to one side (which seem open for debate, comparing that ED article and the marketing section toward the end of the datasheet)... It seems the relative current consumption of the MEMS devices continues to be a bugbear; ~4.5mA MEMS vs 1.5mA TCXO.
Back to P2 Edge.... Can't recall now why we chose the 1.8V TCXO + buffer, instead of the 3.3V TCXO directly. Hmm.. maybe part-supply issue, XI/XO thresholds, overall power consumption, or something else subtle. I'll dig into that a little. Would be neat to simplify / modernise the clock source if possible.
My board already supports crystal and TCXO, but TCXO didn't help with overclocking, so just using crystal. But, the option is there...
Figured out how to do the blind vias needed in Eagle. Think so anyway.
Getting it made is another story, checking on that...
Noticed that Sparkfun switched from Eagle to Kicad. Might have to follow suit (after this).
Guess actually need another type of via...
Think have a reasonable facsimile of Eval Rev. B for first group of 8 pins (40-47).
Now, just need to copy all the way around...
Is that still the best choice ?
5MHz and small is not an easy target, or one that attracts volume ?
TCXO's come down to 10MHz , but you can get the programmable oscillators under that
Epson have a new SG-8201/SG-8200 family, that gives improved ppm and jitter for a prog oscillator, (CMOS out, 1.2 MHz to 170 MHz ) with good data specs :
The SG8201 is getting close to TCXO curves. Price indications for blank parts look to be ~63c/1k for ±50ppm and ~71c/1k for ±15ppm, I'd call these 'light TCXO'
https://download.epsondevice.com/td/pdf/app/SG-8201CJ_en.pdf
https://www.epsondevice.com/crystal/en/techinfo/pdf/OUT-21-0334_PXO_TechNote_en.pdf
Addit: The YXC YSO110TR family look similar jitter, I can find prices of ~31c/100 in 2016 for 4MHz and 10MHz variants with 1.8V~3.3V ±10ppm ±20ppm
Their data is not nearly as good as Epson.
MEMS are inherently more complex but the 1.5mA is for clipped sine, so you need to ad buffer current, which can easily add 3mA
It will likely have been mostly supply. P2 has both 3v3 and 1v8, so no added cost there.
The high volume, high stability TCXO are pretty much all clipped sine, so a simple buffer is needed.
TCXO are modern.
There was a supply hiccup a couple of years back, when some FAB was lost, but the vendors affected seem to all have new silicon and new part codes now.
500ppb TCXO can come as small as 1612 now, but at less choices in MHz and higher prices.
Think this is the one that worked, but didn't help:
https://ecsxtal.com/store/pdf/ECS-TXO-2520.pdf
Yes, a TCXO will not help FMAX, but it does expand the useful application area into things like GPS disciplined Time bases and frequency counters.
Trying to get a handle on whether or not to put resistors on the CC lines of USB-C connector:
https://forum.digikey.com/t/simple-way-to-use-usb-type-c-to-get-5v-at-up-to-3a-15w/7016
I'm seeing one Sparkfun example where they don't do it. But, here, suggests can get more power if you do...
Anyway, glad Sparkfun didn this board in Eagle before switching to Kicad...
Hmm... USB-C connector is relatively ginormous compared to micro-b...
Wondering if should poly fill the top layer with 5V, like eval B, or something else, or nothing...
Ok, I see now rev.B had 5V on LDOs for 3.3V. Guess if fill, could be with the 3.65 V...
As an ex-EMC engineer, I vote fill with the supply that most chips are directly connected to. You want it to be as "stiff" as possible to reduce RF noise on it.
If appropriate, several supplies could be flood filled in the areas they are used in
@VonSzarvas thanks for putting eval C diptrace in OBEX . Big help. Copied having ground poly fill on top layer…
@bob_g4bby thanks for tip. Think most of top and bottom as ground makes a nice faraday cage around most traces
Other than academic reasons, I'm a little surprised that this thread is still going. I know for certain that there is a hard stop of around 350MHz with 180nm technology and I have mentioned this several times. This is at the silicon level and has to do with the substrate leakage and parasitic capacitive properties forming essentially a low pass filter with 350MHz being the cutoff... that said, based on normal random distribution, there will be some chips that will be on the extreme boundary, maybe as much as +/-20MHz . Sure you can cool your board to very low temps and maybe gain a few more MHz... Even the PCB layout could make a difference.... I would stay away from inductive loops, that could be seen as a short within the IC making it work harder than it needs to ... this includes FILL ... If you must add fill, then create a small slit, that prevents it from making a complete loop encompassing the IC.
One of the chips that I designed at NSC with 180nm technology allowed for Gigabit Ethernet speeds... The "trick" in achieving greater than 350MHz was to pipeline the data with four staggered phases of 250MHz ... 250MHz left plenty of overhead to the 350MHz limit. Additionally, the oscillator section was constructed using a double NWELL to minimize any substrate effects that could attenuate the clock signal.
I wouldn't know anything about how and why, but I'm getting quite a linear graph of temperature vs MHz. I should be able to make the Prop2 run at 400 MHz stable ... at 0 degC and a light work load that is. The Cogs can go faster still but the bus to hubRAM can't.
Guess just bothersome that my boards don’t perform as well as Parallax ones. Make me feel like need to up game…
Have reasonable confidence this time is the end ( Got the Eval B/C layout and not afraid to use it!)
(Ok, actually am afraid of 5 mil vias, not doing that...)
But it’s really the 4bit sd driver that restarted it..
Rereading that, I should have said: At 0 degC, the Cogs can go faster still but the bus to hubRAM can't.