It could be a useful test if neither chips are damaged in the process. It will at least tell you if one chip performs better on a lower performing board than another...assuming soldering doesn't significantly affect results. Hopefully the soldering is good. Will be interesting to see what happens. Also in particular to see what happens on the EVAL.
You even also put things back later as it was, and see if good performance returns to the EVAL - if not that might indicate that the soldering process is likely to affects things.
@evanh said:
Don't you have a number of Prop2 ICs you've been testing with already? Seems to me that pulling one from an Eval board isn't achieving anything.
I think the idea is to take a known-measured-exact-MHz part from EVAL and see how many MHz the same part decreases by, on the second board.
(and how many MHz the other P2 increases by, on Eval)
Looking for ghosts doing that. And that's assuming nothing goes wrong.
Really need a way to rapidly measure the die temperature. If Chip does a respin at any stage then I'll be asking for an internal diode voltage measurement to be added next to the reset/brownout circuits.
EDIT: The diode would be even better located in the middle of the "eggbeater" crosspoint switch, but I doubt he'd have that as an option.
On the next rev, you could allow two holes, and connector, to mount a cooler ?
I see this Fan+Plate is just $5, for Pi 5 https://www.adafruit.com/product/5815
@Rayman said:
Transplant complete.
A2 board with Eval's chip is now one of my best. Not the best, interestingly, but very close.
Eval board with A2's chip is dead
This is an interesting result. Pity your original A2 chip is dead (maybe resolder will revive it). Looks like your performance limits are either thermal related to soldering or just the P2 chip variation, and not the other A2 board components or board itself (unless the nearby resoldering improved these support components somehow).
We learned that other components such as regulator and crystal stuff is not necessarily the main contributor to the problem of some of Rayman's boards performing worse than others. It's mainly chip variation or soldering related. Could well be due to soldering if most of the P2-Edges and EVALs seen to date have little performance variation. I think this was useful.
Grr! Of course the soldering is not the issue ... but it is what you're seeing because you're looking too hard for small variations ... and you can't eliminate it. It's like noise in the signal. You're seeing ghosts ... or UFOs if you like.
Here's the final results of first group.
Also, posted the design files to top post.
There is definite correlation between simple VGA overclocking test and NeoYume test.
Solder paste thickness and type less clear, likely doesn't matter...
@evanh said:
Don't you have a number of Prop2 ICs you've been testing with already? Seems to me that pulling one from an Eval board isn't achieving anything.
I think the idea is to take a known-measured-exact-MHz part from EVAL and see how many MHz the same part decreases by, on the second board.
(and how many MHz the other P2 increases by, on Eval)
Do chips permanently degrade at all with soldering and desoldering?
Decided to make another go at this, after not really being totally happy with overclocking ability. But, it's really the new 4-bit SDIO uSD driver from @evanh and @rogloh that pushed me over the edge (hey, just saw a pun here!).
This time, going to do what should have done from the beginning and copy the Eval design.
Fortunately, they posted the Diptrace for Rev.B, so I have 30 days to examine that for free.
This appears to be a 4-layer board. Don't remember exactly how well it did but pretty sure better that this board here.
If you can't beat 'em join 'em
There are several things I'm seeing now that maybe overlooked before:
1.8V ring inside the pins
Caps right next to pins (ok, seeing how they did this now)
Vias under P2 ground pad connected to square fill on inner layers. Can't imagine why didn't do this now, pretty obvious thing in retrospect.
Feeding 3.3V LDOs from a common 3.65V supply. Ok, this is obviously the right thing to do, was wasting energy feeding from 5V supply.
Running P2 I/O out on inner layer. This is the trick to getting caps close to P2.
Ground pads just outside caps. This probably helps with thermals too as brings bottom layer to top.
They used beefly LDOs on every 8 pins. Thinking about little one on every 4 pins, we'll see.
Continuous ground plane under P2. Putting caps on bottom around P2 probably a very bad idea. Plus, didn't help.
3.65V fill around all of this. Liking this idea too.
4.7uF caps for P2 power pins instead of 1.0uF. Still not sold on this 100%, but might as well go all in.
Blind vias so ground layer is continuous. This costs extra, but guess needs to be done. Might rearrange the layers for this. Never did blind vias before...
That's what hoping we get me closer to Eval/Edge overclocking.
The other things want to add:
4-bit SDIO, as mentioned
Reset brought out to fill gap on long header. Decided robots need reset and a shield on top blocks access. Also, continuous header is easier to solder.
1.8V brought out somewhere. For ease in checking it if nothing else.
Make sure to apply the same ideas to the RAM, too. If your CAD software can do it, maybe try matching the length of the data lines. That should enlarge the sweet spot.
@Rayman said:
Been toying with idea of putting qpi flash on second row to share bus with psram.
Qpi flash density has increased a lot since last looked…
The risk in doing this that that is can alter the signal integrity of the PSRAM banks back to the P2 with more capacitive load. It will reduce your highest speed performance. Didn't we all find some time back that more than two loads is not idea for the PSRAM bus and we had to clock it slower for your 96MB/s board to work. How much PSRAM are you planning on this bus?
Feeding 3.3V LDOs from a common 3.65V supply. Ok, this is obviously the right thing to do, was wasting energy feeding from 5V supply.
The basic idea is good, as it also moves thermal sources away from P2, but you may want to check the PSRR and how low dropout affects that.
Blind vias so ground layer is continuous. This costs extra, but guess needs to be done. Might rearrange the layers for this. Never did blind vias before...
The money may be better spent on thicker copper, ( or of course both ) and if the base of the board is all GND, you could look at FAN or even Peltier mounting options ?
There are low cost high power LED fan+heatsink assemblies, design bed to cool higher power LEDs
A bit more expensive are the 1U coolers that have what could be a more useful horizontal airflow ?
Comments
About to attempt chip swap...
Why? Seems to me like you're throwing away a good Eval board.
Maybe not if chips are same…
Fun experiment anyway
It could be a useful test if neither chips are damaged in the process. It will at least tell you if one chip performs better on a lower performing board than another...assuming soldering doesn't significantly affect results. Hopefully the soldering is good. Will be interesting to see what happens. Also in particular to see what happens on the EVAL.
You even also put things back later as it was, and see if good performance returns to the EVAL - if not that might indicate that the soldering process is likely to affects things.
Don't you have a number of Prop2 ICs you've been testing with already? Seems to me that pulling one from an Eval board isn't achieving anything.
I think the idea is to take a known-measured-exact-MHz part from EVAL and see how many MHz the same part decreases by, on the second board.
(and how many MHz the other P2 increases by, on Eval)
Looking for ghosts doing that. And that's assuming nothing goes wrong.
Really need a way to rapidly measure the die temperature. If Chip does a respin at any stage then I'll be asking for an internal diode voltage measurement to be added next to the reset/brownout circuits.
EDIT: The diode would be even better located in the middle of the "eggbeater" crosspoint switch, but I doubt he'd have that as an option.
Transplant complete.
A2 board with Eval's chip is now one of my best. Not the best, interestingly, but very close.
Eval board with A2's chip is dead
On the next rev, you could allow two holes, and connector, to mount a cooler ?
I see this Fan+Plate is just $5, for Pi 5
https://www.adafruit.com/product/5815
Good idea... The 30mm X 30mm fans seem popular:
https://www.amazon.com/dp/B076H3TKBP/
This is an interesting result. Pity your original A2 chip is dead (maybe resolder will revive it). Looks like your performance limits are either thermal related to soldering or just the P2 chip variation, and not the other A2 board components or board itself (unless the nearby resoldering improved these support components somehow).
If we assume the soldering doesn't impact results...
Seems Eval board is definitely better with same chip. Not surprising given 2 oz copper (?) and 6 layers.
But, only ~ 10% faster, maybe not worth it?
Seems to point to my board to board speed limits being chip dependent.
But you do know resoldering makes a difference. I don't think anything was learned.
We learned that other components such as regulator and crystal stuff is not necessarily the main contributor to the problem of some of Rayman's boards performing worse than others. It's mainly chip variation or soldering related. Could well be due to soldering if most of the P2-Edges and EVALs seen to date have little performance variation. I think this was useful.
The variations are small when the soldering is good. The variations are large when the soldering is bad.
EDIT: To put that another way: When testing for small variations, the soldering quality can always be blamed.
I chased soldering for a while but am now convinced that is not an issue.
Plus the fast failure mechanism is too fast for soldering to matter. Pretty sure is internal to chip.
Grr! Of course the soldering is not the issue ... but it is what you're seeing because you're looking too hard for small variations ... and you can't eliminate it. It's like noise in the signal. You're seeing ghosts ... or UFOs if you like.
It is something like that…
Wish there were more examples (or any) here to look at in 4 layers…
Here's the final results of first group.
Also, posted the design files to top post.
There is definite correlation between simple VGA overclocking test and NeoYume test.
Solder paste thickness and type less clear, likely doesn't matter...
Do chips permanently degrade at all with soldering and desoldering?
Performance won't degrade, no. But material stress will eventually fracture joints in a sudden failure.
EDIT: Err, maybe the thermal pad bonding to the die can be gradually degraded and thereby degrade thermal conductivity. Dunno.
Interesting board.
Decided to make another go at this, after not really being totally happy with overclocking ability. But, it's really the new 4-bit SDIO uSD driver from @evanh and @rogloh that pushed me over the edge (hey, just saw a pun here!).
This time, going to do what should have done from the beginning and copy the Eval design.
Fortunately, they posted the Diptrace for Rev.B, so I have 30 days to examine that for free.
This appears to be a 4-layer board. Don't remember exactly how well it did but pretty sure better that this board here.
If you can't beat 'em join 'em
There are several things I'm seeing now that maybe overlooked before:
That's what hoping we get me closer to Eval/Edge overclocking.
The other things want to add:
Make sure to apply the same ideas to the RAM, too. If your CAD software can do it, maybe try matching the length of the data lines. That should enlarge the sweet spot.
Been toying with idea of putting qpi flash on second row to share bus with psram.
Qpi flash density has increased a lot since last looked…
Are they layout compatible? Because I'm still a fan of 64MB RAM (and a massive anti-fan of hard-wired flash storage...)
Think pads are close if not same
Maybe flash not so important with new sdio driver…
The risk in doing this that that is can alter the signal integrity of the PSRAM banks back to the P2 with more capacitive load. It will reduce your highest speed performance. Didn't we all find some time back that more than two loads is not idea for the PSRAM bus and we had to clock it slower for your 96MB/s board to work. How much PSRAM are you planning on this bus?
The basic idea is good, as it also moves thermal sources away from P2, but you may want to check the PSRR and how low dropout affects that.
The money may be better spent on thicker copper, ( or of course both
) and if the base of the board is all GND, you could look at FAN or even Peltier mounting options ?
There are low cost high power LED fan+heatsink assemblies, design bed to cool higher power LEDs
A bit more expensive are the 1U coolers that have what could be a more useful horizontal airflow ?