P2 I2S & S/PDIF audio (was Adjacent pin question and clock regeneration jitter)

evanh

@TonyB_ said:
The question now is how much jitter with various divd < 22 ?

It seems to be roughly proportional to the divider when above 200 MHz sysclock. Below 200 MHz, I think there is another growing factor inverse to frequency. It becomes quite notable below 80 MHz.

TonyB_

@evanh said:

@TonyB_ said:
The question now is how much jitter with various divd < 22 ?

It seems to be roughly proportional to the divider when above 200 MHz sysclock.

Thanks for the clarification, Evan. This is what I thought I was seeing when I said:

The heights of the peaks and troughs within the waveform appear to increase as PLL divider value increases.

evanh

Ya, but just to be clear, those are more accurately widths rather than heights. In hindsight, I should have disabled the trace interpolation at the outset.