@hinv said:
So how fast does it go in MB/sec @320MHz sysclk? At 8 bits wide, I'm guessing it takes less cycles to set up and feed command and address than a 4bit wide PSRAM. So how many cycles for a read/write? Do you get 16bits every time since it is DDR?
I never did a full driver, so there isn't any actual benchmarking with my solution. If I had such a driver I would attempt cogless methods, then it'd have lower overhead than Roger's solution but likely terrible sharing between cogs.
Yes, HyperRAM is a full clock cycle, two data steps, as smallest transaction. There is also the DQS control line intended for controlling writes on a step by step basis. So each byte can still be individually managed. But not easy to manage without custom hardware. DQS would be done as a ninth data bit to the streamer if attempting to use that. Otherwise it'd be bit-bashed or read-modify-write in two bursts and ignoring DQS. Not sure what Roger has done here.
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I never did a full driver, so there isn't any actual benchmarking with my solution. If I had such a driver I would attempt cogless methods, then it'd have lower overhead than Roger's solution but likely terrible sharing between cogs.
Yes, HyperRAM is a full clock cycle, two data steps, as smallest transaction. There is also the DQS control line intended for controlling writes on a step by step basis. So each byte can still be individually managed. But not easy to manage without custom hardware. DQS would be done as a ninth data bit to the streamer if attempting to use that. Otherwise it'd be bit-bashed or read-modify-write in two bursts and ignoring DQS. Not sure what Roger has done here.