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P2 ADC timing — Parallax Forums

P2 ADC timing

Hello,
How many clocks are needed for an 8 or 16 bit conversion?

Thank you.

Comments

  • AribaAriba Posts: 2,471

    Depends on the ADC mode. Here is the table from the documentation:

  • Does the ADC take a sample?
    Or do analogue value fluctuations have an effect on the conversion?

  • AribaAriba Posts: 2,471

    It's a Sigma-Delta ADC, so it measures the average voltage over the sample periode.

  • Ok.
    So the input does not have a sample & hold circuit.
    The counter always runs behind the measured value.
    If the input signal changes relatively slowly, higher resolutions in shorter periods would also be possible.

  • evanhevanh Posts: 10,951

    @pic18f2550 said:
    Ok.
    So the input does not have a sample & hold circuit.
    The counter always runs behind the measured value.

    Correct on both.

    If the input signal changes relatively slowly, higher resolutions in shorter periods would also be possible.

    Yes, and the Sinc3 mode is fastest. Limited by the first-order sigma-delta loop I think. Chip mentioned somewhere around 1 MHz, from memory.

    There is a DC noise floor that isn't particularly great though. The reason is a little beyond my understanding. If you don't need DC then it performs well.

  • evanhevanh Posts: 10,951
    edited 2021-05-02 05:47

    @pic18f2550 said:
    The counter always runs behind the measured value.

    The SincN accumulating counters are 27-bit wide. In Sinc3 mode, that caps the decimation period to max of 512 bit-clocks, or 2^(27/3). For an internal bitstream, from the internal ADC, that's 512 sysclocks. Decimation period is settable with WYPIN, after the WXPIN.

    In Sinc2 "filtering" mode it is a max of 2^(27/2), or 11585 bit-clocks.

    PS: The 27-bit width of "filtering" modes need an additional treatment that's not documented. Without the treatment they will sporadically glitch. I haven't fully got to the bottom of it but I have noticed the glitching is amplitude sensitive.

    The fix is to always eliminate the higher significant bits, over 27, from the 32-bit handling of the decimation. This can be either done as shift left by five, scaling to 32-bit, or by zeroing the upper five bits of the post-diff'ed sample.

    There is a handy instruction just for zeroing - ZEROX

  • The DC noise occurs when the counter changes its counting direction.
    It tends to drift around the switching threshold of the comparator.
    This is usually only one or two bits.

  • evanhevanh Posts: 10,951

    It's much worse than that. Chip refers to it as 1/f noise. The largest decimation periods don't provide any improvement in ENOB.

    I'm guessing that adding some fancy low-pass digital filtering can help some, but I fear it won't be nearly as much as a it would if the DC noise wasn't so bad. I keep meaning to get extra filtering running myself but my knowledge of frequency analysis is very limited so I don't have an end method in mind.

  • evanhevanh Posts: 10,951

    The ENOB numbers in the table above probably only apply in a bandpass above 10 Hz or so.

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