I'm guessing the two ceramic capacitors are protecting V4855 from a trigger event while I'm using the 330 ohm resistor.
That’s possible, as scr’s also have a dV/dT trigger mode, where the capacitance + slope gives the trigger current.
If you can see a dV/dT trigger, maybe quantify what slope is needed ?
It doesn't seem to, not to the 6 Volts anyway. BTW, the current is more like 500 uA now but has been so for a while. I've not worked out why it was 700 uA initially but not since.
EDIT: I did find one bad jumper lead so maybe I had the power supply higher than 6.25 Volts and that clip was losing some. The readout on the bench power supply isn't accurate at all so I rely on the multimeters.
Some vendors with 5V tolerant spec that only with Vdd powered - ie something like Vdd+2,5V, which is suggesting a reverse stress point.
Not sure if P2 has similar VIO to VDD bias issues?
Ie it may be better to test with Vdd powered as long term use with Vdd=0 is less likely. I guess some power failures, or voltage removal watch dogs could briefly remove Vdd, but those are rare.
Did you try RC discharge via reverse diode clamp of pin with VIO = 4v (say) ?
That injects a current, similar to a ESD or Power connect spike.
V4047 with 6.87 Volts is drawing 50 uA. No sign of volts on VDD. EDIT: Actually, the current draw is slowly drooping over time. Been sitting at 6.87 volts for the last ten minutes. It was above 50 uA, maybe 55, but is now below 45 uA.
EDIT2: Same story as V4855. If I ramp up through 0.7 Volts slower then the current is much higher. At the moment I'm sitting on 3.12 Volts and 171 uA for example. EDIT3: And now 1.0 V and 2.65 mA, continuing this one up to 2.0 V gives 7.4 mA.
I'd be hesitant about signing a waiver if it makes Parallax responsible for a blown tester regardless of fault. In that case I'd push back and say: your test your tester your problem. They might say no. But at least you're not on the hook for a mysteriously breaking tester now and forever.
If it's not all about that and just having a somewhat lower absolute maximum, then it's just FUD. Oh well. If we blow up our chip it's our fault for exceeding maximum.
Can you confirm if bad things happen if you feed all 4 signal pins on a VIO group 5.5 volts through a 1K resistor? Does that cause the latch up? If not, just ship it.
V4047 with 6.87 Volts is drawing 50 uA. No sign of volts on VDD. EDIT: Actually, the current draw is slowly drooping over time. Been sitting at 6.87 volts for the last ten minutes. It was above 50 uA, maybe 55, but is now below 45 uA.
EDIT2: Same story as V4855. If I ramp up through 0.7 Volts slower then the current is much higher. At the moment I'm sitting on 3.12 Volts and 171 uA for example. EDIT3: And now 1.0 V and 2.65 mA, continuing this one up to 2.0 V gives 7.4 mA.
Do you know why the slope around 700mV has such persistent effects?
It might be good to pull the four related I/O's low, so that they can't float around the linear region and eat extra current.
Ha, good point, there is volts on all eight I/O pins, and seem to be steady too. Ranging from 0.1 to 1.5 volts.
EDIT: Oops, V4047 is only 1.2 volts itself, so some are full rail. Differing impedances too. A 3k3 resistor will pull a 970 mV pin40 right to zero volts but the moment the resister is removed the 970 mV is straight back in place. No impact on the V4047 current. Same 3k3 on pin42, which is at 334 mV, drops to 270 mV and straight back to 334 mV when removed.
Ha, good point, there is volts on all eight I/O pins, and seem to be steady too. Ranging from 0.1 to 1.5 volts.
EDIT: Oops, V4047 is only 1.2 volts itself, so some are full rail. Differing impedances too. A 3k3 resistor will pull a 970 mV pin40 right to zero volts but the moment the resister is removed the 970 mV is straight back in place. No impact on the V4047 current. Same 3k3 on pin42, which is at 334 mV, drops to 270 mV and straight back to 334 mV when removed.
The VIO logic powers up with DIR=0 and mode bits low, until the core logic powers up and changes it.
With VIO=1.2V, it seems like DIR=1, somehow. Maybe it didn't get a clean power-up. The mode bits could be scrambled, too, without the core powered to set things straight.
The VIO logic powers up with DIR=0 and mode bits low, until the core logic powers up and changes it.
With VIO=1.2V, it seems like DIR=1, somehow. Maybe it didn't get a clean power-up. The mode bits could be scrambled, too, without the core powered to set things straight.
Does VIO reset need a working Sysclk ?
Or is RESN=L enough to init pincells ?
That makes sense. This happens in varying degrees when I ramp VIO up through 0.7 volts really slow like 100 mV/sec. I haven't seen it happen any other time.
That makes sense. This happens in varying degrees when I ramp VIO up through 0.7 volts really slow like 100 mV/sec. I haven't seen it happen any other time.
The slower you ramp up VIO, the less likely that capacitor bias in the level translator is going to have the intended effect, and the more likely you're going to wind up with some random state in each control bit. That has got to be what you are seeing.
The VIO logic powers up with DIR=0 and mode bits low, until the core logic powers up and changes it.
With VIO=1.2V, it seems like DIR=1, somehow. Maybe it didn't get a clean power-up. The mode bits could be scrambled, too, without the core powered to set things straight.
Does VIO reset need a working Sysclk ?
Or is RESN=L enough to init pincells ?
No clock is needed.
RESn=0 will asynchronously reset the core logic which will reset the control signals going to each I/O pad. In Evans case, right now, the core is unpowered, so we are relying on the capacitor biases in the VDD-to-VIO level translators to give proper initialization of zeroes to the VIO-powered circuits.
The level translators latch on input change. They have weak positive feedback. So, the core must drive them one way and then the other.
Without the core powered, each level translator powers up in some random state, except DIR and the top five mode bits, which have bias caps to initialize them as lows. Slow enough VIO rise, though, will cause them to not clear reliably.
Even if the top five mode bits clear properly, the lower eight mode bits will still be random. With the top five bits low, setting up normal digital mode, the lower bits could possibly enable a current drive mode, which will turn on some current bias circuitry, which will draw continuous current.
The design assumes that all these cases of VIO and VDD not being simultaneously powered up or down are brief in duration.
The VIO logic powers up with DIR=0 and mode bits low, until the core logic powers up and changes it.
With VIO=1.2V, it seems like DIR=1, somehow. Maybe it didn't get a clean power-up. The mode bits could be scrambled, too, without the core powered to set things straight.
Does VIO reset need a working Sysclk ?
Or is RESN=L enough to init pincells ?
No clock is needed.
RESn=0 will asynchronously reset the core logic which will reset the control signals going to each I/O pad. In Evans case, right now, the core is unpowered, so we are relying on the capacitor biases in the VDD-to-VIO level translators to give proper initialization of zeroes to the VIO-powered circuits.
Ok, I think you are saying sysclk is not needed but vDD is required for known-state outcome ?
The VIO logic powers up with DIR=0 and mode bits low, until the core logic powers up and changes it.
With VIO=1.2V, it seems like DIR=1, somehow. Maybe it didn't get a clean power-up. The mode bits could be scrambled, too, without the core powered to set things straight.
Does VIO reset need a working Sysclk ?
Or is RESN=L enough to init pincells ?
No clock is needed.
RESn=0 will asynchronously reset the core logic which will reset the control signals going to each I/O pad. In Evans case, right now, the core is unpowered, so we are relying on the capacitor biases in the VDD-to-VIO level translators to give proper initialization of zeroes to the VIO-powered circuits.
Ok, I think you are saying sysclk is not needed but vDD is required for known-state outcome ?
Correct. I kept editing the post above to elaborate on this matter.
Uh-oh, just tried VDD powered - the whole board powered normally except for V4047 - and it doesn't help. Pressing the reset button doesn't help either. A slow rise on any VIO ... is looking bad.
DOH!!! I'd left out the VDD jumper.
If VDD is powered and RESn=0, all the I/O pads will receive all zeros, which will put them in digital input mode with the lowest-possible quiescent current. If the pins are allowed to float, though, they could get around the logic threshold and consume 50uA each. If each pin is pulled low or high, total VIO current should be less than 1uA.
If VDD is powered and RESn=0, all the I/O pads will receive all zeros, which will put them in digital input mode with the lowest-possible quiescent current. If the pins are allowed to float, though, they could get around the logic threshold and consume 50uA each. If they are all pulled lower high, total VIO current should be less than 1uA.
That 50uA is for 3v3 ?
Sounds like the best test is VDD powered and RESN=0 and light pulldowns on related io’s?
Then, various VIO ramps and current injection with light VIO current limiting can find how ‘sensitive’ this is ?
If VDD is powered and RESn=0, all the I/O pads will receive all zeros, which will put them in digital input mode with the lowest-possible quiescent current. If the pins are allowed to float, though, they could get around the logic threshold and consume 50uA each. If they are all pulled lower high, total VIO current should be less than 1uA.
That 50uA is for 3v3 ? YES
Sounds like the best test is VDD powered and RESN=0 and light pulldowns on related io’s?
Then, various VIO ramps and current injection with light VIO current limiting can find how ‘sensitive’ this is ?
Why are you actual test P2 V2 blop passed the VIO voltages 40% test of ON ?
Why are all the P2 not fried on the test ?
Because this type of limit test , tests an analog limit, & no two pins or die will have exactly the same limits. It seems the OnSemi test is a combination of Slew and Voltage and the custom P2 design features are not as high a limit as default digital designs, so some failed the test.
Less clear is what reduced test will pass with enough yields, and what latch up current specs can apply to the P2 ES2 die.
Done right, it's not a stress for the device under test nor the tester. In this case, have a current limit in play and you can push way past the voltage spec. A rule/spec is only that, the physical limits are always a lot further out. Although thermal specs are always something to pay full attention to.
The tester has hundreds of test probes so can have a probe for every pin pad, including the 32 individual GND pins. 128 total pin pads on the prop2 die. EDIT: That said, it looks like all the power and grounds have common rails on the jig, so those won't be individually programmable - https://forums.parallax.com/discussion/comment/1472576/#Comment_1472576
The ON boss said that he could get some kind of waiver on this test, in order to facilitate production. That would mean that this would be our final silicon. My gut is uneasy about that. What do you guys think?
When we call it "final', we must pay them $95k to transition the design to manufacturing mode. Meanwhile, another respin involving just the pad frame will cost $50k..$60k.
IIRC, quite some time ago, Ken Gracey wrote somewhere, that Parallax had already invested like $5m into P2 development. Adding another $50k would add 1% to that amount. That's one way to look at it, if your "gut is uneasy about" calling the design final despite that found failure condition. Other valid ways to look at it have been presented in the comments though.
So basically, if you have bypass caps on the chip it will tolerate 6v on VIO without damage?
It seems like their worst case VIO+40% testing is really sort of a corner worst case and doesn't reflect the real world.
If the silicon is 6v tolerant as-is with minimal bypassing, then I'd say run what you got for now and revisit the n-well guard rings in a later respin once you've made back some of the money spent on NRE (seems a little awkward to say "Recovered some of the NRE you spent").
It's probably unwise to have a deployed operating voltage that high.
Here's a graph of my earlier measurements with an extrapolation in brown. I'm not sure what would be considered as a base quiescent current, I'm guessing by the beginnings of a levelling out at the left there that some decent fraction of 1.0 uA would be it.
Comments
I would have expected the oscillator circuit to be the most sensitive to overvoltage damage ...
I would suppose so, too, but ON had trouble on V4447 and V0407. There was trouble elsewhere, too, but those pins burned the probe cards.
If you can see a dV/dT trigger, maybe quantify what slope is needed ? Some vendors with 5V tolerant spec that only with Vdd powered - ie something like Vdd+2,5V, which is suggesting a reverse stress point.
Not sure if P2 has similar VIO to VDD bias issues?
Ie it may be better to test with Vdd powered as long term use with Vdd=0 is less likely. I guess some power failures, or voltage removal watch dogs could briefly remove Vdd, but those are rare.
Did you try RC discharge via reverse diode clamp of pin with VIO = 4v (say) ?
That injects a current, similar to a ESD or Power connect spike.
EDIT2: Same story as V4855. If I ramp up through 0.7 Volts slower then the current is much higher. At the moment I'm sitting on 3.12 Volts and 171 uA for example. EDIT3: And now 1.0 V and 2.65 mA, continuing this one up to 2.0 V gives 7.4 mA.
If it's not all about that and just having a somewhat lower absolute maximum, then it's just FUD. Oh well. If we blow up our chip it's our fault for exceeding maximum.
Can you confirm if bad things happen if you feed all 4 signal pins on a VIO group 5.5 volts through a 1K resistor? Does that cause the latch up? If not, just ship it.
Do you know why the slope around 700mV has such persistent effects?
It might be good to pull the four related I/O's low, so that they can't float around the linear region and eat extra current.
EDIT: Oops, V4047 is only 1.2 volts itself, so some are full rail. Differing impedances too. A 3k3 resistor will pull a 970 mV pin40 right to zero volts but the moment the resister is removed the 970 mV is straight back in place. No impact on the V4047 current. Same 3k3 on pin42, which is at 334 mV, drops to 270 mV and straight back to 334 mV when removed.
The VIO logic powers up with DIR=0 and mode bits low, until the core logic powers up and changes it.
With VIO=1.2V, it seems like DIR=1, somehow. Maybe it didn't get a clean power-up. The mode bits could be scrambled, too, without the core powered to set things straight.
Or is RESN=L enough to init pincells ?
The slower you ramp up VIO, the less likely that capacitor bias in the level translator is going to have the intended effect, and the more likely you're going to wind up with some random state in each control bit. That has got to be what you are seeing.
No clock is needed.
RESn=0 will asynchronously reset the core logic which will reset the control signals going to each I/O pad. In Evans case, right now, the core is unpowered, so we are relying on the capacitor biases in the VDD-to-VIO level translators to give proper initialization of zeroes to the VIO-powered circuits.
Without the core powered, each level translator powers up in some random state, except DIR and the top five mode bits, which have bias caps to initialize them as lows. Slow enough VIO rise, though, will cause them to not clear reliably.
Even if the top five mode bits clear properly, the lower eight mode bits will still be random. With the top five bits low, setting up normal digital mode, the lower bits could possibly enable a current drive mode, which will turn on some current bias circuitry, which will draw continuous current.
The design assumes that all these cases of VIO and VDD not being simultaneously powered up or down are brief in duration.
Ok, I think you are saying sysclk is not needed but vDD is required for known-state outcome ?
Correct. I kept editing the post above to elaborate on this matter.
DOH!!! I'd left out the VDD jumper.
Sounds like the best test is VDD powered and RESN=0 and light pulldowns on related io’s?
Then, various VIO ramps and current injection with light VIO current limiting can find how ‘sensitive’ this is ?
That sounds like a good approach.
No. I will ask on Monday, though.
Why are you actual test P2 V2 blop passed the VIO voltages 40% test of ON ?
Why are all the P2 not fried on the test ?
Because this type of limit test , tests an analog limit, & no two pins or die will have exactly the same limits. It seems the OnSemi test is a combination of Slew and Voltage and the custom P2 design features are not as high a limit as default digital designs, so some failed the test.
Less clear is what reduced test will pass with enough yields, and what latch up current specs can apply to the P2 ES2 die.
So the tester test a part of the p2 till the tester blow itself with one defective P2?
Or the tester test lots of P2's till you have lots of P2 with zapped parts And have a sum of different P2 leak current, who's blow a test pin?
IIRC, quite some time ago, Ken Gracey wrote somewhere, that Parallax had already invested like $5m into P2 development. Adding another $50k would add 1% to that amount. That's one way to look at it, if your "gut is uneasy about" calling the design final despite that found failure condition. Other valid ways to look at it have been presented in the comments though.
It seems like their worst case VIO+40% testing is really sort of a corner worst case and doesn't reflect the real world.
If the silicon is 6v tolerant as-is with minimal bypassing, then I'd say run what you got for now and revisit the n-well guard rings in a later respin once you've made back some of the money spent on NRE (seems a little awkward to say "Recovered some of the NRE you spent").
Here's a graph of my earlier measurements with an extrapolation in brown. I'm not sure what would be considered as a base quiescent current, I'm guessing by the beginnings of a levelling out at the left there that some decent fraction of 1.0 uA would be it.