They are basically saying it's not up to their standards. But, they are also saying it's viable.
I have a few thoughts:
What does this transition to manufacturing mode mean? I would assume part of that is mothballing the design, move everything to an archive, etc... They can sort of "forget it" and move their limited attention onto other projects.
Say a revision is done in the future, say to produce another family part. (and that should be the only reason for a revision, or the waiver should not have been taken) What is that "wake up" cost?
At that time, a family part would have to be derived from this one, and that layout change could be done then too, prior to the family member being created. Validating it on this revision would make sense.
Given those costs are not insane, taking the waiver now could potentially fund this change with revenue from sales, not ongoing Parallax bootstrap investment.
That being worth it really depends on how robust the chips are. Having a known failure mode, well documented, with reference designs, etc... isn't a big deal, given that mode does not overlap common use case expectations.
Does it?
Seems a round of testing on the protos to come is warranted. People need to implement the chip in addition to testing on the established reference designs so far. Or, the next best thing would be to propose use cases and think through them looking for overlap with the known failure mode. We ended up doing that empirically with the P1 over time.
Are there some of us willing and able to do that? If so, it should happen.
Finally, had you known about the P1 limits early on, (PLL fail on overcurrent) would you have improved those parts of the design, or would you have considered it good enough?
On seems to be looking ahead, presenting their experience, and their standards given that experience, and you are seeing that in play right now. On also is saying if it's good enough, go to production.
The ON boss said that he could get some kind of waiver on this test, in order to facilitate production. That would mean that this would be our final silicon. My gut is uneasy about that. What do you guys think?
When we call it "final', we must pay them $95k to transition the design to manufacturing mode. Meanwhile, another respin involving just the pad frame will cost $50k..$60k.
My opinion is that anything that makes the chip more robust is a win. A one time cost of $60k when compared to the time and money already invested seems small, and will minimize future support issues somewhat. Of course it's not my money, so my opinion isn't that important [8^).
Though if you decide to crowd-fund this respin I would gladly contribute!
It may be convenient to launch the P2 now (with the known problem), because it may be that a few weeks later another problem is discovered, then and only then to get a modified version.
I'm thinking OnSemi just has a higher overvoltage spec than others...
Was just looking at Microchip PIC32MX1XX/2XX 28/36/44-PIN FAMILY and it's absolute maximum Vdd is only 4.0 V...
Where does this P2 go off the rails? Would a test to 4.0 V pass?
The ON boss said that he could get some kind of waiver on this test, in order to facilitate production. That would mean that this would be our final silicon. My gut is uneasy about that. What do you guys think?
When we call it "final', we must pay them $95k to transition the design to manufacturing mode. Meanwhile, another respin involving just the pad frame will cost $50k..$60k.
Supposing you stuck with the current design, how many customer chips could you replace for $50-60k? If it would be no more expensive to just unconditionally replace those that are accidentally fried, you build/reinforce a strong customer service reputation. Just a thought.
I’d get out as many of this batch of chips as possible. see if there are failures out of 100 chips being testing and pushed to the limits for a week. 0% failures would be a good indicator.
On the other hand: why not make the I/O-pins an ON-standard pin?
Because Propeller users are obsessed with video and we need the DACs to do that!
I translate: Parallax should offer ON to use the I/O structure of the propeller ][ with all the features like DAC-ADC-quadrature-++++ as a general purpose building block to use in their other products. These features will always be linked back to Parallax and hopefully others will find their way to the propeller. Why do we fear to make Rocklin great with great ideas?
Ah, that makes more sense. Sorry I misunderstood you!
I failures didn't start until 4.4 V, I'd just stick with what you have...
If they could lower the test voltage to 4.0 V, seems like it'd be all good...
This makes a lot of sense Rayman. Parallax customers are already experienced with the P8x32A having its 4v abs max, and I think would be happy and comfortable with that.
From here, I think the real question is whether there are any other minor (or major?) issues lurking, that haven't been uncovered yet.
Therefore it would be good to get these thousand ES2 dies packaged and out to people who are going to make things with P2, and get them on the road to actually making those prototypes, because thats when any remaining issues will be found.
There's a danger with declaring things 'almost final' that many will sit back and wait until things are 'truly final', and that inhibits finding those issues you really want found.
Seems like we have a target of selling $95k/$150 = 634 ES2 evaluation boards, to 'level-up' and get to production.
It looks like the slower the rise across 0.7 Volts, the steeper the slope becomes. A quick power up produces a current of less than 1.0 uA at 5.0 Volts.
EDIT: Reaches 1.0 uA at 5.27 Volts, and 2.0 uA at 5.63 Volts, and 3.0 uA at 5.80 Volts. EDIT2: 4.0 uA at 5.91 Volts, and 5.0 uA at 6.00 Volts, and 6.0 uA at 6.06 Volts, and 7.0 uA at 6.13 Volts, and 8.0 uA at 6.18 Volts. EDIT3: 10.0 uA at 6.26 Volts, and 20.0 uA at 6.53 Volts, and 30.0 uA at 6.69 Volts, and 40.0 uA at 6.80 Volts.
Are you not seeing any functional problems after 6.80V exposure? By the time you got that high, I imagine something had blown out along the way.
Done some serial echo and ADC measuring, all seems fine. GIO is around 1/6 full scale, with about 2% variation. VIO is around 5/6 full scale, with 4% variation.
EDIT: Floating pinA goes to 50% full scale on the ADCs, with about 4% variation.
EDIT2: I was wrong about the matching variations. I've deleted those comments.
EDIT3: DACs are operating as expected with a ramp.
The only thing I was thinking to change, aside from the guard rings, was the power-steering logic in the clock pad, so that VDD wouldn't draw 20mA extra if V2831 was held at GND. Right now, VDD will source current through a diode into V2831, which shouldn't pose any problems, as that diode will always be reverse-biased during normal operation. Holding V2831 to GND is a very strange thing to do, and is probably never going to happen. I just noticed the diode's effect on the tester plots, since the tester holds V2831 at GND for 3ms after raising VDD. This matter is probably of no real-world significance.
Ah, there was one other thing, actually. I've wanted to reduce the ADC's integrator cap to 1/8th its current value to help 1MHz+ input performance. I'm not sure, though, that maximum resolution wouldn't be reduced.
FWIW, my vote is to build as many boards as you have fresh silicon for and then turn the tigers loose on them. These chips will get close scrutiny and lots of dev time. If there are issues that force a re-spin, then offer these folks a deal on the respun silicon. Maybe a “ship us your board and $30 and we’ll return it to you with a respun chip”. If you did something like that, I bet you’d have 50+ orders before the sun rises in Rocklin on Monday. You’d definitely have mine!
Thats the thing. The ADC performance as it is already looks mighty handy. Increasing the bandwidth would also let more noise in, which has to be dealt with in filtering. While it would be nice to increase the BW I don't think its going to open up a whole bunch of new applications. Besides, I think prop fans enjoy the challenge of getting the most out of the available resources
Thats the thing. The ADC performance as it is already looks mighty handy. Increasing the bandwidth would also let more noise in, which has to be dealt with in filtering. While it would be nice to increase the BW I don't think its going to open up a whole bunch of new applications. Besides, I think prop fans enjoy the challenge of getting the most out of the available resources
The main bandwidth limiter is the analog front end of the ADC. The integrator cap size is just below that, in terms of being a bandwidth limiter. So, they are rather matched, as it is.
Get them out in the wild for real world testing - chips and boards as some of us want to build our boards
Pause a little before committing as a bit more info will help you decide. Probably they are just fine and you can go straight to production. But if something is found, or there are failures, then all can be fixed at one time if necessary.
I doubt a little pause will cause any loss of sales as you will have a number of chips from this run to fill the initial take-up.
Perhaps in the meantime work out with ON precisely just what changes need to be made. Maybe even get the basics done, ready for a later chip variant, just without proceeding to masks. Don't know how much this might cost but should be way cheaper without going to masks.
The ON boss said that he could get some kind of waiver on this test, in order to facilitate production. That would mean that this would be our final silicon. My gut is uneasy about that. What do you guys think?
When we call it "final', we must pay them $95k to transition the design to manufacturing mode. Meanwhile, another respin involving just the pad frame will cost $50k..$60k.
Get it like you want it, but don't let the perfect be the enemy of the good enough. If it requires a waiver, maybe the pad frame should be re-spun. I know that's not going to be a popular position around here. I want new silicon now too, but I would hate for it to not be as reliable as the P1.
I think these last few comments have been really good. Sleep on the current design for a while before making a decision. It would be great to see what the results and fall out are for the remaining 4 wafers. Remember the first one passed all the tests, the second one did not - looks like the tester, but it could have been a bad lot. Package the remaining chips and let us test and build stuff in the real world. That way you might find other issues that need to be corrected, if need be. Something like when I run the marathon - Trust in your training and Believe in yourself.
Got another slightly new behaviour. Using 6.25 Volt supply through the 300 ohm resistor, live jumpering it on and off of V4855 doesn't trigger any latch up but does draw more current (around 700 uA) than when I did the slow increments yesterday. Not a scary amount though.
I'm guessing the two ceramic capacitors are protecting V4855 from a trigger event while I'm using the 330 ohm resistor.
Got another slightly new behaviour. Using 6.25 Volt supply through the 300 ohm resistor, live jumpering it on and off of V4855 doesn't trigger any latch up but does draw more current (around 700 uA) than when I did the slow increments yesterday. Not a scary amount though.
I'm guessing the two ceramic capacitors are protecting V4855 from a trigger event while I'm using the 330 ohm resistor.
I wonder if that 700uA is from conduction between n-wells. Any way to determine if it's flowing from VIO to VDD?
I wonder if that 700uA is from conduction between n-wells. Any way to determine if it's flowing from VIO to VDD?
Always seems to be slope and rest voltage related. I just checked on the scope and the charging is around 2.0 V/ms and looks surprisingly linear until about 5.0 Volts.
EDIT: Here's me removing a short from V4855. Second image is zoomed in on the charge slope.
I wonder if that 700uA is from conduction between n-wells. Any way to determine if it's flowing from VIO to VDD?
Always seems to be slope and rest voltage related. I just checked on the scope and the charging is around 2.0 V/ms and looks surprisingly linear until about 5.0 Volts.
If you hold RESn low, VDD current should be very low. If you fed VDD via a resistor, you would be able to see it rise if it's being fed unexpected current from V4855.
I'm not powering VDD at all. I've checked VDD voltage on occasion with the multimeter and never seen it off zero while V4855 is at a set level. I'll put a scope probe on VDD now ...
I'm not powering VDD at all. I've checked VDD voltage on occasion with the multimeter and never seen it off zero while V4855 is at a set level. I'll put a scope probe on VDD now ...
EDIT: Nothing happening on VDD
I wonder if you'd see things behave differently if VDD was powered.
I think the most important thing to do is test the current silicon and update any errata as found. ON should have run this test on v1 (if it was a normal part of their test suite) and didn't. This was also not found with the other DRC fails that were fixed in the custom logic. This guard ring issue wasn't found until v2 which makes me ask how much of an issue it's really gotta be? There's a bunch of us exercising the ES1 that has the same fault as the current chip. The absolute max on P1 is 4v so comparable... Is 4v6 just their spec for stress test or is there something industry standard?
If I were Parallax I'd weigh all the options after the ES2 boards are for sale, with part of that being how fast the ES2 sells as well as yields. I'm just really surprised how this whole situation occurred. I guess this is the cost of using custom i/o logic instead of the standard libraries? Even so it seems short sighted to run such a brutal over-volt stress test that could possibly destroy thousands in test equipment without any sort of protection. If I were ON I'd be very embarrassed right now and heavily discount any sort of respin to fix this issue.
Oh, I've heard that multi-layer ceramics have a significantly variable voltage dependant capacitance. They apparently lose capacitance inverse to charge voltage. That could well explain the straightness of the charge slope.
I wonder if you'd see things behave differently if VDD was powered.
It doesn't seem to, not to the 6 Volts anyway. BTW, the current is more like 500 uA now but has been so for a while. I've not worked out why it was 700 uA initially but not since.
EDIT: I did find one bad jumper lead so maybe I had the power supply higher than 6.25 Volts and that clip was losing some. The readout on the bench power supply isn't accurate at all so I rely on the multimeters.
Thanks for checking all that, Evanh. I wonder why they are seeing failures at such low voltages, when you can take things up to 6V. Hey, do you dare try that on V4447? That's where ON saw trouble.
Comments
They are basically saying it's not up to their standards. But, they are also saying it's viable.
I have a few thoughts:
What does this transition to manufacturing mode mean? I would assume part of that is mothballing the design, move everything to an archive, etc... They can sort of "forget it" and move their limited attention onto other projects.
Say a revision is done in the future, say to produce another family part. (and that should be the only reason for a revision, or the waiver should not have been taken) What is that "wake up" cost?
At that time, a family part would have to be derived from this one, and that layout change could be done then too, prior to the family member being created. Validating it on this revision would make sense.
Given those costs are not insane, taking the waiver now could potentially fund this change with revenue from sales, not ongoing Parallax bootstrap investment.
That being worth it really depends on how robust the chips are. Having a known failure mode, well documented, with reference designs, etc... isn't a big deal, given that mode does not overlap common use case expectations.
Does it?
Seems a round of testing on the protos to come is warranted. People need to implement the chip in addition to testing on the established reference designs so far. Or, the next best thing would be to propose use cases and think through them looking for overlap with the known failure mode. We ended up doing that empirically with the P1 over time.
Are there some of us willing and able to do that? If so, it should happen.
Finally, had you known about the P1 limits early on, (PLL fail on overcurrent) would you have improved those parts of the design, or would you have considered it good enough?
On seems to be looking ahead, presenting their experience, and their standards given that experience, and you are seeing that in play right now. On also is saying if it's good enough, go to production.
That's my .02
My opinion is that anything that makes the chip more robust is a win. A one time cost of $60k when compared to the time and money already invested seems small, and will minimize future support issues somewhat. Of course it's not my money, so my opinion isn't that important [8^).
Though if you decide to crowd-fund this respin I would gladly contribute!
thanks,
Jonathan
Same
Was just looking at Microchip PIC32MX1XX/2XX 28/36/44-PIN FAMILY and it's absolute maximum Vdd is only 4.0 V...
Where does this P2 go off the rails? Would a test to 4.0 V pass?
Chip mentioned failures started from 35% over 3.3V, so about 4.4V
Supposing you stuck with the current design, how many customer chips could you replace for $50-60k? If it would be no more expensive to just unconditionally replace those that are accidentally fried, you build/reinforce a strong customer service reputation. Just a thought.
If they could lower the test voltage to 4.0 V, seems like it'd be all good...
This makes a lot of sense Rayman. Parallax customers are already experienced with the P8x32A having its 4v abs max, and I think would be happy and comfortable with that.
From here, I think the real question is whether there are any other minor (or major?) issues lurking, that haven't been uncovered yet.
Therefore it would be good to get these thousand ES2 dies packaged and out to people who are going to make things with P2, and get them on the road to actually making those prototypes, because thats when any remaining issues will be found.
There's a danger with declaring things 'almost final' that many will sit back and wait until things are 'truly final', and that inhibits finding those issues you really want found.
Seems like we have a target of selling $95k/$150 = 634 ES2 evaluation boards, to 'level-up' and get to production.
EDIT: Floating pinA goes to 50% full scale on the ADCs, with about 4% variation.
EDIT2: I was wrong about the matching variations. I've deleted those comments.
EDIT3: DACs are operating as expected with a ramp.
The only thing I was thinking to change, aside from the guard rings, was the power-steering logic in the clock pad, so that VDD wouldn't draw 20mA extra if V2831 was held at GND. Right now, VDD will source current through a diode into V2831, which shouldn't pose any problems, as that diode will always be reverse-biased during normal operation. Holding V2831 to GND is a very strange thing to do, and is probably never going to happen. I just noticed the diode's effect on the tester plots, since the tester holds V2831 at GND for 3ms after raising VDD. This matter is probably of no real-world significance.
Ah, there was one other thing, actually. I've wanted to reduce the ADC's integrator cap to 1/8th its current value to help 1MHz+ input performance. I'm not sure, though, that maximum resolution wouldn't be reduced.
The main bandwidth limiter is the analog front end of the ADC. The integrator cap size is just below that, in terms of being a bandwidth limiter. So, they are rather matched, as it is.
Package as many chips as you can - 500++???
Get them out in the wild for real world testing - chips and boards as some of us want to build our boards
Pause a little before committing as a bit more info will help you decide. Probably they are just fine and you can go straight to production. But if something is found, or there are failures, then all can be fixed at one time if necessary.
I doubt a little pause will cause any loss of sales as you will have a number of chips from this run to fill the initial take-up.
Perhaps in the meantime work out with ON precisely just what changes need to be made. Maybe even get the basics done, ready for a later chip variant, just without proceeding to masks. Don't know how much this might cost but should be way cheaper without going to masks.
Get it like you want it, but don't let the perfect be the enemy of the good enough. If it requires a waiver, maybe the pad frame should be re-spun. I know that's not going to be a popular position around here. I want new silicon now too, but I would hate for it to not be as reliable as the P1.
That's my $.02
I'm guessing the two ceramic capacitors are protecting V4855 from a trigger event while I'm using the 330 ohm resistor.
I wonder if that 700uA is from conduction between n-wells. Any way to determine if it's flowing from VIO to VDD?
EDIT: Here's me removing a short from V4855. Second image is zoomed in on the charge slope.
If you hold RESn low, VDD current should be very low. If you fed VDD via a resistor, you would be able to see it rise if it's being fed unexpected current from V4855.
EDIT: Nothing happening on VDD
I wonder if you'd see things behave differently if VDD was powered.
If I were Parallax I'd weigh all the options after the ES2 boards are for sale, with part of that being how fast the ES2 sells as well as yields. I'm just really surprised how this whole situation occurred. I guess this is the cost of using custom i/o logic instead of the standard libraries? Even so it seems short sighted to run such a brutal over-volt stress test that could possibly destroy thousands in test equipment without any sort of protection. If I were ON I'd be very embarrassed right now and heavily discount any sort of respin to fix this issue.
My 2c fwiw..
EDIT: I did find one bad jumper lead so maybe I had the power supply higher than 6.25 Volts and that clip was losing some. The readout on the bench power supply isn't accurate at all so I rely on the multimeters.