ON Semi figured out the VIO problem!!!!
cgracey
Posts: 14,153
in Propeller 2
I got a call today from the engineering boss at On Semi and he said they now realize what's triggering the latch-up destruction on VIO pins.
Their test technician, who Wendy and I have been working with, realized yesterday that in the test suite for the new silicon, an additional test had been added that wasn't (but should have been) in the test suite for the original silicon. It's a V-stress test which raises VDD and VIO voltages 40% above 1.8V and 3.3V. This is what's been blowing out the VIO pins!!! This indicates that there is some design weakness in the chip regarding latch-up immunity at higher voltages, which may incidentally occur in a customer application.
This is funny, because Wendy and I had asked in a dozen different ways if ANYTHING had changed in the test suite, aside from the updated digital test patterns, and the answer was always "no", to paraphrase. It just wasn't making sense, but the tester seemed to play a role. Anyway, the tester WAS blowing up the chips.
I'm relieved that we now know what the trouble is, but it's frustrating to have lost a month diagnosing this problem, and even more so that this V-stress test wasn't applied to the first-version silicon, as it would have resulted in awareness of a problem that would have been already fixed in this new silicon. The fix is just placing guard rings around several N-wells, which is no big deal. At this point, though, it means new masks and a wafer run.
So, they are going to be able to package us up a few hundred new chips in the Amkor package. It will take a few weeks, at least. We will be able to build new P2 Eval boards immediately. They had tested two wafers out of six, before stopping after both probe cards had sustained damage to VIO pins. Many of those dies are now toast. They will need to re-probe those wafers, checking for excessive VIO current, or just probe virgin wafers which haven't been exposed to the V-Stress test, in order to get dies to send to Amkor for packaging.
I'm really glad that we know what the problem is now.
Their test technician, who Wendy and I have been working with, realized yesterday that in the test suite for the new silicon, an additional test had been added that wasn't (but should have been) in the test suite for the original silicon. It's a V-stress test which raises VDD and VIO voltages 40% above 1.8V and 3.3V. This is what's been blowing out the VIO pins!!! This indicates that there is some design weakness in the chip regarding latch-up immunity at higher voltages, which may incidentally occur in a customer application.
This is funny, because Wendy and I had asked in a dozen different ways if ANYTHING had changed in the test suite, aside from the updated digital test patterns, and the answer was always "no", to paraphrase. It just wasn't making sense, but the tester seemed to play a role. Anyway, the tester WAS blowing up the chips.
I'm relieved that we now know what the trouble is, but it's frustrating to have lost a month diagnosing this problem, and even more so that this V-stress test wasn't applied to the first-version silicon, as it would have resulted in awareness of a problem that would have been already fixed in this new silicon. The fix is just placing guard rings around several N-wells, which is no big deal. At this point, though, it means new masks and a wafer run.
So, they are going to be able to package us up a few hundred new chips in the Amkor package. It will take a few weeks, at least. We will be able to build new P2 Eval boards immediately. They had tested two wafers out of six, before stopping after both probe cards had sustained damage to VIO pins. Many of those dies are now toast. They will need to re-probe those wafers, checking for excessive VIO current, or just probe virgin wafers which haven't been exposed to the V-Stress test, in order to get dies to send to Amkor for packaging.
I'm really glad that we know what the problem is now.
Comments
No need to resynthesize. The core is fine.
This turn will just be some GDS changes to the custom pad frame elements.
So, no tool impact.
Yeah, it was impossible without the information that the V-stress test was in use. We had asked in so many ways, in excruciating detail, to discover this, but the test technician wasn't aware of it, himself, so we couldn't get any affirmation that anything unexpected was going on.
C.W.
I didn't believe that substrate resistance stuff...
The old ones where $150.
https://www.parallax.com/product/64000-es
I suppose that would be nice...
Well, it will be production tested to 4.62V. A design improvement might make it much better than that, but it will only be tested at ON Semi to 4.62V. Once we get new silicon, I will do some destructive checks to see where the limit is.
I think we will sell the new ones for $150, again.
Bean
I wonder how much delay to full production this change will introduce?
Do you need to wait to get the remaining working P2's from this latest run packaged and sent out and tested by others to find any other remaining unknown issues before you commit to the next respin, or does it all go in parallel?
Kind regards, Samuel Lourenço
It is still the substrate problem, that's why the guard rings are needed. Chip is just pointing that there was a undocumented testing change that started highlighting, in a severe way, the real problem.
I assume the re-spin with this fix will still be a few months time before we have "new new" chips...
That seems like a pretty brutal test to me...
Meanwhile, I asked him about the ESD test, which the chip passed. He said it passed the 4kV human body model and 2kV machine model, which is good.
All the new features seem to work. We are going to send you a new-silicon P2 Eval Rev B on Monday, actually. Ersmith, EvanH, Peter, and a few others will be getting one, too. Hopefully, if there are any logic errors, you guys will discover them pretty soon. I am working on the documentation, again, so things will be ready.
The Propeller is the result of careful thinking both of an individual, of individuals and of the community. Thats great.
It’s a bit embarrassing for ON. Hopefully they’ll push the fixes thru quickly.
Meanwhile you can get some more chips/boards out into more hands.
Seems like they have set this limit, based on what designs usually can tolerate.
It could be useful to know where the present limit is, to give rules around ES2 use, and to find what gains are actually made by the changes.
The way Nuvoton and Atmel spec is to give ESD kV like that, and latch up MAX injection currents and some absolute max values for Vdd/VIO, which are not usually as high as +40% on nominal.
Users would not expect VIO to suddenly change, but they can expect ESD events and if enough current is also injected, that can trigger Usually high VIO impulse is a secondary outcome of a ESD event, it is not ‘operational’ or static.
I would be curious to nail down existing limit values before hitting a revise button.
Ie the failure trigger is not what anyone would consider normal use ?
They just tested a bunch of Rev A chips they had on hand, gradually increasing the VDD and VIO voltages until they started seeing VIO failures at +35%. That is our current baseline.
The absolute-maximum rating in the data sheet will be much lower than that, of course.
My understanding is that this V-stress test is part of their standard testing.