Does this mean ON don’t need to redo the verilog? ie it’s only a change to those outer ring parts and that can be done without other changes?
I presume the answer is yes, and that should be a simple and quick respin. And the speed you’re getting will stay!
Right. No need to resynthesize. We just need to add these guardbars to prevent latch-up.
Chip,
Regarding the concern about PLL speed. I'm pretty sure it wasn't the PLL causing the limit. My testing of the v1 silicon indicates the PLL can go faster in that design than even the top sysclock frequency you were getting on the v2 silicon. My conclusion is the sysclock speed limit is the core logic/RAM. Same as v1 silicon. You got a small sysclock increase over v1 just because lower wattage.
And you have already tweaked the PLL speed for the v2 silicon. I posted a link a while back where you stated so.
I've proven the PLL can go faster than 390 MHz, even on v1 silicon, by using XDIVP = 2 (%PPPP = 0). This way the sysclock is half the PLL and therefore keeps the core logic from limiting the measurement.
If all pins on the chip are floating and VDD starts to rise from 0V, where is all that current flowing? By the way, the 65% decay period on that current spike is about 10us. That 75mA is flowing ...
470nF and a peak dV slope of 2V in 12.5us, will give a peak current of ~75mA.
I've proven the PLL can go faster than 390 MHz, even on v1 silicon, by using XDIVP = 2 (%PPPP = 0). This way the sysclock is half the PLL and therefore keeps the core logic from limiting the measurement.
Thanks. Here it is:
I remember changing the VCO inverters' gate lengths while I was editing the layout, before I turned it over to ON Semi. Later, they massaged the layout to work with their tools and I had them change the filter resistor settings, which improved the PLL in the new silicon. I need to get the layout database from them so I'll have the latest layout on my end.
Anyway, I can give the PLL impossibly-high-frequency settings and it goes as fast as it can and becomes temperature dependent, since it can't lock. This makes me think that the VCO divider is faster than the VCO, which is better than the opposite, since things top out safely.
I wasn't clear, at all. Those VCO inverters' gate lengths were changed BEFORE the v1 silicon, while the PLL filter resistor settings were changed before the v2 silicon. So, the VCO inverters are the same as they've ever been. Sorry about that.
@cgracey Would the "re-work" at OnSemi allow for the ROM code to be updated, without additional change/cost ?
It doesn't sound like it does, but I will naively ask anyway! Reason being... I thought Cluso had mentioned a while back, that there was a final version of the ROM that didn't quite make the deadline before the last spin. Something to do with improving the way a certain SD card IO gets released, so that Flash can be accessed on the same bus without a power-cycle.
... this change they are going to make will probably only involve metal1 (m1), among all the metal layers, so not that much will be possible.
If it is that simple, and a known issue, you sort of wonder why there are not DRC checks to flag this ? - and even semi automated adding guardbars/rings ?
If all pins on the chip are floating and VDD starts to rise from 0V, where is all that current flowing? By the way, the 65% decay period on that current spike is about 10us. That 75mA is flowing ...
470nF and a peak dV slope of 2V in 12.5us, will give a peak current of ~75mA.
Jmg, you once figured out about what the total nodal (gate) capacitance on the chip was, based on the first silicon. I think you used P = F*C*V^2. What capacitive value did you arrive at?
But you can see that 75mA surge starts when VDD=0 volts. That doesn't make sense to me. I would think the charging current would look like a gentle hump that rises and then falls.
Chip,
Regarding the concern about PLL speed. I'm pretty sure it wasn't the PLL causing the limit. My testing of the v1 silicon indicates the PLL can go faster in that design than even the top sysclock frequency you were getting on the v2 silicon. My conclusion is the sysclock speed limit is the core logic/RAM. Same as v1 silicon. You got a small sysclock increase over v1 just because lower wattage.
And you have already tweaked the PLL speed for the v2 silicon. I posted a link a while back where you stated so.
Here is the speed test I use:
dat org
loop drvnot #0 'toggle P0 at 1/1000th the clock frequency
waitx #500-8
jmp #loop
You can set the PLL to an impossibly high speed and it tops out around 390MHz on the new silicon, as evidenced by the non-locked, drifting, 390KHz observed on P0 using this program. The HUBSET instructions are missing, as you see.
Jmg, you once figured out about what the total nodal (gate) capacitance on the chip was, based on the first silicon. I think you used P = F*C*V^2. What capacitive value did you arrive at?
The equivalent Cpd of the ES1 silicon was in the order of 1.6nF for the clock trees.
But you can see that 75mA surge starts when VDD=0 volts. That doesn't make sense to me. I would think the charging current would look like a gentle hump that rises and then falls.
Current is set by the slope viz i = C*dV/dT, so it will be a fast step to some value set by CL, and Slew, and then as slew falls, so too does the current.
They may simply have a total ballpark of ~470nF decoupling on the test head. (in which case it will not change much with empty socket)
Jmg, you once figured out about what the total nodal (gate) capacitance on the chip was, based on the first silicon. I think you used P = F*C*V^2. What capacitive value did you arrive at?
The equivalent Cpd of the ES1 silicon was in the order of 1.6nF for the clock trees.
But you can see that 75mA surge starts when VDD=0 volts. That doesn't make sense to me. I would think the charging current would look like a gentle hump that rises and then falls.
Current is set by the slope viz i = C*dV/dT, so it will be a fast step to some value set by CL, and Slew, and then as slew falls, so too does the current.
They may simply have a total ballpark of ~470nF decoupling on the test head. (in which case it will not change much with empty socket)
Ay, ay, ay! I see what you are saying. Current is C times the slope of the voltage. I just did a simulation to show this, too. That makes sense now. Thanks for explaining that. I've been asking ON for a week to explain why those current spikes are there, but now I see they are just the bypass caps on the test board. Kind of embarrassing.
I wasn't clear, at all. Those VCO inverters' gate lengths were changed BEFORE the v1 silicon, while the PLL filter resistor settings were changed before the v2 silicon. So, the VCO inverters are the same as they've ever been. Sorry about that.
I wasn't clear, at all. Those VCO inverters' gate lengths were changed BEFORE the v1 silicon, while the PLL filter resistor settings were changed before the v2 silicon. So, the VCO inverters are the same as they've ever been. Sorry about that.
The resistors don't affect PLL speed?
No. They affected the PLL 2nd-order RC filter that enables the PLL to lock.
@cgracey Would the "re-work" at OnSemi allow for the ROM code to be updated, without additional change/cost ?
It doesn't sound like it does, but I will naively ask anyway! Reason being... I thought Cluso had mentioned a while back, that there was a final version of the ROM that didn't quite make the deadline before the last spin. Something to do with improving the way a certain SD card IO gets released, so that Flash can be accessed on the same bus without a power-cycle.
IIRC I fixed all but one hole where it could escape the foolproof release of DO. I don’t think it’s important.
From what i recall, the ROM is not a mask layer so changing is not a cheap solution.
@cgracey Would the "re-work" at OnSemi allow for the ROM code to be updated, without additional change/cost ?
It doesn't sound like it does, but I will naively ask anyway! Reason being... I thought Cluso had mentioned a while back, that there was a final version of the ROM that didn't quite make the deadline before the last spin. Something to do with improving the way a certain SD card IO gets released, so that Flash can be accessed on the same bus without a power-cycle.
IIRC I fixed all but one hole where it could escape the foolproof release of DO. I don’t think it’s important.
From what i recall, the ROM is not a mask layer so changing is not a cheap solution.
When I find out which layers are changing, I'll post it.
"substrate resistivity, which varies by ... location on the wafer."
Is this a real thing? I think they might have made this part up...
Well, it can vary by location on the wafer. Maybe it doesn't if the wafer is very consistent. I don't think they made it up. My gut feeling, anyway, is that they are straight shooters and pretty smart.
I assume there a first blanket deep doping that makes the substrate. Unevenness in this doping will create variation in resistance even in what is a pure crystal. EDIT: Or maybe more accurately, imperfection in the surface polish will affect absorption speed/distribution of the doping gas.
If by "substrate", they mean the wafer that they started from, grown from melt, I've not heard of there being a variation in the resistivity... It's hard to imagine. I've only seen one number for the resistivity of a wafer... But, that was a long time ago and with small wafers...
Will the guard rings around M1 and M4 be redesigned?
Anyway, this is an important find.
Kind regards, Samuel Lourenço
They don't think it's necessary. Only a guardband (not even a guardring) separating some N-wells is their recommendation.
One can never be too cautious. Beau raised attention on a potential issue, that I'm hoping it doesn't turn out to be real. On the other hand, if the extra guard rings reduce the pin bandwidth, it is better to leave that option out.
If by "substrate", they mean the wafer that they started from, grown from melt, I've not heard of there being a variation in the resistivity... It's hard to imagine. I've only seen one number for the resistivity of a wafer... But, that was a long time ago and with small wafers...
I have given my two cents already but ON semi saying "They don't think it's necessary" does not settle well with me. You don't plan a long trip without looking to see how much gas is in the car "thinking" you might have enough to get there do you? ... this is a long trip.
When I was working for National Semiconductor, rings were always insisted upon over bars or strips because of fringing effects that can occur. One ring isn't enough either since you can't completely isolate the PNPN or NPNP parasitic SCR device that occurs with a simple inverter structure. You must instantiate a minimum of two rings with ESD devices. I worked side by side with a guy who was the lead ESD design engineer and might have picked up a thing or two.
When you and I sat down with the recommended 180nm TSMC design rules for ESD structures and ironed out what was to be implemented, we had applied the three structures I mentioned in an earlier post. Even if you had to re-do everything, the layout model we created would have been a good guideline to follow.
Either way, with rings or bars, you will need more than just M1 in the respin to correct the problem. ... M1, Contacts, NWELL, P+, and N+
Beau, I agree that full rings would be optimal. I suppose ON Semi thinks that, too, but they are trying to see if this can be done economically.
They have some carreer ESD guys on staff that have been through lots of trials and errors in developing their own I/O libraries. So, they know what they can get away with.
I've asked, but haven't gotten word back, yet, about how many reticles they are thinking need to rebuilt.
We'll hear something soon.
They also need to complete ESD testing on the first silicon, since they have the full test suite for that version working. That should be done before we call things final.
Comments
Right. No need to resynthesize. We just need to add these guardbars to prevent latch-up.
Regarding the concern about PLL speed. I'm pretty sure it wasn't the PLL causing the limit. My testing of the v1 silicon indicates the PLL can go faster in that design than even the top sysclock frequency you were getting on the v2 silicon. My conclusion is the sysclock speed limit is the core logic/RAM. Same as v1 silicon. You got a small sysclock increase over v1 just because lower wattage.
And you have already tweaked the PLL speed for the v2 silicon. I posted a link a while back where you stated so.
I've proven the PLL can go faster than 390 MHz, even on v1 silicon, by using XDIVP = 2 (%PPPP = 0). This way the sysclock is half the PLL and therefore keeps the core logic from limiting the measurement.
470nF and a peak dV slope of 2V in 12.5us, will give a peak current of ~75mA.
Thanks. Here it is:
I wasn't clear, at all. Those VCO inverters' gate lengths were changed BEFORE the v1 silicon, while the PLL filter resistor settings were changed before the v2 silicon. So, the VCO inverters are the same as they've ever been. Sorry about that.
It doesn't sound like it does, but I will naively ask anyway! Reason being... I thought Cluso had mentioned a while back, that there was a final version of the ROM that didn't quite make the deadline before the last spin. Something to do with improving the way a certain SD card IO gets released, so that Flash can be accessed on the same bus without a power-cycle.
If it is that simple, and a known issue, you sort of wonder why there are not DRC checks to flag this ? - and even semi automated adding guardbars/rings ?
Jmg, you once figured out about what the total nodal (gate) capacitance on the chip was, based on the first silicon. I think you used P = F*C*V^2. What capacitive value did you arrive at?
But you can see that 75mA surge starts when VDD=0 volts. That doesn't make sense to me. I would think the charging current would look like a gentle hump that rises and then falls.
Here is the speed test I use:
You can set the PLL to an impossibly high speed and it tops out around 390MHz on the new silicon, as evidenced by the non-locked, drifting, 390KHz observed on P0 using this program. The HUBSET instructions are missing, as you see.
Current is set by the slope viz i = C*dV/dT, so it will be a fast step to some value set by CL, and Slew, and then as slew falls, so too does the current.
They may simply have a total ballpark of ~470nF decoupling on the test head. (in which case it will not change much with empty socket)
Ay, ay, ay! I see what you are saying. Current is C times the slope of the voltage. I just did a simulation to show this, too. That makes sense now. Thanks for explaining that. I've been asking ON for a week to explain why those current spikes are there, but now I see they are just the bypass caps on the test board. Kind of embarrassing.
The resistors don't affect PLL speed?
PS: I've now used your code and got a result of 404 MHz (and dropping to 402 MHz as it heats) for the max PLL frequency on the v1 silicon.
Here's the full source: EDIT: Corrected the 100 ms pause.
No. They affected the PLL 2nd-order RC filter that enables the PLL to lock.
IIRC I fixed all but one hole where it could escape the foolproof release of DO. I don’t think it’s important.
From what i recall, the ROM is not a mask layer so changing is not a cheap solution.
When I find out which layers are changing, I'll post it.
Will the guard rings around M1 and M4 be redesigned?
Anyway, this is an important find.
Kind regards, Samuel Lourenço
They don't think it's necessary. Only a guardband (not even a guardring) separating some N-wells is their recommendation.
At about every ~14 C increase, it goes 10MHz slower.
Is this a real thing? I think they might have made this part up...
Well, it can vary by location on the wafer. Maybe it doesn't if the wafer is very consistent. I don't think they made it up. My gut feeling, anyway, is that they are straight shooters and pretty smart.
Kind regards, Samuel Lourenço
As far as I know, the wafers are doped in the initial state... OK, google found: https://universitywafer.com/n-type-silicon.html it for me.
I have given my two cents already but ON semi saying "They don't think it's necessary" does not settle well with me. You don't plan a long trip without looking to see how much gas is in the car "thinking" you might have enough to get there do you? ... this is a long trip.
When I was working for National Semiconductor, rings were always insisted upon over bars or strips because of fringing effects that can occur. One ring isn't enough either since you can't completely isolate the PNPN or NPNP parasitic SCR device that occurs with a simple inverter structure. You must instantiate a minimum of two rings with ESD devices. I worked side by side with a guy who was the lead ESD design engineer and might have picked up a thing or two.
When you and I sat down with the recommended 180nm TSMC design rules for ESD structures and ironed out what was to be implemented, we had applied the three structures I mentioned in an earlier post. Even if you had to re-do everything, the layout model we created would have been a good guideline to follow.
Either way, with rings or bars, you will need more than just M1 in the respin to correct the problem. ... M1, Contacts, NWELL, P+, and N+
They have some carreer ESD guys on staff that have been through lots of trials and errors in developing their own I/O libraries. So, they know what they can get away with.
I've asked, but haven't gotten word back, yet, about how many reticles they are thinking need to rebuilt.
We'll hear something soon.
They also need to complete ESD testing on the first silicon, since they have the full test suite for that version working. That should be done before we call things final.