Fingers crossed here!
Any words are better than no word at all.
I hope the problem is just something on one wafer. I don't know if they've figured anything out, yet. It might just be a meeting about how they're going to proceed to investigate the cause of the problem, and in what way they'll permit me to help.
Fingers and toes crossed... The more formal these things are, the less likely it is to be good news..
Fingers crossed here!
Any words are better than no word at all.
I hope the problem is just something on one wafer. I don't know if they've figured anything out, yet. It might just be a meeting about how they're going to proceed to investigate the cause of the problem, and in what way they'll permit me to help.
Fingers and toes crossed... The more formal these things are, the less likely it is to be good news..
Exactly!
I'm a little worried about something like that. I do have a perfectly-working chip, though. So, it seems the reticles are good.
They don't have a current-limited test to run, yet, so I don't think they have been able to test any more wafers since the probe cards were damaged.
They have noticed that the hot spots are occurring near the VIO and GIO pins, which contain these circuits:
It seems that Circuit A, which is an ESD clamp, is passing current from Vgs=0, through M4. Of course, that shouldn't be possible, but it looks like it's always turned on, without even any bias.
They are going to build some open-cavity chips into packages and test them. We are needing to see if these failures are always in the same circuits. Seems to me, that's the case.
This could take a month, they think, because they need to order new exposed-pad 100-pin packages.
So, after all, this might be an issue related with the design? Or facilitated by it under certain conditions?
Kind regards, Samuel Lourenço
I don't think it's the design, because this same circuit was fabricated in the original V1 silicon and there was no issue. I even have a new V2 silicon chip on my desk that works fine. It looks to me like some manufacturing defect that was widespread for some reason in the V2 silicon.
So, after all, this might be an issue related with the design? Or facilitated by it under certain conditions?
Kind regards, Samuel Lourenço
I don't think it's the design, because this same circuit was fabricated in the original V1 silicon and there was no issue. I even have a new V2 silicon chip on my desk that works fine. It looks to me like some manufacturing defect that was widespread for some reason in the V2 silicon.
I hope that it is the latter. But what could cause this issue? A malformed transistor B pulling the gate of A? Or a malformed transistor A itself?
So, after all, this might be an issue related with the design? Or facilitated by it under certain conditions?
Kind regards, Samuel Lourenço
I don't think it's the design, because this same circuit was fabricated in the original V1 silicon and there was no issue. I even have a new V2 silicon chip on my desk that works fine. It looks to me like some manufacturing defect that was widespread for some reason in the V2 silicon.
I hope that it is the latter. But what could cause this issue? A malformed transistor B pulling the gate of A? Or a malformed transistor A itself?
Yeah, I wonder the same things. Maybe there was even a dopant problem, because M4 seems to always be on, in some VIO pins.
So, after all, this might be an issue related with the design? Or facilitated by it under certain conditions?
Kind regards, Samuel Lourenço
I don't think it's the design, because this same circuit was fabricated in the original V1 silicon and there was no issue. I even have a new V2 silicon chip on my desk that works fine. It looks to me like some manufacturing defect that was widespread for some reason in the V2 silicon.
I hope that it is the latter. But what could cause this issue? A malformed transistor B pulling the gate of A? Or a malformed transistor A itself?
Yeah, I wonder the same things. Maybe there was even a dopant problem, because M4 seems to always be on, in some cases.
Maybe I'm playing Devil's advocate here, and I don't wish to. But if it is a dopant problem, wouldn't this affect the core logic as well? But so far, this issue was isolated to the individual IOs, right? And if it is an ESD issue after all? Not a latch-up, but some ESD event piercing the gate isolation of transistor B, causing A to be pulled up? Or transistor A itself being damaged, I don't know.
If GIO and VSS are to be bonded together only during/after the packaging of the die, is there any chance that ESD is jumping across GIO to VSS during testing? Only the weakest gate isolation could be affected, and after that, a disharge path would be formed. That discharge path could be formed on any pin, explaining the randomness, and also why only one pin fails at a time (the new discharge path protects other pins, acting as a clamping diode or as a low resistance path).
Of course this is a wild shot in the very dark, from someone who knows nothing about micro-electronics (me), so bare with me Chip. I have a 99% chance of being absolutely wrong.
For manufacturing defect, since it affects random pins I'd think maybe a mask got contaminated with dust. A registration error, focus problem, doping defect or etching goof would probably affect everything across the wafer more consistently.
It seems that Circuit A, which is an ESD clamp, is passing current from Vgs=0, through M4. Of course, that shouldn't be possible, but it looks like it's always turned on, without even any bias.
Didn't OnSemi design the ESD sections ? ISTR some respins around ESD handling of the PAD
It's quite weird only some fail, and also weird they fail apparently as a resistor. Is there is a G-D filament, then the resistance would be non linear at < 500mV
Can you check a failed part, with no VDD applied - maybe that unexplained lateral current that seems to flow Vdd -> VIO, is enough to bias the ESD fet ?
If you can plot I-V on a failed pin, and compare with Spice on that MOSFET with (eg) D-G shorted that could help suggest failure mechanisms ?
Wasn't it just 1 out of 3 wafers that had this problem?
And, only on the edges?
I've not seen any info on follow up lower-initial current tests that were planned, I think those are not done yet, until they figure out the cause.
If the locations vary across all wafers, that rather excludes a fixed damaged photo-mask error.
When they ran ESD tests, I wonder how similar the ESD failures measure to this failure ?
It seems that Circuit A, which is an ESD clamp, is passing current from Vgs=0, through M4. Of course, that shouldn't be possible, but it looks like it's always turned on, without even any bias.
Didn't OnSemi design the ESD sections ? ISTR some respins around ESD handling of the PAD
It's quite weird only some fail, and also weird they fail apparently as a resistor. Is there is a G-D filament, then the resistance would be non linear at < 500mV
Can you check a failed part, with no VDD applied - maybe that unexplained lateral current that seems to flow Vdd -> VIO, is enough to bias the ESD fet ?
If you can plot I-V on a failed pin, and compare with Spice on that MOSFET with (eg) D-G shorted that could help suggest failure mechanisms ?
The V2 chip on my desk has a single bad VIO that measures 91 ohms without power. At 3.3V, it passes 29mA quiescent current, which is a little less than 3.3V/(91 ohms), but probably due to conduction loss from self-heating.
I designed these ESD circuits and ON Semi reviewed them in a meeting, prior to V1 silicon tapeout, and figured they were okay. They worked fine on V1, but now seem to be continuously conducting in some cases.
Wasn't it just 1 out of 3 wafers that had this problem?
And, only on the edges?
I've not seen any info on follow up lower-initial current tests that were planned, I think those are not done yet, until they figure out the cause.
If the locations vary across all wafers, that rather excludes a fixed damaged photo-mask error.
When they ran ESD tests, I wonder how similar the ESD failures measure to this failure ?
On Semi no longer wants to develop the resistance test that their test engineer and I were going to work on, since they feel it represents too great a risk to the probe cards. I think it would be safe, myself. So, we are waiting to see what the open-cavity chips reveal. My big question is whether or not it's always "Circuit A" that causes the trouble.
Were they found at some random distribution, or did the misbehaving M4 Nmos devices more likelly to be at two opposing sides of the malfunctioning dies?
Were they found at some random distribution, or did the misbehaving M4 Nmos devices more likelly to be at two opposing sides of the malfunctioning dies?
Not sure, yet. They've apparently seen a few cases of this on V4447. One of the probe cards also had its V0407 pin damaged.
On Semi no longer wants to develop the resistance test that their test engineer and I were going to work on, since they feel it represents too great a risk to the probe cards. I think it would be safe, myself. So, we are waiting to see what the open-cavity chips reveal. My big question is whether or not it's always "Circuit A" that causes the trouble.
Hmm, that seems extremely conservative of them, but sounds like they may review, after the open cavity packages tests.
The V2 chip on my desk has a single bad VIO that measures 91 ohms without power. At 3.3V, it passes 29mA quiescent current, which is a little less than 3.3V/(91 ohms), but probably due to conduction loss from self-heating.
I designed these ESD circuits and ON Semi reviewed them in a meeting, prior to V1 silicon tapeout, and figured they were okay. They worked fine on V1, but now seem to be continuously conducting in some cases.
A typical meter might inject 1mA, which is 91mV drop for the ohms test, so well below any gate threshold. (excludes G-D filaments?)
It's not easy to turn an enhancement mode mosfet into a pure resistor ?
Do you have the artwork layers for ES1 and ES2 to compare, and how close those ESD fets physically are to each of their PAD areas that are probed ?
On Semi no longer wants to develop the resistance test that their test engineer and I were going to work on, since they feel it represents too great a risk to the probe cards. I think it would be safe, myself...
Hurm ... The purpose of the low current resistance test is to protect the equipment against repeat of the prior damage. In fact it's a little surprising it doesn't already protect itself in this manner given the reasonable probability of unexpected shorts at some stage in mass testing like this.
It seems to me that On Semi are making excuses for something else if that's the actual reason they gave. The reason, on its own, appears illogical.
It seems to me that On Semi are making excuses for something else if that's the actual reason they gave. The reason, on its own, appears illogical.
You mean, like the test team move to brush the blame under the carpet of the manufacturing team, who seek to brush the blame under the carpet of the design team........ etc.. etc..
Seems all that effort damages communication and delays getting stuff fixed, but hopefully behind all that stuff the solution has been identified and they are moving fast to provide the right solution.
Customers want chips ! With the resolution comes the solution.
(Not withstanding the point about test current limiting- does seem peculiar that a simple continuity/resistance test isn't standard before pumping test-probe melting high current into any wafer, for any customer. Although maybe OnSemi have a good reason for that; perhaps they would rather pay the cost of a few probe repairs in the low-occurrence cases of "manufacturing" defects, than spend more time on testing each part. Even so, I would have thought it typical to use a voltage source that limits current below the melting point of a >$2000 probe! Such is the view from this window, far far away.)
Well, they are going to have to implement some kind of resistance check before power up, before they use the probe card again. I think they just want to try to discover more about the nature of the problem before they get back into that. The decision to not develop the test immediately might have to do with using their test engineer's time on other things, for now.
Your circuit "A" does not seem correct to me.
Assuming on power up that the "capacitor" (M1) is discharged, then every time power is applied M4 will conduct until M1 is charged through R1.
A second note ... your mention on the schematic "On PAD_GIO, this is GIO, not VIO." ... How are you conveying that in the schematic so that it meets up properly in layout? .... If this got mixed up somehow and GIO happens to be VIO in the wrong location, then it wouldn't matter if M4 was turned on or not.
Do you happen to have a layout view of this particular ESD section?
There are two main things that should be in place for ESD protection, and three if you want to go over redundant.
1) An NMOS and/or PMOS with the gates tied to their respective Source ... This clamps on a negative ESD voltage spike.
2) An RC configuration (similar to what you have), but instead of threshold switching it relies on the Zener effect of the transistor to switch when the voltage is above a certain level. ... This ensures that there is no clamping under normal voltage conditions and positive ESD voltage spikes will be properly handled.
3) Is a "comb" structure with proper spacing between points which must create a breakdown voltage higher than the operating voltage. ...This acts as a "spark gap" and will clamp both positive and negative ESD voltage spikes.
Your circuit "A" does not seem correct to me.
Assuming on power up that the "capacitor" (M1) is discharged, then every time power is applied M4 will conduct until M1 is charged through R1.
Only a sharp rise on VIO will cause conduction through M4. That 210.9K resistor and the M1 gate cap have an RC time constant of 211k * 9pF = 1.9us. System VIO usually rises in 1ms, or much more, so that circuit never turns on, normally. If you get an ESD spike that has a rise time of 2ns, that thing will definitely turn on, for maybe >1us.
A second note ... your mention on the schematic "On PAD_GIO, this is GIO, not VIO." ... How are you conveying that in the schematic so that it meets up properly in layout? .... If this got mixed up somehow and GIO happens to be VIO in the wrong location, then it wouldn't matter if M4 was turned on or not.
The only difference between the VIO and GIO pad schematics is in what the pad metal connects to (VIO or GIO). I just didn't want to post two nearly-identical schematics with only one subtle difference. I was worried it would cause wasted effort in the person wanting to understand the pad schematics.
Do you happen to have a layout view of this particular ESD section?
I attached a picture. It is M4 that is apparently getting hot, but conducting current from VIO>0, without VIO ever needing to hit the threshold voltage. Very weird.
There are two main things that should be in place for ESD protection, and three if you want to go over redundant.
1) An NMOS and/or PMOS with the gates tied to their respective Source ... This clamps on a negative ESD voltage spike.
This was done better on each I/O pad by having dedicated diode arrays that clamp the I/O pin to VIO and GIO. The VIO and GIO pads just have VSS-to-GIO clamps and over-voltage protection.
2) An RC configuration (similar to what you have), but instead of threshold switching it relies on the Zener effect of the transistor to switch when the voltage is above a certain level. ... This ensures that there is no clamping under normal voltage conditions and positive ESD voltage spikes will be properly handled.
Circuit A achieves the same thing. It should never turn on during power-up, due to bypass charging and supply impedance limits. Even it does turn on, it will be off in another 1us to 2us.
3) Is a "comb" structure with proper spacing between points which must create a breakdown voltage higher than the operating voltage. ...This acts as a "spark gap" and will clamp both positive and negative ESD voltage spikes.
This, we don't have.
We did a pretty exhaustive review at ON Semi of the ESD structures and they made a few recommendations which Nathan, their layout guy, immediately implemented, like beefing up some metal pathways and maximizing clamp sizes.
Thanks for thinking about these things. It really seems to me like either the tester is somehow destroying chips or there is a manufacturing defect.
Well, they are going to have to implement some kind of resistance check before power up, before they use the probe card again. I think they just want to try to discover more about the nature of the problem before they get back into that. The decision to not develop the test immediately might have to do with using their test engineer's time on other things, for now.
We did a pretty exhaustive review at ON Semi of the ESD structures and they made a few recommendations which Nathan, their layout guy, immediately implemented, like beefing up some metal pathways and maximizing clamp sizes.
Did they run actual ESD tests ? - At what spike levels did these fail, (IO pins and Supply pins) and what were the failure modes ?
You could even try some ESD events yourself, into the P2 part you have with one VIO
Well, they are going to have to implement some kind of resistance check before power up, before they use the probe card again. I think they just want to try to discover more about the nature of the problem before they get back into that. The decision to not develop the test immediately might have to do with using their test engineer's time on other things, for now.
We did a pretty exhaustive review at ON Semi of the ESD structures and they made a few recommendations which Nathan, their layout guy, immediately implemented, like beefing up some metal pathways and maximizing clamp sizes.
Did they run actual ESD tests ? - At what spike levels did these fail, (IO pins and Supply pins) and what were the failure modes ?
You could even try some ESD events yourself, into the P2 part you have with one VIO
They have a bunch of V1 silicon chips that they are planning on zapping and retesting. I need to ask about that, because they have all the facilities they need to do that test, but they haven't said anything about it for weeks.
The senior engineer at ON Semi emailed me today and said that they are reviewing additional data and we will have another conference call mid next week.
Comments
Fingers and toes crossed... The more formal these things are, the less likely it is to be good news..
Exactly!
I'm a little worried about something like that. I do have a perfectly-working chip, though. So, it seems the reticles are good.
They don't have a current-limited test to run, yet, so I don't think they have been able to test any more wafers since the probe cards were damaged.
Let's see what they say.
They have noticed that the hot spots are occurring near the VIO and GIO pins, which contain these circuits:
It seems that Circuit A, which is an ESD clamp, is passing current from Vgs=0, through M4. Of course, that shouldn't be possible, but it looks like it's always turned on, without even any bias.
They are going to build some open-cavity chips into packages and test them. We are needing to see if these failures are always in the same circuits. Seems to me, that's the case.
This could take a month, they think, because they need to order new exposed-pad 100-pin packages.
Kind regards, Samuel Lourenço
Yes, I wish I had taken a screen shot.
We need to know if that is always where the trouble is coming from. It seems to be on different pins, but the same "Circuit A" M4.
I don't think it's the design, because this same circuit was fabricated in the original V1 silicon and there was no issue. I even have a new V2 silicon chip on my desk that works fine. It looks to me like some manufacturing defect that was widespread for some reason in the V2 silicon.
Kind regards, Samuel Lourenço
Yeah, I wonder the same things. Maybe there was even a dopant problem, because M4 seems to always be on, in some VIO pins.
If GIO and VSS are to be bonded together only during/after the packaging of the die, is there any chance that ESD is jumping across GIO to VSS during testing? Only the weakest gate isolation could be affected, and after that, a disharge path would be formed. That discharge path could be formed on any pin, explaining the randomness, and also why only one pin fails at a time (the new discharge path protects other pins, acting as a clamping diode or as a low resistance path).
Of course this is a wild shot in the very dark, from someone who knows nothing about micro-electronics (me), so bare with me Chip. I have a 99% chance of being absolutely wrong.
Kind regards, Samuel Lourenço
And, only on the edges?
Can't they just proceed and solve this problem later?
It's quite weird only some fail, and also weird they fail apparently as a resistor. Is there is a G-D filament, then the resistance would be non linear at < 500mV
Can you check a failed part, with no VDD applied - maybe that unexplained lateral current that seems to flow Vdd -> VIO, is enough to bias the ESD fet ?
If you can plot I-V on a failed pin, and compare with Spice on that MOSFET with (eg) D-G shorted that could help suggest failure mechanisms ?
If the locations vary across all wafers, that rather excludes a fixed damaged photo-mask error.
When they ran ESD tests, I wonder how similar the ESD failures measure to this failure ?
The V2 chip on my desk has a single bad VIO that measures 91 ohms without power. At 3.3V, it passes 29mA quiescent current, which is a little less than 3.3V/(91 ohms), but probably due to conduction loss from self-heating.
I designed these ESD circuits and ON Semi reviewed them in a meeting, prior to V1 silicon tapeout, and figured they were okay. They worked fine on V1, but now seem to be continuously conducting in some cases.
On Semi no longer wants to develop the resistance test that their test engineer and I were going to work on, since they feel it represents too great a risk to the probe cards. I think it would be safe, myself. So, we are waiting to see what the open-cavity chips reveal. My big question is whether or not it's always "Circuit A" that causes the trouble.
Not sure, yet. They've apparently seen a few cases of this on V4447. One of the probe cards also had its V0407 pin damaged.
Hmm, that seems extremely conservative of them, but sounds like they may review, after the open cavity packages tests.
A typical meter might inject 1mA, which is 91mV drop for the ohms test, so well below any gate threshold. (excludes G-D filaments?)
It's not easy to turn an enhancement mode mosfet into a pure resistor ?
Do you have the artwork layers for ES1 and ES2 to compare, and how close those ESD fets physically are to each of their PAD areas that are probed ?
It seems to me that On Semi are making excuses for something else if that's the actual reason they gave. The reason, on its own, appears illogical.
You mean, like the test team move to brush the blame under the carpet of the manufacturing team, who seek to brush the blame under the carpet of the design team........ etc.. etc..
Seems all that effort damages communication and delays getting stuff fixed, but hopefully behind all that stuff the solution has been identified and they are moving fast to provide the right solution.
Customers want chips ! With the resolution comes the solution.
(Not withstanding the point about test current limiting- does seem peculiar that a simple continuity/resistance test isn't standard before pumping test-probe melting high current into any wafer, for any customer. Although maybe OnSemi have a good reason for that; perhaps they would rather pay the cost of a few probe repairs in the low-occurrence cases of "manufacturing" defects, than spend more time on testing each part. Even so, I would have thought it typical to use a voltage source that limits current below the melting point of a >$2000 probe! Such is the view from this window, far far away.)
Your circuit "A" does not seem correct to me.
Assuming on power up that the "capacitor" (M1) is discharged, then every time power is applied M4 will conduct until M1 is charged through R1.
A second note ... your mention on the schematic "On PAD_GIO, this is GIO, not VIO." ... How are you conveying that in the schematic so that it meets up properly in layout? .... If this got mixed up somehow and GIO happens to be VIO in the wrong location, then it wouldn't matter if M4 was turned on or not.
Do you happen to have a layout view of this particular ESD section?
There are two main things that should be in place for ESD protection, and three if you want to go over redundant.
1) An NMOS and/or PMOS with the gates tied to their respective Source ... This clamps on a negative ESD voltage spike.
2) An RC configuration (similar to what you have), but instead of threshold switching it relies on the Zener effect of the transistor to switch when the voltage is above a certain level. ... This ensures that there is no clamping under normal voltage conditions and positive ESD voltage spikes will be properly handled.
3) Is a "comb" structure with proper spacing between points which must create a breakdown voltage higher than the operating voltage. ...This acts as a "spark gap" and will clamp both positive and negative ESD voltage spikes.
Only a sharp rise on VIO will cause conduction through M4. That 210.9K resistor and the M1 gate cap have an RC time constant of 211k * 9pF = 1.9us. System VIO usually rises in 1ms, or much more, so that circuit never turns on, normally. If you get an ESD spike that has a rise time of 2ns, that thing will definitely turn on, for maybe >1us.
The only difference between the VIO and GIO pad schematics is in what the pad metal connects to (VIO or GIO). I just didn't want to post two nearly-identical schematics with only one subtle difference. I was worried it would cause wasted effort in the person wanting to understand the pad schematics.
I attached a picture. It is M4 that is apparently getting hot, but conducting current from VIO>0, without VIO ever needing to hit the threshold voltage. Very weird.
This was done better on each I/O pad by having dedicated diode arrays that clamp the I/O pin to VIO and GIO. The VIO and GIO pads just have VSS-to-GIO clamps and over-voltage protection.
Circuit A achieves the same thing. It should never turn on during power-up, due to bypass charging and supply impedance limits. Even it does turn on, it will be off in another 1us to 2us.
This, we don't have.
We did a pretty exhaustive review at ON Semi of the ESD structures and they made a few recommendations which Nathan, their layout guy, immediately implemented, like beefing up some metal pathways and maximizing clamp sizes.
Thanks for thinking about these things. It really seems to me like either the tester is somehow destroying chips or there is a manufacturing defect.
Good to hear forward progress.
Did they run actual ESD tests ? - At what spike levels did these fail, (IO pins and Supply pins) and what were the failure modes ?
You could even try some ESD events yourself, into the P2 part you have with one VIO
They have a bunch of V1 silicon chips that they are planning on zapping and retesting. I need to ask about that, because they have all the facilities they need to do that test, but they haven't said anything about it for weeks.