The ESD protections are well designed, as far as I'm concerned. The design should be fine. My only concern is On Semi testing methodology. If they think that the design is faulty, they will have to justify it, based on how 100 samples in the wild survived.
This is the issue with big companies: they don't own blame and/or responsability. It was the same thing at Synopsys.
At this point, ON thinks it's either something about the design which is not agreeable to the process, despite passing design-rule checks, or there's some kind of manufacturing defect.
They need to get this resolved to move the whole P2 program forward and get it into the "manufacturing" stage. That's where their profit potential is.
I wish the pace of communication was a bit brisker.
Or, I suppose you could just proceed with the V1 analog and the V2 digital, right?
The only thing that changed from V1 to V2 in the entire pad ring was the PLL filter settings, which involved a few 1.8V logic signals being connected differently. So, something else must be wrong.
If ON were able to get to the bottom of things in this case, it could help them with future customers, even though doing so could take investing some more engineering resouces now. And if the problem does turn out to be something in the P2 design being incompatible with the process, then there may very well be a work-around for it (such as, don't use this particular combination, or make sure "this" always has "that" or keep this shorter than x). Anyway, perhaps more will be revealed during the next conference call. Fingers crossed that ON sees this as a research opportunity and at least gets some more data.
I have been thinking about this quite a bit, and I wonder if this is a classic parasitic "latch-up" issue ... The circuit that you have in Circuit "A" is essentially a CMOS inverter with the PMOS shorted and the gate is tied low. That said, you have still constructed an Inverter. In the parasitic model, the PNP transistor is now essentially a diode (Because The Source and Drain of the PMOS has been shorted) which provides a HIGH signal to the base of the parasitic NPN transistor turning it "ON" resulting in the NMOS (M4) transistor turning "ON". The proper use of guard rings prevent the parasitic "SCR" from forming.
The guard rings on Circuit "A" don't look correct to me ... Compare to Circuit "B" which does look correct ...
Notice in Circuit "B" that there are double guard rings around each active device? You should have the same style of double guard ring around the active devices in Circuit "A". M4 has a continuous guard ring, and the second ring encapsulates M1. The second guard ring is NOT correct. M1 should have it's own ring as well. For good measure R1 should also have a double ring.
Note: The secondary ring around M4 should encompass just M4 and have nothing to do with M1. The same strategy using two guard rings should be applied to M1. See the last Image "Latchup Guard Rings_A Correct.JPG"
The VDD and VSS pins have these same circuits, but for 1.8V (no deep N-well). They haven't had any issues, just the VIO (and GIO) have this latch-up or blow-out problem.
I really think there is something funny going on with the tester. There are some V/t and I/t plots of the new silicon a few posts up that show an initial current rush of 180mA when VIO is still at 0V, but beginning to rise. I suspect that current measurement was taken from behind a switch that routes the VIO supply out to the VIO pins. And I also think that GND, which is a programmable pin from the tester is not at 0V, but maybe ~1V above or below what should be GND. So, when VIO gets switched on, there is an immediate current rush which could be initiating latch-up, which subsequently leads to frying as voltage and current continue to rise from the tester supply.
The tester used to be safe on packaged parts, but I recall some talk of ON Semi removing the bypass caps, and now it's killing packaged parts, just like it was killing dies via the probe card, which has no bypass caps.
If there is some offset voltage causing an initial current rush, the bypass caps would slow down the voltage rise and keep M4 off, maybe avoiding the latch-up trigger event.
...
The tester used to be safe on packaged parts, but I recall some talk of ON Semi removing the bypass caps, and now it's killing packaged parts, just like it was killing dies via the probe card, which has no bypass caps.
If there is some offset voltage causing an initial current rush, the bypass caps would slow down the voltage rise and keep M4 off, maybe avoiding the latch-up trigger event.
There is usually some trigger current on the lateral SCRs, which was part of the reason I asked about the ESD test results, which I assumed would also include latch up tests...
I tested CPLD and MCUs (Atmel) some years ago, and they needed hundreds of mA to trigger, but once triggered the thyristor was actually 'quite good' with a holding current sub 10mA.
...
The tester used to be safe on packaged parts, but I recall some talk of ON Semi removing the bypass caps, and now it's killing packaged parts, just like it was killing dies via the probe card, which has no bypass caps.
If there is some offset voltage causing an initial current rush, the bypass caps would slow down the voltage rise and keep M4 off, maybe avoiding the latch-up trigger event.
There is usually some trigger current on the lateral SCRs, which was part of the reason I asked about the ESD test results, which I assumed would also include latch up tests...
I tested CPLD and MCUs (Atmel) some years ago, and they needed hundreds of mA to trigger, but once triggered the thyristor was actually 'quite good' with a holding current sub 10mA.
A current spike from the tester due to unexpected start-up phenomena could explain all these problems.
So, after all, it may be a latch-up condition triggered by the tester. If packaged parts can also fail the same, without caps, I guess we can exclude the phenomena being triggered by a floating GIO relative to VSS (GIO is bonbed to VSS/GND on a packaged part, right)?
I wonder if this can be considered a design issue or not. Fast analog inputs are often more prone to SCR latching, because the measures that would make them less prone also degrade the bandwith. Lets see if the way the guard rings are designed is motivated by a decision like that.
Maybe explains the early Eval board smoke-ups when moving the VIO jumpers with the power on. I know I've avoided doing that again.
I remember someone saying something about this. I will do some tests this morning to see if I can replicate the problem.
One VIO has failed on the new-silicon P2 Eval board that I have. I had been moving the power jumper off and on, but I've been supposing that it must have been something else that broke it.
Maybe explains the early Eval board smoke-ups when moving the VIO jumpers with the power on. I know I've avoided doing that again.
Never had any smoke escaping when doing that, and I did it many times. Better not to do it again.
I have to see the original eval board schematic, because I have the idea that the decoupling capacitors are right near the VIO pins, after the jumpers. So, the chance of having latch-up is minimized, but not null.
I guess it is possible to use the next batch of chips, but the design has to be reviewed, probably.
I have to see the original eval board schematic, because I have the idea that the decoupling capacitors are right near the VIO pins, after the jumpers. So, the chance of having latch-up is minimized, but not null.
I'm guessing it depends on there being a number of jumpers already in the switcher supply position. That way there is a stack of fully charged ceramics ready to punch back hard against the two that are protecting that freshly shifted jumper.
I have to see the original eval board schematic, because I have the idea that the decoupling capacitors are right near the VIO pins, after the jumpers. So, the chance of having latch-up is minimized, but not null.
I'm guessing it depends on there being a number of jumpers already in the switcher supply position. That way there is a stack of fully charged ceramics ready to punch back hard against the two that are protecting that freshly shifted jumper.
Yeah, I pulled down a VIO with a 10k resistor and then watched the voltage as I played with the jumper. Rise time to 3.3V was just under 1us. No damage sustained. Then I tried connecting that VIO to 5V with a wire I'd brush against it. The scope was showing 10V peak! I damaged P54 through playing with VIO on that occasion. Not sure what exactly happened.
I have to see the original eval board schematic, because I have the idea that the decoupling capacitors are right near the VIO pins, after the jumpers. So, the chance of having latch-up is minimized, but not null.
I'm guessing it depends on there being a number of jumpers already in the switcher supply position. That way there is a stack of fully charged ceramics ready to punch back hard against the two that are protecting that freshly shifted jumper.
Yeah, I pulled down a VIO with a 10k resistor and then watched the voltage as I played with the jumper. Rise time to 3.3V was just under 1us. No damage sustained. Then I tried connecting that VIO to 5V with a wire I'd brush against it. The scope was showing 10V peak! I damaged P54 through playing with VIO on that occasion. Not sure what exactly happened.
The individual IOs are supposed to be 5V tolerant, for a brief moment, right? But then you supplied 5V briefly to the IO supply of a bank? And only damaged one pin? I was not aware that VIO pins could also tolerate 5V briefly, or at least were supposed to.
By the way, that 10V peak is probably due to the wire inductance, but it could be caused by the lead inductance on the oscilloscope probe as well. But the wire itself alone could have caused a spike that triggered a latch up when it disconnected.
The wire inductance, coupled with the ceramic capacitors, will cause a resonant behavior (under dampened oscillation). Bit that bullet myself, when plugging a board that had a 35V tolerant LDO, to a 24V supply, with a 1m cable, and only having a 1u ceramic decoupling the input. How long is the wire? If you use a resistor as low as 2.2R, in series with your supply and after the long wire, you might be able to dampen the spike/oscillation.
The individual IOs are supposed to be 5V tolerant, for a brief moment, right? But then you supplied 5V briefly to the IO supply of a bank? And only damaged one pin? I was not aware that VIO pins could also tolerate 5V briefly, or at least were supposed to.
That depends on 'supposed to'.
The P2 pins are certainly not 5V Tolerant.
There is a clamp diode in all pins to VIO, so any higher voltage is clamped (same as in P1)
During the very brief ESD events, a pin will often spike to 5V or more, but an ESD event is not the same as operating continually.
ESD specs are usually based on some model and some pF is charged to a large voltage, then discharged thru a pin via some resistance,
Pins also often have a latch-up spec, where the vendor specs some peak injection current limit, that is guaranteed to not cause latch up. (of lateral parasitic SCRs )
This is a good example from a Nuvoton MCU data sheet. These numbers are at the 'rugged' end of the scale.
Symbol Description Min Typ Max Unit
VHBM[*1] Electrostatic discharge,human body mode -8000 - +8000 V
VCDM[*2] Electrostatic discharge,charge device model -1000 - +1000
LU[*3] Pin current for latch-up[*3] -400 - +400 mA
VEFT[*4] [*5] Fast transient voltage burst -4 - +4 kV
1. Determined according to ANSI/ESDA/JEDEC JS-001 Standard, Electrostatic Discharge Sensitivity Testing – Human Body Model (HBM) – Component Level
2. Determined according to ANSI/ESDA/JEDEC JS-002 standard for Electrostatic Discharge Sensitivity (ESD) Testing – Charged Device Model (CDM) – Component Level.
3. Determined according to JEDEC EIA/JESD78 standard.
4. Determinded according to IEC 61000-4-4 Electrical fast transient/burst immunity test.
5. The performace cretia class is 4A.
The main thing here is the effect of the wire inductance, coupled with the ceramic capacitor resonant behavior. That is not ESD, and is far more powerfull.
The low value series resistor I've mentioned earlier is to break that behavior (to dampen the oscillation, essentially), not to emulate an ESD model, by the way.
ON Semi has located the likely problem. They will confirm with some tests tomorrow.
The problem is that there are some N-wells at different potentials in the I/O pad that don't have guardbars (or guardrings) between them to inhibit latch-up. Once those small circuits latch up, the nearby VIO pad's ESD clamp latches up, causing the real damage.
They think the reason this just showed up is because susceptibility to this happening is a function of substrate resistivity, which varies by wafer and location on the wafer. Some of these dies have sufficiently conductive substrates that enable latch-up to be triggered, given our design problems. On the first silicon, the substrates were less conductive. Again, this can be remedied by better design. Nathan at ON Semi (layout engineer) has looked over the other pads and found that the XI/XO pads need some attention, and the RESn and TESn pads could be improved, but are probably okay. All these circuits are level translators that convert core 1.8V signals to 3.3V signals that are used by the pad logic.
So, we are going to have to make some changes to fix this, which means a respin is necessary. It may only require a few new reticles, though. On the last respin, they were able to reuse 7 reticles from the first silicon, since deep N-wells, 3.3V circuits, and passivation openings didn't change, and those all exist only in the custom padframe.
Some of the dies on these current six wafers are okay, but they need current-limiting on the tester setup before they can be safely probed. I'm hoping we'll be able to get a few hundred good chips out of the new wafers on hand, so that we can make P2 Eval boards that are at least worthy of tool development, before we have the final production chips.
Here are some pictures of the area where the latch-up is occurring. I could have easily filled those single-via areas solid with vias when I was editing the layout, but I didn't notice them. I was completely insensitive to this other issue of guardbars/rings, though.
ON Semi has located the likely problem. They will confirm with some tests tomorrow.
The problem is that there are some N-wells at different potentials in the I/O pad that don't have guardbars (or guardrings) between them to inhibit latch-up. Once those small circuits latch up, the nearby VIO pad's ESD clamp latches up, causing the real damage.
They think the reason this just showed up is because susceptibility to this happening is a function of substrate resistivity, which varies by wafer and location on the wafer...
Does that mean the injection current needed to trigger latchup varies, but it is always > 0 ?
ie the dies may actually all be useful but with some limits on injection current tolerance ?
What latch up currents did they measure on ES1 packaged parts ?
(I've seen vendors quote >200mA (Atmel PLD) and >400mA (Nuvoton MCU) current tolerance levels)
ON Semi has located the likely problem. They will confirm with some tests tomorrow.
The problem is that there are some N-wells at different potentials in the I/O pad that don't have guardbars (or guardrings) between them to inhibit latch-up. Once those small circuits latch up, the nearby VIO pad's ESD clamp latches up, causing the real damage.
They think the reason this just showed up is because susceptibility to this happening is a function of substrate resistivity, which varies by wafer and location on the wafer...
Does that mean the injection current needed to trigger latchup varies, but it is always > 0 ?
ie the dies may actually all be useful but with some limits on injection current tolerance ?
What latch up currents did they measure on ES1 packaged parts ?
(I've seen vendors quote >200mA (Atmel PLD) and >400mA (Nuvoton MCU) current tolerance levels)
This seems to happen on some chips whenever there is >700mV difference between well potentials (which run at 1.8V and 3.3V). ON Semi thinks that it's not triggered by transients, but initiates during steady-state operation. In other words, there's no precaution you can take against it happening. It's just going to occur at normal operating voltages.
I'm still pretty leery of their tester, though. It's never been explained why there are 75mA initial current surges on VDD and VIO when they are each at 0V, beginning to rise. They will do an empty-socket test tomorrow on the tester and see what the current looks like in relation to the voltage.
Here you can see those current spikes on the old silicon being tested:
I'm still pretty leery of their tester, though. It's never been explained why there are 75mA initial current surges on VDD and VIO when they are each at 0V, beginning to rise. They will do an empty-socket test tomorrow on the tester and see what the current looks like in relation to the voltage.
Here you can see those current spikes on the old silicon being tested:
To me, that looks like simple capacitive charge - the die is very large, so likely has nF of capacitance, and there may be probe decoupling too ?.
What are the time-units on the X axis ? It should be possible to calculate what C that indicates.
More curious to me is the 20mA of residual/lateral current on Vdd when VIO is 0, that goes away then VIO ramps.
It does drop to 0 when VIO ~ VDD, so that should unlatch any SCRs.
Normal SCR/Thryistors do also have a dV/dT limit, and above that, they can self-trigger from the capacitive path currents alone.
Does this mean ON don’t need to redo the verilog? ie it’s only a change to those outer ring parts and that can be done without other changes?
I presume the answer is yes, and that should be a simple and quick respin. And the speed you’re getting will stay!
You mean make it go faster? Or, do you mean the glitch? The glitch issue cannot be simply gotten around, I think. Also, this change they are going to make will probably only involve metal1 (m1), among all the metal layers, so not that much will be possible.
I'm still pretty leery of their tester, though. It's never been explained why there are 75mA initial current surges on VDD and VIO when they are each at 0V, beginning to rise. They will do an empty-socket test tomorrow on the tester and see what the current looks like in relation to the voltage.
Here you can see those current spikes on the old silicon being tested:
To me, that looks like simple capacitive charge - the die is very large, so likely has nF of capacitance, and there may be probe decoupling too ?.
What are the time-units on the X axis ? It should be possible to calculate what C that indicates.
More curious to me is the 20mA of residual/lateral current on Vdd when VIO is 0, that goes away then VIO ramps.
It does drop to 0 when VIO ~ VDD, so that should unlatch any SCRs.
Normal SCR/Thryistors do also have a dV/dT limit, and above that, they can self-trigger from the capacitive path currents alone.
If all pins on the chip are floating and VDD starts to rise from 0V, where is all that current flowing? By the way, the 65% decay period on that current spike is about 10us. That 75mA is flowing to some potential below 0V, before it decays, and 20mA of quiescent current takes over.
I need to figure out what that 20mA of VDD is from, before VIO rises.
Comments
This is the issue with big companies: they don't own blame and/or responsability. It was the same thing at Synopsys.
You have a great design, Chip. Press on!
Kind regards, Samuel Lourenço
They need to get this resolved to move the whole P2 program forward and get it into the "manufacturing" stage. That's where their profit potential is.
I wish the pace of communication was a bit brisker.
Kind regards, Samuel Lourenço
The only thing that changed from V1 to V2 in the entire pad ring was the PLL filter settings, which involved a few 1.8V logic signals being connected differently. So, something else must be wrong.
I have been thinking about this quite a bit, and I wonder if this is a classic parasitic "latch-up" issue ... The circuit that you have in Circuit "A" is essentially a CMOS inverter with the PMOS shorted and the gate is tied low. That said, you have still constructed an Inverter. In the parasitic model, the PNP transistor is now essentially a diode (Because The Source and Drain of the PMOS has been shorted) which provides a HIGH signal to the base of the parasitic NPN transistor turning it "ON" resulting in the NMOS (M4) transistor turning "ON". The proper use of guard rings prevent the parasitic "SCR" from forming.
The guard rings on Circuit "A" don't look correct to me ... Compare to Circuit "B" which does look correct ...
Notice in Circuit "B" that there are double guard rings around each active device? You should have the same style of double guard ring around the active devices in Circuit "A". M4 has a continuous guard ring, and the second ring encapsulates M1. The second guard ring is NOT correct. M1 should have it's own ring as well. For good measure R1 should also have a double ring.
Note: The secondary ring around M4 should encompass just M4 and have nothing to do with M1. The same strategy using two guard rings should be applied to M1. See the last Image "Latchup Guard Rings_A Correct.JPG"
The VDD and VSS pins have these same circuits, but for 1.8V (no deep N-well). They haven't had any issues, just the VIO (and GIO) have this latch-up or blow-out problem.
I really think there is something funny going on with the tester. There are some V/t and I/t plots of the new silicon a few posts up that show an initial current rush of 180mA when VIO is still at 0V, but beginning to rise. I suspect that current measurement was taken from behind a switch that routes the VIO supply out to the VIO pins. And I also think that GND, which is a programmable pin from the tester is not at 0V, but maybe ~1V above or below what should be GND. So, when VIO gets switched on, there is an immediate current rush which could be initiating latch-up, which subsequently leads to frying as voltage and current continue to rise from the tester supply.
The tester used to be safe on packaged parts, but I recall some talk of ON Semi removing the bypass caps, and now it's killing packaged parts, just like it was killing dies via the probe card, which has no bypass caps.
If there is some offset voltage causing an initial current rush, the bypass caps would slow down the voltage rise and keep M4 off, maybe avoiding the latch-up trigger event.
What do you think?
There is usually some trigger current on the lateral SCRs, which was part of the reason I asked about the ESD test results, which I assumed would also include latch up tests...
I tested CPLD and MCUs (Atmel) some years ago, and they needed hundreds of mA to trigger, but once triggered the thyristor was actually 'quite good' with a holding current sub 10mA.
A current spike from the tester due to unexpected start-up phenomena could explain all these problems.
So, after all, it may be a latch-up condition triggered by the tester. If packaged parts can also fail the same, without caps, I guess we can exclude the phenomena being triggered by a floating GIO relative to VSS (GIO is bonbed to VSS/GND on a packaged part, right)?
I wonder if this can be considered a design issue or not. Fast analog inputs are often more prone to SCR latching, because the measures that would make them less prone also degrade the bandwith. Lets see if the way the guard rings are designed is motivated by a decision like that.
Kind regards, Samuel Lourenço
I remember someone saying something about this. I will do some tests this morning to see if I can replicate the problem.
One VIO has failed on the new-silicon P2 Eval board that I have. I had been moving the power jumper off and on, but I've been supposing that it must have been something else that broke it.
Don't think there will be too many volunteers to help with that kind of testing!
LOL
I have to see the original eval board schematic, because I have the idea that the decoupling capacitors are right near the VIO pins, after the jumpers. So, the chance of having latch-up is minimized, but not null.
I guess it is possible to use the next batch of chips, but the design has to be reviewed, probably.
There should be no worries. There are plenty of volunteer samples yet to be tested.
Kind regards, Samuel Lourenço
Yeah, I pulled down a VIO with a 10k resistor and then watched the voltage as I played with the jumper. Rise time to 3.3V was just under 1us. No damage sustained. Then I tried connecting that VIO to 5V with a wire I'd brush against it. The scope was showing 10V peak! I damaged P54 through playing with VIO on that occasion. Not sure what exactly happened.
By the way, that 10V peak is probably due to the wire inductance, but it could be caused by the lead inductance on the oscilloscope probe as well. But the wire itself alone could have caused a spike that triggered a latch up when it disconnected.
The wire inductance, coupled with the ceramic capacitors, will cause a resonant behavior (under dampened oscillation). Bit that bullet myself, when plugging a board that had a 35V tolerant LDO, to a 24V supply, with a 1m cable, and only having a 1u ceramic decoupling the input. How long is the wire? If you use a resistor as low as 2.2R, in series with your supply and after the long wire, you might be able to dampen the spike/oscillation.
Kind regards, Samuel Lourenço
The P2 pins are certainly not 5V Tolerant.
There is a clamp diode in all pins to VIO, so any higher voltage is clamped (same as in P1)
During the very brief ESD events, a pin will often spike to 5V or more, but an ESD event is not the same as operating continually.
ESD specs are usually based on some model and some pF is charged to a large voltage, then discharged thru a pin via some resistance,
Pins also often have a latch-up spec, where the vendor specs some peak injection current limit, that is guaranteed to not cause latch up. (of lateral parasitic SCRs )
This is a good example from a Nuvoton MCU data sheet. These numbers are at the 'rugged' end of the scale.
The low value series resistor I've mentioned earlier is to break that behavior (to dampen the oscillation, essentially), not to emulate an ESD model, by the way.
Kind regards, Samuel Lourenço
The problem is that there are some N-wells at different potentials in the I/O pad that don't have guardbars (or guardrings) between them to inhibit latch-up. Once those small circuits latch up, the nearby VIO pad's ESD clamp latches up, causing the real damage.
They think the reason this just showed up is because susceptibility to this happening is a function of substrate resistivity, which varies by wafer and location on the wafer. Some of these dies have sufficiently conductive substrates that enable latch-up to be triggered, given our design problems. On the first silicon, the substrates were less conductive. Again, this can be remedied by better design. Nathan at ON Semi (layout engineer) has looked over the other pads and found that the XI/XO pads need some attention, and the RESn and TESn pads could be improved, but are probably okay. All these circuits are level translators that convert core 1.8V signals to 3.3V signals that are used by the pad logic.
So, we are going to have to make some changes to fix this, which means a respin is necessary. It may only require a few new reticles, though. On the last respin, they were able to reuse 7 reticles from the first silicon, since deep N-wells, 3.3V circuits, and passivation openings didn't change, and those all exist only in the custom padframe.
Some of the dies on these current six wafers are okay, but they need current-limiting on the tester setup before they can be safely probed. I'm hoping we'll be able to get a few hundred good chips out of the new wafers on hand, so that we can make P2 Eval boards that are at least worthy of tool development, before we have the final production chips.
Here are some pictures of the area where the latch-up is occurring. I could have easily filled those single-via areas solid with vias when I was editing the layout, but I didn't notice them. I was completely insensitive to this other issue of guardbars/rings, though.
ie the dies may actually all be useful but with some limits on injection current tolerance ?
What latch up currents did they measure on ES1 packaged parts ?
(I've seen vendors quote >200mA (Atmel PLD) and >400mA (Nuvoton MCU) current tolerance levels)
This seems to happen on some chips whenever there is >700mV difference between well potentials (which run at 1.8V and 3.3V). ON Semi thinks that it's not triggered by transients, but initiates during steady-state operation. In other words, there's no precaution you can take against it happening. It's just going to occur at normal operating voltages.
I'm still pretty leery of their tester, though. It's never been explained why there are 75mA initial current surges on VDD and VIO when they are each at 0V, beginning to rise. They will do an empty-socket test tomorrow on the tester and see what the current looks like in relation to the voltage.
Here you can see those current spikes on the old silicon being tested:
To me, that looks like simple capacitive charge - the die is very large, so likely has nF of capacitance, and there may be probe decoupling too ?.
What are the time-units on the X axis ? It should be possible to calculate what C that indicates.
More curious to me is the 20mA of residual/lateral current on Vdd when VIO is 0, that goes away then VIO ramps.
It does drop to 0 when VIO ~ VDD, so that should unlatch any SCRs.
Normal SCR/Thryistors do also have a dV/dT limit, and above that, they can self-trigger from the capacitive path currents alone.
I presume the answer is yes, and that should be a simple and quick respin. And the speed you’re getting will stay!
You mean make it go faster? Or, do you mean the glitch? The glitch issue cannot be simply gotten around, I think. Also, this change they are going to make will probably only involve metal1 (m1), among all the metal layers, so not that much will be possible.
If all pins on the chip are floating and VDD starts to rise from 0V, where is all that current flowing? By the way, the 65% decay period on that current spike is about 10us. That 75mA is flowing to some potential below 0V, before it decays, and 20mA of quiescent current takes over.
I need to figure out what that 20mA of VDD is from, before VIO rises.