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## Comments

14,874How many bits do you think that improved the SFDR ?

Maybe you need to feed this into some spectrum software to confirm your dynamic range ?

12,178Ah, nope, from reading, recommended optimal arrangement is have the filter/accumulator at least one order higher than the modulator/integrator.

EDIT: You'll note that diagram is labelled as a Sinc3 filter. When I first saw that stated it was a huge relief to me because before that I didn't have the faintest what the maths was saying in terms of implementation.

13,685It just filters away the disruption caused by the chunkiness of the <7-clock cycling in the ADC bit stream patterns. This results in a two-bit improvement across the board. After this improvement, we are totally clean until we hit the 1/f noise starting at 13 bits.

The filter can be thought of as something that just processes the first 32 and last 32 bit samples. Everything in-between is counted normally (inc on 1).

Nobody seems to understand how simple this filter is. It will probably grow the smart pins by only 2%.

13,685I still have no idea why it should work. I just don't get the principal, except in the vaguest sense.

12,178It could be simulated from the same streamer data.

13,685But what is the principal?

12,17813,685Since we are dealing with a bit stream here, and not integral values, do we need that wide of an accumulator? How do we go from 1 bit to 16 bits?

13,68512,178I'll try duplicating what you've already done, but save the bitstream data and see if comparisons can be made.

13,685That would be awesome. Meanwhile, I'll read something about SINC filters.

14,87432/6144 = 0.520% of the samples.

I'm not seeing how a claimed 2-bit improvement can come from doing nothing at all to 99% of the samples ?

13,685(1) Take your voltage value (0..255) and add it into an 8-bit accumulator

(2) The carry output from the add is the ADC bit

(3) goto (1)

for $40 you will get 0001000100010001...

for $80 you will get 0101010101010101...

for $C0 you will get 0111011101110111...

That synthesized ADC bitstream is all you need to feed your SINC filter. No need to hook up anything. Work on the platform of your choice.

13,685The cyclical patterns in the ADC output bitstream present a nasty situation, where they are cycling in less than 7 bit spans. For continuous sampling, this doesn't matter, but for discrete sampling, your sample gets corrupted by what it first and last accumulates. That cruft needs to be low-passed to stop it from causing unpredictable noise in the two LSBs.

12,178I probably want some noise. I'll give that a try though, thanks.

14,874I can see a soft-close, soft-open linear weighted switch, but I remain unconvinced that has

actuallygained you 2 LSBs improvement in ADC performance.Imagine those readings are seriously bad, with 0% or 100% return values, they only account for 0.5% of the ADC answer, so they can only give 99.5%~100.5% of total possible outcomes.

12,17813,685I look at it differently.

Without the filtering, for a steady-voltage input, samples will always span four levels.

With the filtering, for a steady-voltage input, the samples settle at one level. That's 4x the certainty, which counts for two bits.

And it doesn't matter how long the sample run is, although past 6k bits, the 1/f noise becomes influential.

13,685I wouldn't worry about noise, at first. Just see if you can get something sensible going under ideal conditions.

14,874the noise in all those other bits, passes straight through.Noise is always there, spread over all the samples.

13,685Well, you tell me how it works, then. All I know is that it improves sample quality so that contiguous values are output all the way into 13 bits.

8K sample without filtering of first 16 and last 16 bits:

8K sample WITH filtering of first 16 and last 16 bits:

(I'm just doing 16 bits, not 32 here.)

13,6854,436The technique could be extended to a 'crossfade' from one sample to another, potentially

Part of me wonders why this filter works as effectively as it does. Perhaps we should look at the clumpiness of the low level bitstream to understand the underlying issues better

14,874I'm still unconvinced about filtering, but maybe you have found some ADC artifact. eg Maybe there is an enable settling time effect, that this is fixing.

In that case :

If you remove the trailing filter, does it make any difference ?

If you replace the leading filter with a simpler, blanking delay, how does that look ?

For real ADC measurements, you need to get a serious DAC and plot ADC ideal against ADC actual.

eg TI have an 18b 5us DAC, with a 50MHz SPI interface, that has Eval Board DAC9881EVM for $77 - that should have a noise floor way below anything the P2 can manage internally.

Or an EVAL-AD5680DBZ for $55, but the specs are not as good as DAC9881

Addit:

There are also Audio DACs that seem to go to DC, but with no specific gain/drive for DC levels, so they may need a companion 'good ADC' to calibrate.

eg TI has a PCM5102A that seems to have low cost eval boards. This DAC claims 384kHz sampling, up to 50MHz SCK, accepts 16/24/32b DAC streams.

That's sounding a useful device for P2 to be able to drive anyway.

13,685It needs filtering at both the front and back to work. Without both, you get lots of noise.

13,6852,567The integrator is still linear and not exponential like in classical filters.

12,365It's just a square moving average. Turns out that this is a sinc function in the frequency domain.

Looks like a lot of people size the window such that it cuts out 50 or 60 Hz...

12,17818,037Something seems amiss when you can effectively remove a group of first samples and last samples and end up with a superior result. Since you say the sampling is free running and has been before you start, the something is upsetting the results. Otherwise all the results would be noisy and you could just take any window of samples and you would get the same/similar results.

So the question is rather, what is causing those first and last sample groups to be poor?

What you have found is the result of a problem. Now it's time to find out the why. It's not the final silicon yet, so a workaround currently isn't the solution.

Just my observation.