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## Comments

14,876Err, hopefully, they simply just disable the

optionalfilter !! No PCB mods or product revisions required,14,876Of course, a single bit can disable the windowing, quite simply.

13,68914,876I thought TonyB_ meant rounding when doing the shift right ? /32

13,689Yes. He did.

I'm making some tables of what happens with a pure ramp (trapezoid) and there's lots of error. The cosine-shaped ramp-up/down is much better. This is going to improve things a lot.

13,689Yes, this will be a special sub-mode, in addition to the ones we already have. Nobody has to use it.

13,689Here is trapezoidal windowed sampling:

I'm making a table next using TonyB_'s cosine pattern...

13,689Wow! This Tukey curve is supreme!!! And it definitely benefits from rounding.

Before doing the table exercise, I thought I would just code it and try it. No need to mess with a table. It's obvious this is WAY better than the trapezoid. In fact, the ADC is looking quite PERFECT now. Pictures in a minute...

13,68914,876You could use some of the inbuilt DACs to get plots like the nice TI data, of INL, DNL for the ADCs over a number of pins.

INL is the difference from an ideal straight line, and DNL is the adjacent step-size comparison.

eg you could join 4 pins, run 4 triangle sweeps, one from each possible DAC, and plot the deviation from ideal and the spread across the 4 ADCs.

That does not over

allpossible ADC values, but it does sweep over the user dynamic range.Do you have low noise regulators fitted yet ?

13,689No low-noise regulator, yet.

I'm outputting analog values into the ADC via an adjacent pin's DAC in 16-bit random-dither mode. I step the DAC at very fine granularity and then record ADC samples.

13,689First, a straight accumulator approach (no windowing):

Next, TonyB_'s Tukey cosine window operating on the first 32 and last 32 samples:

This seems quite ideal. Now I'll work on some 4096-sample (12-bit) conversions...

1,672With every clock cycle, the comparator determines, if there is a 0 or 1 and so every clock cycle the counter counts up 0 or 1. The counter readout can not be at clock speed, so the difference between to readouts should be in the range of 0 to number of clocks per readout. (e.g.: 7)

There will be some noise, so worst case, at constant input voltage, the readout should be 0 to 7. If we average two adjacent values, the result can be 0 -15. The more samples we add, the higher the range is, so noise becomes more.

But that's an incomplete theory, as noise is distributed and tends to cancel out, so reading over a longer time, the noise floor should decrease. If I read 7 multiple times, it's not noise but a signal.

So, if there is more noise then expected, it could be systematical or not. In the first case, a filter makes sense, in the second, not. As the filter seems to work better then we could expect from just averaging, it look to be a systematical noise source.

So: could somebody stream the readout data to a file and upload that file?

14,876For these tests it may be best to disable the dithering, at least initially, and compare more than one ADC in the captures ?

The dispersal of the multiple ADCs all reading exactly the same V, should be a good indicator

13,6894,07013,689Yes, listening is a great way to determine spectral quality and noise. I need to get some audio hookups.

4,07013,689I think you came up with a special rendition that would be easy to generate sequentially, right? The first two values are zero, making it really a 30-step window, but that helped keep the numerics simple, correct?

13,689Phil, this initial/terminal-samples windowing doesn't undermine anyone's use of the ADC. It allows the ADC to really do what it's capable of. This problem of incomplete cycles of short delta-sigma patterns appearing at the start and end of measurements cannot be fixed by better analog design. It needs a digital solution. To not implement one when it's so simple would be a shame. And I doubt anybody will even use the ADC without windowing. To do so would just be inviting needless uncertainty into their measurements.

13,689First, the straight accumulator approach (no windowing). The monitor DAC was wrapping vertically because of the noise amplitude:

And next, TonyB_'s Tukey cosine window operating on the first 32 and last 32 samples:

It looks like the windowing is getting rid of sporadic +1/+2 contributions from the initial and terminal bits samples.

13,689Cosine windowing is clearly better:

1,808Chip, the Tukey ramps are ((cos -180..cos 0)+1)/2 and ((cos0..cos+180)+1)/2.

Only 28 steps are needed to get from 1 to 64, so I added two zeroes and two 64's at the start and end to make things symmetrical. I can post the logic for the accumulator increment later today. I'll check first whether having four zeroes reduces the logic, but it may well increase it.

We can't use the output of a 5-bit counter directly for the Tukey accumulator, obviously. The counter is used to generate the next 2-bit increment to add to a 6-bit accumulator.

13,689Yes, I'm working out the adder values now:

'up' works left-to-right.

'dn' works right-to-left.

When we are doing the main sample accumulation, we keep using the Tukey value, which will be at 64.

I'm wondering if it's best to work this windowing into the period set by WXPIN or to use 32+WXPIN+32. Either can be done with about the same logic, I think.

13,68913,6891,808Stretching the values to fit would mess up the waveform, probably. What we could do is have 28 steps from 1-64 then four 64s and no zeroes. I'll look into that next.

So that you have something now, here is the truth table and logic for the symmetrical version with two zeroes and two extra 64s:

Q[4:0] are the counter output and X[1:0] the increment. I used Logic Friday to create this.

13,689Wow! That's pretty efficient. I wonder if the ASIC compiler could make such an inference.

1,672You read out the counter at a given period?

You substract the last read value from the current value?

If I didn't know it better, I would think, you look to the future as you start and to the past as you stop reading ;-)

OK, it's 4096 clocks per sample. At a clock rate of 100 MHz it's about 25 KHz sampling frequency.

Is this still a slowly ramping analog input voltage? Is the spiked signal always 16 Bits (as if Bit #5 is toggling?)

What happens if you measure a slightly longer period?

The spikes are independend of the signal level you start with? What happens if you execute a series of measurement? Is the effect repeated and if you pause between different bursts, is there a minimal pause time to have the effect?

13,689