P2 hardware reference design and choices
Peter Jakacki
Posts: 10,193
As part of this "documentation" I mentioned that I am doing up a reference schematic and pcb which isn't really documentation but necessary to complete the documentation. Rather than clutter up that thread with talk about chips and "should we do it this way or that?" and since it is not just about companion parts I thought it would be appropriate to start a new thread altogether.
However while revisiting USB serial chip possibilities I couldn't help thinking that this is so 2006'ish. I mean, for about the price of a USB serial chip I can pick up ESP32 parts which also support Bluetooth/BLE. Although this particular part requires support components it just seems a better interface choice for 2018 rather than just plain USB.
Even plain old Bluetooth serial or BLE serial like the nRF8001 make a lot of sense. But I rarely build serial interface circuitry directly onto a board preferring to have at least the standard 4 pins plus at least a power pin. Now that the serial boot protocol is autobauding and simplified we can talk to P2's from our smartphones and tablets easily. I know that with TAQOZ in ROM too that I don't even need an IDE or compiler of any kind.
So let's kick off this thread with this thought while we also consider what kind of chips and configurations we could use. For instance, efficient regulators that could perhaps supply both the 1.8V and 3.3V while operating from a 2.5V to 6V or more supply. Of course we will know more about power requirements in due process that we can take those finer details into account.
However while revisiting USB serial chip possibilities I couldn't help thinking that this is so 2006'ish. I mean, for about the price of a USB serial chip I can pick up ESP32 parts which also support Bluetooth/BLE. Although this particular part requires support components it just seems a better interface choice for 2018 rather than just plain USB.
Even plain old Bluetooth serial or BLE serial like the nRF8001 make a lot of sense. But I rarely build serial interface circuitry directly onto a board preferring to have at least the standard 4 pins plus at least a power pin. Now that the serial boot protocol is autobauding and simplified we can talk to P2's from our smartphones and tablets easily. I know that with TAQOZ in ROM too that I don't even need an IDE or compiler of any kind.
So let's kick off this thread with this thought while we also consider what kind of chips and configurations we could use. For instance, efficient regulators that could perhaps supply both the 1.8V and 3.3V while operating from a 2.5V to 6V or more supply. Of course we will know more about power requirements in due process that we can take those finer details into account.
Comments
Well, not quite, or a very wide meaning of 'about'...:)
USB chips are sub $1 from mainstream US vendors, and sub 50c from Asian vendors.
You need some power connector, so the USB connector is likely already in place.
A smarter question is which P2 hardware reference design and choices aka Development Boards, are needed ?
The first reference schematic should be just enough to give the P2 a pulse : Xtal / Power/ decoupling and one LED
ie someone could make a very simple breakout board using that.
Of course, a proper Eval Board is going to need more than just a pulse...
If you scratch the better debug STKs they have more than one PC link channel.
Some have a Debug pathway, and UART for terminal use (not an either/or choice) and some have i2c and SPI too, for even better development testing access.
Some use HS-USB, tho most use FS-USB.
So that points to a P2-Eval offering rapid download and separate COM links back to the host.
Cheapest standard (USA) USB-UART is CP2102N, for 1 channel, $1+. There is a CP2105 DUAL UART, but the settings on that are OTP, which I find a minus.
EXAR have a nice UART series, and the XR21B1422 is Dual channel, but at $2.67/1k, it's nudging up in price...
The FT4222 is quite a good price ~ $1.50 and HS-USB, but strangely, is i2c/SPI and not UART choices ?
The FT2232H is HS-USB and has 2 capable UARTS, but is not cheap at ~$4/1k - or is that price point ok for performance ?
Or, do you go cheap/standard and fit 2 x CP2102N with 2 USB connectors, with a switch on one connector for P2-USB work
Or, use a small MCU, and build a UART / Debug channel pathway ?
Cheapest USB MCU are EFM8UB1/UB2/UB3/(UB4?), and Microchip have a couple...
How important is getting to HS-USB ? - a 12MHz USB link is slow compared to P2 abilities, and it also means slower debug experience...
Cheapest HS-USB MCU I can locate, is the NUC505 $1.74/1k for 100MHz & 128kR,512kF LQFP48
Example code finds of EC_NUC505_USBD_MassStorage_MP3Player_V1.0 1.0 2018/03/31
A jump in price from that is the FT93x, $3.475/1k, QFN48, but more standard libraries may be available ?
On FS-USB parts, for sub $ you have EFM8UB1/UB3 48Mhz CPU choices.
There is Dual UART code support for NUC123 here
The NUC123 is one of many variants, Digikey stock NUC123LD4AN0 $1.54/1k 68KB Flash 3.3V/5V 48-Pin LQFP
It is valid to ask about WiFi (note the latest Ardunio has WiFi on board, as well as USB Debug ), but that's moving away from " reference schematic " level and more into system use.
Power supplies is a whole separate topic
For the very simplest linear regulators, I like the new LDL1117 - LDO, low cost, with low Iq of typ 250μA , for peak Io of 1.2A and industry standard pinout & PCB layout.
For more serious core power, a SMPS part will be needed,
As for regulation I normally use one or more 3.3V LDOs from 5V and if the supply is higher than 7V I use SMPS for 5V but keep the 3.3V clean and ripple free using those LDOs. To make best use of power and because there are so many options available these days that simplify buck/boost it seems prudent to research this for a reference design and get it right the first time to promote good design practice as I have seen way too many boards with poorly implemented cascaded linear regulators and the wrong type of capacitors in the wrong places etc.
BTW, to quote a peak current for an LDO is very misleading as most have way too much Vin/Vout differential to be able to dissipate the heat at that power level, even with good heat sinking. 5-3.3 = 1.7V X 1.2A = 2 hot hot hot Watts
These days, peak startup currents of large die devices can matter, so peak regulator current may be part of the P2 spec.
Look at the peak current needs of the SRAM based FPGAs.
I wonder if OnSemi can simulate the ramping Vcc peak current values ?
Whoa up there, you are talking about peak current at startup of FPGAs which are busy loading configurations vs P2 silicon which will never do that and at the worst case simply reads sequential ROM into hub ROM and then checks boot methods etc. Now at this point only one cog is running at RCFAST speeds of 20MHz to 30MHz. Once you startup it will probably run more than one cog at 180MHz with many smartpins enabled etc. So the peak current is user code dependent, not at boot time. Best to think about these things beforehand as we end up with what I call "clutter", that is unnecessary or OT junk that buries the good stuff.
From my point of view an ESP32 as a interface is extravagant vs FTDI options but its too early to rule in or out as being useful, but it would be great to explore it as a possibility.
Personally i'm going to look seriously at FT60x options.
Regarding regular transient loading I would expect the fast loading of cogs and big static hub means its quite possible designs will turn on banks of cogs in bursts to get things done, then switch them off back to a single cog idle state. Certainly more likely than with the P1.
Looking forward to some current consumption data (active, leakage etc), no matter what it might be
Maybe an ESP32 is a bit of overkill but if I can get BLE serial for much the same price with only a bit more complexity, I'd go for that anytime although I normally power my boards from the same USB connection when testing which Parallax don't seem to do with their boards. But then again I only plug USB or BLE in as a module anyway as I normally don't need serial USB as a hard and inflexible option.
Let us know how you go with looking at those other options.
Probably ok for USB/5V powerpack powered designs ?
The very low cost parts lack PowerGood outputs, which I prefer to have..
Something like
AOZ3024PI looks useful wide Vcc, (4.5~18V), 3A, and PGood out, ~31c/3k
or
NCP3170A/B OnSemi 4.5~18V 3A PGood 38c/2.5k 33c/2.5k Mouser. (if a part fits ok, there is some appeal to selecting OnSemi
or
RT2751 4.0~17V 1.5A PGood 51c/2.5k
There are also i2c programmable SMPS parts, which could be useful on an Eval Board.
or, if someone needs best analog, they might choose a SMPS then a LDO, like the low noise NCV816x series, or the NCP114
The peak current effect is there before the clock starts shifting data - it is during Vcc ramp, and is a consequence of all those CMOS gates, and some decide to power-up in the linear region with 50% gate voltage.
Once Vcc is high enough for proper CMOS operation, things settle down, but first Vcc has to be able to get to that voltage.
The P2 has a shipload of fast RAM, which has no reset signal, so it is perfectly valid to ask what the peak Vcc ramp current is. That will dictate the regulator choice.
This from a TI app note:
"These in-rush currents are needed not only to charge the capacitances of the millions of internal components of the FPGA but also to momentarily supply current through a
low resistance path to ground created by, for example, stacked complementary transistors that are both on."
Interesting - SuperSpeed USB with wide FIFOs is one way to pump massive amounts thru the streamer. That's only HS-USB/SS_USB, so is getting quite niche.
The microSD is designed to face inwards as I have had bad experiences with breaking a great many microSD cards that poked out but I will also have a reverse footprint as well to allow for it to poke out.
The thermal vias are not fully implemented, just there for show at present but the ones I have used are 0.3mm hole size.
This pcb is 2" x 1.5" but drops down to 2" x 1" if discarding the 0.1" pads and using castellations.
In the actual pcb manufacture process you use to make your boards, is there any chance to get those 0.3mm vias, at the heat spread area, fully copper filled?
Also, is it possible to evenly space them, in a 8x8 or 9x9 grid, occupying the whole soldering reflow area, between the package exposed pad and the pcb?
Henrique
The POR is a plus, but it looks like the LP3996 is only 150mA at 1.8V, which is the main Core Vcc ?
Using a dual linear regulator also pulls all the heat into one single hot spot ?
The cheapest DPAK regulator is something like NCP1117DT33T5G, which is nothing fancy in PSRR or IQ, but has a decent heat-slug that can flow to cooper area.
The SOT223 is slightly lighter thermally, but that includes 'better' regulators like the LDL1117
We'll probably want a reset button somewhere
What do you think about a 1.8v bus surrounding the ground pad on top layer? (inside the pins) ?
Yes, I have a VDD ring on the inside and via through for VIO to 4 separate VIO rails that connect up to the edge. I'm trying to keep this a simple DSPTH design while using the bottom side mainly for ground and heatsinking and no components so that it could be mounted flat if needed.
Looking at regulators is like looking in a shoe shop, there are so many to choose from and I may still drop back to single LDOs like the MCP1700s in SOT89 that I already use. SMPS still have a chance, but they have got to be cheap, simple, and compact. Since there is no need for this pcb to be produced before silicon we will have plenty of time to find out some more about current consumption and deal accordingly with that information.
I'm pretty sure to that the thermal vias could be filled simply by the reflow process if we paste over those holes since they are so small.
Sounds good, but I'd suggest including footprints for decoupling caps underneath too. That gives a very low inductance path, and they can easily be left off if the ones on top prove 'good enough' ?
SMPS parts do tend to run away with the BOM, but they are the most efficient. You might have room to do footprints for both Linear, and something like NCP3170A SMPS ?
For a KISS breakout, I'd suggest go for simple and chunky LDO, use 2 well separated to spread the power, and SOT223 or DPAK or even D2PAK and plenty of copper...
If they have separate power-in pins, someone who is 'pushing things' can even add a few diodes on the 1.8V feed, in the loom to spread the heat.
Normally, such thermal pads have a sparse solder paste grid, to ensure the part does not float-up on the paste and not reflow the pins.
That also usually means an array/grid of vias, which has ample thermal pathways.
For manual assembly, screened paste is not always practical, so one idea I've seen is to add a single larger hole in the centre, enough to heat and solder-wet the tab thru.
@jmg - Yes, I often use extra cap footprints including the reverse side for that "just in case". As I always say, footprints cost absolutely nothing but they are there if you need them and you don't have to redo the design. I will give that switcher chip a look and I may even use it for 5V (or 3.3V) to 1.8V perhaps but the I/O will need to be as ripple free as possible and I may use more than one LDO for them anyway.
Those inductors are always so much bigger than the switcher chip so if I do use a switcher I may also still have the footprint there for an LDO anyway.
If you run out of room to allow a low cost SMPS part like NCP3170A, I see the some modules that are very small, and also give programmable Vccs (tho a P2 DAC can do that too, via any ADJ regulator)
These include the inductor inside the package
SC202 is 500mA with 15 voltage steps, via 4 pins. $1.12/3k
EP5358LUI from Altera, $1.40/3k
Interestingly, most of the documents I'd found about soldering large exposed pad areas to pcbs does seem to pay a lot of attention in avoiding molten solder leakage from the interface region, between pcb's exposed metal contact area and qfp's exposed pad, to the other side of the pcb.
Always remember; a ~10x10mm squared exposed pad could do everything to lowering heat pile up under the package, but is greater than the ones you could find, usualy.
This is the reason they recommend copper-filled vias, in fact, a large grid-arranged number of them, if possible, as a means to confine and evenly distribute the solder at the interface region.
This helps preventing the occurence of solder voids, whose presence would severely downgrade heat transfer in first place (enableing the occurence of 'hot spots'), and also GND current transfer, in extreme situations.
Since, during production, only RX analisys would be capable of showind bad-soldered exposed pads, better take some precautions, or, at least, the ones that are not that hard to apply.
Thermografy analisys would be good for studying the whole heat transfer landscape, e.g, in four or even higher numbers, layer board designs, but it's not even capable of ensuring enough connection between the exposed pad and the copper land area, at the pcb.
Perhaps it could be used to pin-point a failed assembly, due to the presence of uneven heat distribution (hot spots), under the package. Just like a coroner could help understanding why a victim has died, due to an extreme fever episode.
Hi Peter Jakacki
Better check with Chip how he has chosen to design the VCO power suply.
Perhaps he has used one of the VIOs to feed an internaly-crafted, 1.8V regulator, so your idea of spliting the VIOs between two (or even more) small regulators could help maintaining the power suply that feeds the VCO very stable, heavily filtered and quieter than a tomb, after midnight.
JUST REMEMBER - THIS IS STILL ROUGH - IT IS NOT A FINAL
Couple feedback comments.
Not sure I am a fan of the pin arrangement on the edges. I like having multiple data pins arranged in a single row, instead of two. So a normal 4 wide connector can connect to 4 consecutive data pins (or similar).
Also, one way to make this breadboard friendly would be to have one row of pins going down (into the breadboard) and the other row going up as pins you can attach jumpers to. If you do that then having consecutive data pins side by side makes more senses than alternating rows.
Also, on the ends you have it going power -> ground -> data on all four corners (going from the outside edge inward). If you swapped the power and ground, then standard 3 pin servo type connections would just plug in (which is a common setup for sensors, at least most of the ones parallax sells).
Thanks for all your work, it's looking pretty good.
Any chance that the PCB will be available for order on OSH Park?
Kind regards, Samuel Lourenço
I think we need silicon first.
You might have room to bump those regulators to a universal footprint - one that can take any of SOT223, TO-252, SOT89 ?
I would spin them all 180', to allow copper flood to give more TAB cooling.
The AZ1117C data sheet has all 3 packages in one place.
I'd suggest making the castellation pads ovals, at least inwards facing to give more adhesion strength ?
As well as X1, it could be nice to allow for a oscillator module, with optional series C (for clipped sine) - that covers XO and TCXO modules, including GPS ones.
I see Digikey newly list NT1612AA-48MHZ-END5173A for 72c/1k - I think that's 0.5ppm ?
That's more a guide of price and size trends, (due 18 Aug?) a more mainsteam part like this is stocked
ASVTX-11-121-19.200MHZ-T Abracon LLC OSC VCTCXO 19.200MHZ CL SNWV SMD 3,266 stk $0.95728 @ 3000 is 3.3V and (3.20mm x 2.50mm) package
The good news is most of these Osc modules have the same pin-outs, so a somewhat 'universal' footprint can be placed to take any of the sizes, fine for modest volume assembly.
There will be some upper limit to Clipped Sine via Xtal amplifier MHz, so 48MHz might push that, 19.2MHz should be fine.
Can I have tea & coffee with that?