Parallax Propeller 2 Form Factor and DIP version
microcontrolleruser
Posts: 1,194
Can anybody tell yet what form factor the Propeller 2 will be?
How about a DIP version?
microcontrolleruser
Posts: 1,194
Comments
The plan from early on was to have some sort of breakout board as well as something like the Activity Board, maybe something like a FLIP module with regulators, crystal, EEPROM or SD card ... the P2 can boot from several sources.
So.Has anybody gotten prototypes from Parallax to evaluate?
It's common practice with the 100 pin devices to have a breakout board
so you can get a socket and solder the socket to your design.
They have not run off any rough ones for us to test?
Then give them feedback?
Thank you.
Let me try another tack.
Is the editor out yet?
Propeller 2 Editor.
Not yet. Spin2 and assembler tools will start after silicon is cast. We have several weeks before a test chip gets back.
No charge evaluation ones please.
Then I won't charge you if they fry one of my nice power supplies or something.
The 100pin TQFP ones.
Good proofreading.
'the list' not 'this'.
FPGA's? No. I am not adding a layer of complication to this.
Just curious about the new Propeller.
Okay,How about a datasheet for the Propeller 2?
Like Mike says, you need to read the P2 threads:
https://forums.parallax.com/categories/propeller-2-multicore-microcontroller
You have to catch up with 6+ years of evolution.
Scroll down to where it says "DOCUMENTATION"
Click on each of the two links and read the documents
Ask more questions about the P2 after you've read the two documents
-Phil
Don't confuse the members on the forum with the company, and don't confuse the family run company with huge corporations. There are no "samples" however Parallax is happy to sell us chips when they become available for a paltry sum of a few dollars instead of having to pay the megabucks that it costs them. As for "nice power supplies", if we manage to blow them up somehow then that has never been anything to do with anybody but the user and the power-supply manufacturer although I certainly hope you spoke in jest. BTW, did the power-supply company give you those as "samples"?
Think of the P2 project a bit like crowd funding but instead of funding we the crowd have been contributing to the design and tools and documentation of Chip Gracey's creation. I don't know of any company that shares and welcomes input, being able to test a chip in FPGA before the final silicon product etc. Read the documentation by all means but even for us P1 experts the P2 is a big leap. If I were you I wouldn't go there until the tools and documentation are "mature". In the meantime, learn about P1 and that will help you a little when the time comes in a year (or 2 or 3) when there is a bit more finish on the support and evaluation boards and sample code as well as OBEX .
Not the simplest ones as you need a EPAD Breakout.
There are custom ones like
https://www.ebay.com/itm/2-piecs-TQFP-100-TQFP100-0-5-mm-pitch-DIP-Adapter-PCB-SMD-convert-PIC24-MCU-/141895830900
or
https://www.ebay.com/p/2-TQFP-EQFP-LQFP-176-100-Pin-0-5mm-to-DIP-Adapter-PCB-Board-Converter-Gold-B90/2175184175
but given the special Power, Clock & decoupling needs of a P2, you really are best designing a specific breakout, anything less is going to be a time sink, and you'll never be sure about ti...
I'd imagine the first P2 breakouts would be done 4 layers, and as that reference point is proven, 2 layers might be possible.
For P2 testing, a Si5351A takes very little PCB space, but allows any SysCLK in, and a TCXO footprint for a GPS oscillator would allow sub ppm precision.
Regulators will need careful selection, but one that allows supply voltage change would be great for testing - maybe TPS62356 ? or equiv ?
Definitely agree that a dedicated, properly planned out breakout board with all appropriate support components for basic use will be mandatory for early success of the P2. This will also require at least a fundamental datasheet for the P2, code examples, full details for support circuit design criteria, and a few example applications. Without these things, early adoption of the P2 will be limited to the dozen or so folks currently playing with P2 on FPGA boards.
Parallax is fully aware of how proper documentation and learning support can make or break a product. Once a live P2 chip is "blessed", Parallax will have to make some expensive hiring decisions to support the wave of needs to make the P2 successful when released into the wild. The S2, S3, FLiP, Blockly, Prop Activity board, and BOE-Bot products are good examples of where Parallax made a lot of the right decisions during launch, so they are capable of doing the same for P2.
My guess is someone will make a prob2 board in a small profile with headers for the GPIO. That should be close enough for most purposes. Most especially if there's an open source design for it. (The p2 may not be open source, but that should not necessarily effect a board for it.
They should produce a less pin count version in a DIP.
No charge for that idea Parallax!
I really should start charging them a consulting fee!
That idea there will probably make them who knows. I am not an accountant.
There is sure to be 0.1" boards, of more than one type.
Some examples of what is already out there (besides RaspPi header and Ardunio) are these ( all these have Debug support on-board)
and at 100 pins