Are BITAND, etc. updating D or the flag(s)? If it's the flags, maybe use "CZ" prefix instead of "BIT"?
It must be a flag, otherwise you'd have instructions such as C & Z := D(S) AND C AND Z. This means there are 8 opcodes unused in each of the BITAND and INAND blocks (bits CZ=11) and there is room in the former for 8 new D,S instructions that don't write C or Z. Just saying...
These latest (and final?) bit instructions seem to be excellent functionally. Adding F to the mnemonic to indicate a flag destination would help avoid confusion but that would break the 7-letter rule.
Have WC and WZ been dropped from OUT/FLT/DRV?
Have all the opcodes for the new MODCZ instruction been posted yet?
Are BITAND, etc. updating D or the flag(s)? If it's the flags, maybe use "CZ" prefix instead of "BIT"?
The groups with {WC,WZ required} had a mandatory suffix and update C or Z.
Unclear still if
BITAND BitVar WC,WZ is valid, or remapped to another operation ?
I see BITEST/BITESTN instead of BITGET/BITGETN. Is that correct?
I think so, but these tables need operation equations to know if the details change.
ie present opcode table says TESTB does C/!Z = bit S[4:0] of D.
but the !Z is now possible in BITTESTN ?
HeaterPin := (MinTemp < Temp < MaxTemp) AND HeaterON AND NOT ThermalTrip OR TestPin
could be realized as:
CMP Temp,MaxTemp WC
CMP MinTemp,Temp AC
BIT Flags,#HeaterOn AC
BITN Flags,#ThermalTrip AC
BIT Flags,#TestPin OC
DRVC #HeaterPin
where WC sets C from instruction AC ands prior C with instruction C OC ors C with instructin C XC xors C with instruction C
conditionals works the same way of course
Same binary encoding used.
I quite like that, easy enough to scan, and edit
(but it might cause culture shock to those who want to see only WC WZ in that column)
in full table and equation form this is
Suffix BIT BITN
WC C = B, C = !B
AC C = C AND B C = C AND !B
OC C = C OR B C = C OR !B
XC C = C XOR B C = C XOR !B
WZ Z = B, Z = !B
AZ Z = Z AND B Z = Z AND !B
OZ Z = Z OR B Z = Z OR !B
XZ Z = Z XOR B Z = Z XOR !B
and once you have done that, it is a very small step to this ...
Suffix BIT BITN
WC C = B, C = !B
AC C = C AND B C = C AND !B
OC C = C OR B C = C OR !B
XC C = C XOR B C = C XOR !B
WZ Z = B, Z = !B
AZ Z = Z AND B Z = Z AND !B
OZ Z = Z OR B Z = Z OR !B
XZ Z = Z XOR B Z = Z XOR !B
ACB B = B AND C B = B AND !C
OCB B = B OR C B = B OR !C
XCB B = B XOR C B = B XOR !C
AZB B = B AND Z B = B AND !Z
OZB B = B OR Z B = B OR !Z
XZB B = B XOR Z B = B XOR !Z
and voila, just like that, you have added the variants needed to support the proven Full Bit Instructions Verilog
HeaterPin := (MinTemp < Temp < MaxTemp) AND HeaterON AND NOT ThermalTrip OR TestPin
could be realized as:
CMP Temp,MaxTemp WC
CMP MinTemp,Temp AC
BIT Flags,#HeaterOn AC
BITN Flags,#ThermalTrip AC
BIT Flags,#TestPin OC
DRVC #HeaterPin
where WC sets C from instruction AC ands prior C with instruction C OC ors C with instructin C XC xors C with instruction C
conditionals works the same way of course
Same binary encoding used.
I quite like that, easy enough to scan, and edit
(but it might cause culture shock to those who want to see only WC WZ in that column)
in full table and equation form this is
Suffix BIT BITN
WC C = B, C = !B
AC C = C AND B C = C AND !B
OC C = C OR B C = C OR !B
XC C = C XOR B C = C XOR !B
WZ Z = B, Z = !B
AZ Z = Z AND B Z = Z AND !B
OZ Z = Z OR B Z = Z OR !B
XZ Z = Z XOR B Z = Z XOR !B
and once you have done that, it is a very small step to this ...
Suffix BIT BITN
WC C = B, C = !B
AC C = C AND B C = C AND !B
OC C = C OR B C = C OR !B
XC C = C XOR B C = C XOR !B
WZ Z = B, Z = !B
AZ Z = Z AND B Z = Z AND !B
OZ Z = Z OR B Z = Z OR !B
XZ Z = Z XOR B Z = Z XOR !B
ACB B = B AND C B = B AND !C
OCB B = B OR C B = B OR !C
XCB B = B XOR C B = B XOR !C
AZB B = B AND Z B = B AND !Z
OZB B = B OR Z B = B OR !Z
XZB B = B XOR Z B = B XOR !Z
and voila, just like that, you have added the variants needed to support the proven Full Bit Instructions Verilog
Yes, then you can have some instructions to ser and reset C and Z .... or add a few suffix more:
SC set C regardless of what the instruction do
RC reset C regardless of what the instruction do
SZ set Z regardless of what the instruction do
RZ reset Z regardless of what the instruction do
this can be used with
NOP RC to only reset the C flag, or
ANYOP D,S RC execute the instruction but in any case also reset the C flag
so the next line can or/and a new C or Z chain
Yes, then you can have some instructions to ser and reset C and Z .... or add a few suffix more:
SC set C regardless of what the instruction do
RC reset C regardless of what the instruction do
SZ set Z regardless of what the instruction do
RZ reset Z regardless of what the instruction do
can or/and a new C or Z chain
I'm not sure there is opcode space for those ?
Instructions to Set and Clear Z and C do exist already, but not as a suffix, because there is only 4 states in the CZ bits.
The Full Bit Instructions Verilog I mentioned, has an explicit list of what is supported. Logical OPs to BitDest are in there.
Here is the new pin operations instruction block:
...
These INx instructions let you read the INA/INB bits and do logic ops into the flags. The DIRx/OUTx/FLTx/DRVx instructions affect the DIRA/DIRB/OUTA/OUTB bits, but not the flags.
I do not know how the opcodes have to be optimized and waht is behind the production of a good working set.
But after all this discussions, and with some inspiration from other environments, I would love it to be possible to have all this in the effect field like (taken from prior post):
HeaterPin := (MinTemp < Temp < MaxTemp) AND HeaterON AND NOT ThermalTrip OR TestPin
could be realized as:
CMP Temp,MaxTemp WC
CMP MinTemp,Temp AC
BIT Flags,#HeaterOn AC
BITN Flags,#ThermalTrip AC
BIT Flags,#TestPin OC
DRVC #HeaterPin
where
WC sets C from instruction
AC ands prior C with instruction C
OC ors C with instructin C
XC xors C with instruction C
conditionals works the same way of course
Excellent!
I've been thinking we could just use ANDC/ORC/XORC to make it really clear. And WC for just reading the bit. I love BIT/BITN. This is the way forward. Even jmg is happy.
Are BITAND, etc. updating D or the flag(s)? If it's the flags, maybe use "CZ" prefix instead of "BIT"?
It must be a flag, otherwise you'd have instructions such as C & Z := D(S) AND C AND Z. This means there are 8 opcodes unused in each of the BITAND and INAND blocks (bits CZ=11) and there is room in the former for 8 new D,S instructions that don't write C or Z. Just saying...
These latest (and final?) bit instructions seem to be excellent functionally. Adding F to the mnemonic to indicate a flag destination would help avoid confusion but that would break the 7-letter rule.
Have WC and WZ been dropped from OUT/FLT/DRV?
Have all the opcodes for the new MODCZ instruction been posted yet?
DIRx/OUTx/FLTx/DRVx no longer allow WC/WZ. They used to return the INA/INB bit into C/NZ, but it wasn't really that useful. Now, INTEST overlaps those encodings, but with the C and/or Z bit set.
Here are the MODCZ operands (it's just one opcode):
Do you guys like ANDC/ORC/XORC -or- AC/OC/XC best?
I think the short ones look pretty good, once you know what they are. Spelling it out makes it clearer, but not as tidy.
So what happens when users try to use ANDC/ORC/XORC on other instructions? Rhetorical question, they'll get an error. But then they'll want to know why they can't use them in general. It seems like a trap for newbies.
It's also more weird syntax that assemblers are going to have to handle. I don't like it. I don't have to like it, of course, and I don't want to hold back shipping P2, so just implement something... but I don't know how/when gas and fastspin are going to support these.
CMP Temp,MaxTemp WC
CMP MinTemp,Temp ANDC
BIT Flags,#HeaterOn ANDC
BITN Flags,#ThermalTrip ANDC
BIT Flags,#TestPin ORC
DRVC #HeaterPin
CMP Temp,MaxTemp WC
CMP MinTemp,Temp AC
BIT Flags,#HeaterOn AC
BITN Flags,#ThermalTrip AC
BIT Flags,#TestPin OC
DRVC #HeaterPin
Both are ok, I'd lean to the explicit form - on some MCUs AC is Auxillary Carry, and the AND makes it very clear it is an AND operation.
Of course, once you have that, the choices can expand to
BIT Flags,#ThermalTrip ANDNC 'TT=TT AND !C (typo fixed)
BITN Flags,#ThermalTrip ANDC 'TT=TT AND !C
the first one of those is closer to what actually happens.
You do realize using this approach, can support all opcodes in your Full Bit Instructions Verilog ?
I like the longer ones. In fact, all of them that are only useful here could be longer to help differentiate where, when used.
And for easy code review, it's really nice to have a column where flag writes stand out. Burying them inside the mnemonic hides where they are actually happening.
I like the longer ones. In fact, all of them that are only useful here could be longer to help differentiate where, when used.
And for easy code review, it's really nice to have a column where flag writes stand out. Burying them inside the mnemonic hides where they are actually happening.
And for easy code review, it's really nice to have a column where flag writes stand out. Burying them inside the mnemonic hides where they are actually happening.
Seems a form that supports all of these is needed ?
C = B, C = !B
C = C AND B C = C AND !B
C = C OR B C = C OR !B
C = C XOR B C = C XOR !B
Z = B, Z = !B
Z = Z AND B Z = Z AND !B
Z = Z OR B Z = Z OR !B
Z = Z XOR B Z = Z XOR !B
B = B AND C B = B AND !C
B = B OR C B = B OR !C
B = B XOR C B = B XOR !C
B = B AND Z B = B AND !Z
B = B OR Z B = B OR !Z
B = B XOR Z B = B XOR !Z
Comments
It must be a flag, otherwise you'd have instructions such as C & Z := D(S) AND C AND Z. This means there are 8 opcodes unused in each of the BITAND and INAND blocks (bits CZ=11) and there is room in the former for 8 new D,S instructions that don't write C or Z. Just saying...
These latest (and final?) bit instructions seem to be excellent functionally. Adding F to the mnemonic to indicate a flag destination would help avoid confusion but that would break the 7-letter rule.
Have WC and WZ been dropped from OUT/FLT/DRV?
Have all the opcodes for the new MODCZ instruction been posted yet?
I've got this Hackchat thing in an hour, but after that, we'll get this syntax perfected. We are very close now. And it's looking good.
The groups with {WC,WZ required} had a mandatory suffix and update C or Z.
Unclear still if
BITAND BitVar WC,WZ is valid, or remapped to another operation ?
I think so, but these tables need operation equations to know if the details change.
ie present opcode table says TESTB does C/!Z = bit S[4:0] of D.
but the !Z is now possible in BITTESTN ?
Same binary encoding used.
I quite like that, easy enough to scan, and edit
(but it might cause culture shock to those who want to see only WC WZ in that column)
in full table and equation form this is
Suffix BIT BITN WC C = B, C = !B AC C = C AND B C = C AND !B OC C = C OR B C = C OR !B XC C = C XOR B C = C XOR !B WZ Z = B, Z = !B AZ Z = Z AND B Z = Z AND !B OZ Z = Z OR B Z = Z OR !B XZ Z = Z XOR B Z = Z XOR !Band once you have done that, it is a very small step to this ...Suffix BIT BITN WC C = B, C = !B AC C = C AND B C = C AND !B OC C = C OR B C = C OR !B XC C = C XOR B C = C XOR !B WZ Z = B, Z = !B AZ Z = Z AND B Z = Z AND !B OZ Z = Z OR B Z = Z OR !B XZ Z = Z XOR B Z = Z XOR !B ACB B = B AND C B = B AND !C OCB B = B OR C B = B OR !C XCB B = B XOR C B = B XOR !C AZB B = B AND Z B = B AND !Z OZB B = B OR Z B = B OR !Z XZB B = B XOR Z B = B XOR !Zand voila, just like that, you have added the variants needed to support the proven Full Bit Instructions VerilogAt first glance that may appear true.... but that type of alias, conflicts with using any prefix on the new apparent opcode. (breaks more rules)
Try the alias form of Of course, we already have opcode space for Bit ops that write to D
Yes, then you can have some instructions to ser and reset C and Z .... or add a few suffix more:
SC set C regardless of what the instruction do
RC reset C regardless of what the instruction do
SZ set Z regardless of what the instruction do
RZ reset Z regardless of what the instruction do
this can be used with
NOP RC to only reset the C flag, or ANYOP D,S RC execute the instruction but in any case also reset the C flag so the next line can or/and a new C or Z chainInstructions to Set and Clear Z and C do exist already, but not as a suffix, because there is only 4 states in the CZ bits.
The Full Bit Instructions Verilog I mentioned, has an explicit list of what is supported. Logical OPs to BitDest are in there.
Right, the assembler is going to have to handle this case for the C/Z suffixes.
These new instructions update the flags, not the bits. Bits can be updated through conditionals plus bit-writes.
BITEST/BITESTN are new names, like you said, but what dMajo proposed is even better, especially with the special flag suffixes!
BITRND writes a random bit value.
Excellent!
I've been thinking we could just use ANDC/ORC/XORC to make it really clear. And WC for just reading the bit. I love BIT/BITN. This is the way forward. Even jmg is happy.
DIRx/OUTx/FLTx/DRVx no longer allow WC/WZ. They used to return the INA/INB bit into C/NZ, but it wasn't really that useful. Now, INTEST overlaps those encodings, but with the C and/or Z bit set.
Here are the MODCZ operands (it's just one opcode):
EEEE 1101011 CZ1 0cccczzzz 001101111 * MODCZ c,z {WC,WZ} Examples: MODCZ _CLR, _Z_OR_C WC,WZ 'C = 0, Z |= C MODCZ _NZ,0 WC 'C = !Z MODCZ 0,_SET WZ 'Z = 1 --------------- MODCZ constants --------------- _CLR = %0000 _NC_AND_NZ = %0001 _NZ_AND_NC = %0001 _GT = %0001 _NC_AND_Z = %0010 _Z_AND_NC = %0010 _NC = %0011 _GE = %0011 _C_AND_NZ = %0100 _NZ_AND_C = %0100 _NZ = %0101 _NE = %0101 _C_NE_Z = %0110 _Z_NE_C = %0110 _NC_OR_NZ = %0111 _NZ_OR_NC = %0111 _C_AND_Z = %1000 _Z_AND_C = %1000 _C_EQ_Z = %1001 _Z_EQ_C = %1001 _Z = %1010 _E = %1010 _NC_OR_Z = %1011 _Z_OR_NC = %1011 _C = %1100 _LT = %1100 _C_OR_NZ = %1101 _NZ_OR_C = %1101 _C_OR_Z = %1110 _Z_OR_C = %1110 _LE = %1110 _SET = %1111In the examples, I used "0" as ignored field data. Yes, _CLR = 0, but _SET = %1111, not 1.
BITAND/BITANDN/BITOR/BITORN/BITXOR/BITXORN/BITEST/BITESTN?
Could we use BIT/BITN mnemonics to write to D with new BITNOT replacing old BITN and BITF/BITFN to write to C or Z?
EEEE 0100000 CZI DDDDDDDDD SSSSSSSSS * BIT D,S/# {ANDC,ANDZ required} EEEE 0100001 CZI DDDDDDDDD SSSSSSSSS * BITN D,S/# {ANDC,ANDZ required} EEEE 0100010 CZI DDDDDDDDD SSSSSSSSS * BIT D,S/# {ORC,ORZ required} EEEE 0100011 CZI DDDDDDDDD SSSSSSSSS * BITN D,S/# {ORC,ORZ required} EEEE 0100100 CZI DDDDDDDDD SSSSSSSSS * BIT D,S/# {XORC,XORZ required} EEEE 0100101 CZI DDDDDDDDD SSSSSSSSS * BITN D,S/# {XORC,XORZ required} EEEE 0100110 CZI DDDDDDDDD SSSSSSSSS * BIT D,S/# {WC,WZ required} EEEE 0100111 CZI DDDDDDDDD SSSSSSSSS * BITN D,S/# {WC,WZ required} EEEE 1101011 CZL DDDDDDDDD 001000000 * INP D/# {ANDC,ANDZ required} EEEE 1101011 CZL DDDDDDDDD 001000001 * INPN D/# {ANDC,ANDZ required} EEEE 1101011 CZL DDDDDDDDD 001000010 * INP D/# {ORC,ORZ required} EEEE 1101011 CZL DDDDDDDDD 001000011 * INPN D/# {ORC,ORZ required} EEEE 1101011 CZL DDDDDDDDD 001000100 * INP D/# {XORC,XORZ required} EEEE 1101011 CZL DDDDDDDDD 001000101 * INPN D/# {XORC,XORZ required} EEEE 1101011 CZL DDDDDDDDD 001000110 * INP D/# {WC,WZ required} EEEE 1101011 CZL DDDDDDDDD 001000111 * INPN D/# {WC,WZ required}I think the short ones look pretty good, once you know what they are. Spelling it out makes it clearer, but not as tidy.
Examples:
and I think these are illegal/not what user intended, so should be flagged (comment is not what code actually does )
So what happens when users try to use ANDC/ORC/XORC on other instructions? Rhetorical question, they'll get an error. But then they'll want to know why they can't use them in general. It seems like a trap for newbies.
It's also more weird syntax that assemblers are going to have to handle. I don't like it. I don't have to like it, of course, and I don't want to hold back shipping P2, so just implement something... but I don't know how/when gas and fastspin are going to support these.
Eric
Both are ok, I'd lean to the explicit form - on some MCUs AC is Auxillary Carry, and the AND makes it very clear it is an AND operation.
Of course, once you have that, the choices can expand to the first one of those is closer to what actually happens.
You do realize using this approach, can support all opcodes in your Full Bit Instructions Verilog ?
Above could be write to reg and below could be write to flag.
I made a typo above, as I think the Bit as Logical-op destination is only in the original Full Bit Instructions Verilog opcode encoding.
Maybe to make this clearer, we could use:
RDBIT D,{#}S {WC/ANDC/ORC/XORC,WZ/ANDZ/ORZ/XORZ} RDBITN D,{#}S {WC/ANDC/ORC/XORC,WZ/ANDZ/ORZ/XORZ} WRBITL D,{#}S WRBITH D,{#}S WRBITC D,{#}S WRBITNC D,{#}S WRBITZ D,{#}S WRBITNZ D,{#}S WRBITN D,{#}SAnd for easy code review, it's really nice to have a column where flag writes stand out. Burying them inside the mnemonic hides where they are actually happening.
Yeah, home run!
RBIT D,{#}S {WC/ANDC/ORC/XORC,WZ/ANDZ/ORZ/XORZ} RBITN D,{#}S {WC/ANDC/ORC/XORC,WZ/ANDZ/ORZ/XORZ} WBITL D,{#}S WBITH D,{#}S WBITC D,{#}S WBITNC D,{#}S WBITZ D,{#}S WBITNZ D,{#}S WBITN D,{#}S