After considering lots of alternatives, the latest bit instruction mnemonics have ended up little changed from v18 but the functionality is much improved. We were groping about in the dark until dMajo found the light switch with the new flag suffixes - what an excellent suggestion.
Will there be a new instruction in TESTB's old slot? And is BOTONE in or out?
After considering lots of alternatives, the latest bit instruction mnemonics have ended up little changed from v18 but the functionality is much improved. We were groping about in the dark until dMajo found the light switch with the new flag suffixes - what an excellent suggestion.
Will there be a new instruction in TESTB's old slot? And is BOTONE in or out?
The latest instruction list has some new ones, I think:
MUXBYTS - to complement MUXNIBS & MUXNITS
RCZR/RCZL - what are these? 1-bit rotate of D through C and Z ??
WRC/WRNC/WRZ/WRNZ - do these write same flag value to every bit of D?
The latest instruction list has some new ones, I think:
MUXBYTS - to complement MUXNIBS & MUXNITS
RCZR/RCZL - what are these? 1-bit rotate of D through C and Z ??
WRC/WRNC/WRZ/WRNZ - do these write same flag value to every bit of D?
RCZR loads C and Z from D[1:0], D = {C, Z, D[31:2].
RCZL loads C and Z from D[31:30], D = {D[29:0], C, Z}.
WRC/WRNC/WRZ/WRNZ write 0 or 1 to D, based on the {!}flag.
Comments
It's been advanced more than any other processor on this forum.
Good answer!
Will there be a new instruction in TESTB's old slot? And is BOTONE in or out?
TOPONE has been renamed to ENCOD.
BOTONE is gone, currently empty.
The old TESTB is empty, too.
MUXBYTS - to complement MUXNIBS & MUXNITS
RCZR/RCZL - what are these? 1-bit rotate of D through C and Z ??
WRC/WRNC/WRZ/WRNZ - do these write same flag value to every bit of D?
RCZR loads C and Z from D[1:0], D = {C, Z, D[31:2].
RCZL loads C and Z from D[31:30], D = {D[29:0], C, Z}.
WRC/WRNC/WRZ/WRNZ write 0 or 1 to D, based on the {!}flag.