A "P2" - now or never - I'm off to join the ARMy
Peter Jakacki
Posts: 10,193
in Propeller 2
I've shelved all my P2 stuff quite a while ago because as interesting as it may be, it is just a rather fluid intellectual curiosity that we have been discussing for over a decade now. I have practical concerns with commercial designs to consider as do many others and while I have been stretching the uses for P1, and while it may be regarded as "old tech" the main problem is simply lack of I/O and lack of RAM, the whole reason for "a P2" in the first place. A P1 that had these extras at the very least would have been a P2 and then one with smart pins and analog would be a P3 and so on. Here we are in 2017 and over the years in this P2 desert so many that we used to know have fallen off, never to be heard from again. If we had the basic P2 years ago I really believe that many of these ones would still be here. Instead of discussing curiosities and magnets, we would be dealing with exciting and surprising new applications.
So if a new chip had come out every 4 years we would have P3 already and looking forward to P4 but we don't have anything but the original P1. Chip has been asked many times if he could just design an upgrade of the P1 without all the bells and whistles that we might never use, but despite saying he could, that has never happened because this constantly changing design called "P2" is so close. Well "P2" should just be this upgraded P1 that would be so simple to design and test and it could even have the same pinout as the proposed P2 would have. But it is ludicrous to call an upgraded P1 a P1B as it is a P2 as it should have been, just move along with the numbers or call them by their year (P18). The design Chip has been working on all these years is either a P3 or a P4 although it may evolve into a P5 yet.
I will continue with the P1 in some designs but I have a lot of experience with many other architectures including ARM that I intend to push so the day will come when I just stop using the Propeller altogether in any design, and then I will really miss this forum sad to say. In 2017 we are in a world awash with cheap and very powerful chips so this is just the reality. The statement "It will be ready when it's ready" is only good enough for anyone who is not serious about using it commercially so I guess Parallax aren't serious about commercial uses, just "education".
BTW, I really really love the Propeller but I really really hate getting to the point where I end up writing posts like these, I'd rather have silicon.
So if a new chip had come out every 4 years we would have P3 already and looking forward to P4 but we don't have anything but the original P1. Chip has been asked many times if he could just design an upgrade of the P1 without all the bells and whistles that we might never use, but despite saying he could, that has never happened because this constantly changing design called "P2" is so close. Well "P2" should just be this upgraded P1 that would be so simple to design and test and it could even have the same pinout as the proposed P2 would have. But it is ludicrous to call an upgraded P1 a P1B as it is a P2 as it should have been, just move along with the numbers or call them by their year (P18). The design Chip has been working on all these years is either a P3 or a P4 although it may evolve into a P5 yet.
I will continue with the P1 in some designs but I have a lot of experience with many other architectures including ARM that I intend to push so the day will come when I just stop using the Propeller altogether in any design, and then I will really miss this forum sad to say. In 2017 we are in a world awash with cheap and very powerful chips so this is just the reality. The statement "It will be ready when it's ready" is only good enough for anyone who is not serious about using it commercially so I guess Parallax aren't serious about commercial uses, just "education".
BTW, I really really love the Propeller but I really really hate getting to the point where I end up writing posts like these, I'd rather have silicon.
This discussion has been closed.
Comments
The released device should not really be P2, in order to leave room for intermediate parts.
Agreed.
There is an upgrade of the P1 already released, it is the P1V which has many variants already.
The high NRE costs mean the P2 is the right thing to release, in the new process.
What has happened in the mean time, over the slow gestation you mention, is FPGAs continue to evolve, and there is now (I think) a serious commercial contender for that P1+ you lament. With much lower NRE.
Look at the base level now, that meets 'more RAM' and 'more IO' ( & smaller package too, as a bonus ) :
http://www.latticesemi.com/Products/FPGAandCPLD/iCE40Ultra.aspx
48-pin QFN (7 x 7 mm) with 39io and 1024kb of SRAM, 5280 LUT with on-board OTP and Serial Loading option.
Price showing around US$6
Eval boards in stock, $65
I've not seen build info for 'how much P1V' can fit into this, but it has 4x the RAM of P1, from the get-go.
I would love to play second fiddle if only I had a fiddle to play. Are you the PR guy for Parallax? That's how you are coming across. I am coming across as a loyal customer and fan which I am. Reality bites.
@jmg 0 I have considered the FPGA approach many times. When it is practical I may go that way.
I think you are being a bit harsh on Parallax and some of its supporters.
It is a lot of work for a single person to develop a chip such as the P2, and perhaps an interim product with more I/O and some enhanced features would have been a good commercial bet. For several years now I have been interested in developing such a product, and have had meetings with Parallax, Treehouse and OnSemi about that. The thing that was missing, at an affordable price, was the knowledge to modify the Verilog files to make that happen. I do not possess the skills to do that, and I can't risk the expense of not "getting it right", and Ken made it clear that I should not engage Chip to help with that as the P2 needed all his attention.
Chip suggested soliciting some of the more experienced forum members to effect this project, and so mid October of last year II contacted five forum members, including yourself, to gauge the interest and feasibility. The answers were not sufficient to risk the development and NRE costs. And I never even got a response to my query from you which I found rather disappointing..... perhaps you didn't believe my intent was serious.
So, after 2 years we are no farther ahead in getting real silicon for an enhanced P1, and I don't have the resources to force this to happen by farming all the work out. I was looking for a low cost solution.
While I respect your decision not to participate in my endeavor, I feel it unkind to unload on Parallax as you have..... you could have been part of the answer, and perhaps still can !
Respectfully,
Peter (pjv)
Although Tachyon in its current form was written specially for the Prop, I can see that I can do something very similar for CortexM just I did many years ago for the LPC2148 where I also managed to bitbash VGA graphics and playback wave file under interrupts. Even this old ARM chip had more effective memory with 48k RAM and 256kB Flash IIRC.
The trouble with Mecrisp is that it is just a Forth, there is no O/S and drivers to speak of just as is the problem with many "Forths".
I've spent most of last year going through some harsh chemotherapy and although I was "active" on the forum, many times that was from the hospital. I am still not through with it either. There were many things over the last couple of years or so that I just couldn't even look it as my system was already on overload.
As for being "harsh" I did not even think for a microsecond that I was doing so, my intent is to convey while I am still on the forum using the Propeller to convey the realities we face when designing commercial products. A "P2" was doable so many times but nobody is going to wait forever. Sometimes our interest dies off, sometimes we die off. I say all I have said respectfully but from a viewpoint of somebody who can't keep smiling year after year waiting for P2 as I might not even be here. Chip came close to saying goodbye. None of us have to wait as if P2 is the only answer, we can go elsewhere. I don't really want to go, it's just life, it's just reality.
No. I just made some changes today to facilitate nibble/byte/word reading and writing of cog registers.
I could not have said it any better myself.
The latest incarnation(s) of the P2 have hardly had any testing. The best tested was probably the P2-HOT.
I have brought up the need for a P1+ many times, both on and off the forum. Even Peter (pjv) wanted to do a P1+/P1V (call it a P2 or whatever, it doesn't matter) but the P2 was almost here a year ago so it was shelved. Guess we are all sorry (in hindsight) we voted for P2 and not P1B. So many missed opportunities.
There used to be a time where I went awaw for a few days, and the forum posts were a nightmare to catch up on. I can go away for a month now and not miss much.
Most of the active forumistas have vanished. Was it for the P2 delay, poor forum software, or just found something better - Arduino, Raspberry Pi, ESP8266, ARM, FPGA, etc ???
Sorry Roy, but you are missing the point.
Is this really going to help Parallax? Not likely!!!
The only thing it will do is shift revenue away from P1 and Parallax. This would be the worst outcome.
The die is plenty big and there's a lot of logic gating with flops to conserve power. There shouldn't be any trouble.
Would a P1+ fit into the P2 outer frame with the analog/smartpins, even if they were not enabled ???
No doubt a 1MB hub and 8 or 16 P1 cogs would fit with only a minor update to the P1 architecture. I understand the PLL problem should be sorted.
J
No worries, Peter. I understand what you are saying. Eleven years IS an eternity in the tech world. It's even long enough for our own perishability to come up.
I wish I knew what the ARM feels like to design with. That has bearing on the Prop2's future. If you get experience with it, I'm curious to know what you think about it.
I see a bigger question mark over the RAM that will actually fit, as the synthesis approach has (hopefully) avoided the P2-hot aspect. How much RAM fits, is determined by how much area the tools consume for place and route the verilog code.
Is the eventual possible RAM binary-multiple locked ( as in 256k / 512k / 1024k) , or is it just 16 x N, meaning 640k, or 384k etc are possible ?
I've also not seen any mention of HyperRAM/HyperFLASH testing, plus the testing seems to have tapered off with new revisions ?
Peter, eventhough I had some inkling of you medical situation, I was not aware of its severity, and now better understand your inability to participate.
I sincerely hope you can beat this thing and have a productive future.
Sincerely,
Peter (pjv)
Parallax already make good revenue from modules, there is nothing preventing them from doing exactly the same with a FPGA based one.
Lack of any siblings is already 'shifting revenue away from P1', and P2 is quite a large step-change, and not binary or timer compatible.
Last thing we need is Chip under a lot of pressure again.
There are a number of experiments I would like to work on and I see this pairing of hardware and software as being very powerful!
J
Having used the ARM in the past and evaluated dozens and dozens of different ARMs "MCUs" from itty-bitty M0 types to M7s I can say that the biggest pain is learning about the peripherals for all the different types and the limitations of which pins you can use them on. Get and read the errata too, all of them. Many times I just want a good macro-assembler but everybody wants to sell you $$$$$.00 tools although I did use some that had decent macroassemblers that could be used "free", but not now as I didn't find GAS very flexible or friendly. The ARM instruction set used to be quite friendly too but with all the different modes that they operate in these days they expect you to program everything in C. The Propeller is as friendly as you can get for any micro I find and if I'm going to work then I'm going to have fun doing it. Smart pins though are starting to become a little too smart, maybe bury a P1 cog on every pin and let fly.
No changes are ever planned. As the need arises, the change gets made. There may be some things that come to light during HLL development that will result in Verilog improvements. That we had no means to randomly r/w bytes was bugging me for a long time. Same with single-instruction pin setting.
Interesting about ARMs. I think the reason we all keep thinking about Props is because they're knowable and fully usable. It doesn't satisfy to work with something that remains aloof and fickle. We all want something engaging. At least, I do, and I suspect others feel similarly.