LP (10CL0xx) parts broadly similar to cyclone V fmax's, only cheaper. The LP parts probably won't significantly improve our P2 testing, compared with what we're already doing
The GX parts, while smaller than the Cyclone V A9, might run about double the clock speed. Likely to be available November. Pricing is on Mouser except for the smallest.
Digikey also have a cyclone 10 eval kit listed that I don't see elsewhere, yet.
On the Altera Cyclone 10 site they have a link to the "buy online" parts and prices, includes also the Evalboard (EK-10CL025U256).
The link text says: "Available today" but the available quantity for all parts is 0 (zero, nothing).
Here is a comparsion to the already available ECP5 parts from Lattice:
Here is a comparsion to the already available ECP5 parts from Lattice:
Interesting. I see the Cyclone TQFP144 pin package goes only up to the 10CL025.
The ECP5 parts have BGA only, but there is a 10mm BGA in the smallest 12K version, and Cyclone has 10CL010 & 10CL016, in 8mm BGA
Comes down to how much fits, (P1V and P2), and at what MHz ?
The 10mm BGA ECP5s are not available, only the big 17x17mm ones. That's why Fleasystems can not produce the cheap PI-Zero sized FPGA board.
I have not found a board with an ECP5 beside the Promo offer of Lattice. They use FPGAs with SerDes that need a license and they have only a license for 1 year included.
Tubular
That's why I could not do any tests with P1V so far, but I have designed my own ECP5 board. I just was not brave enough to try to solder the BGA with my Toaster oven till now...
The free version of the Toolchain only supports the devices without serdes, but the promo boards have the ones with serdes mounted. So my understanding is you can not use the whole FPGA without a license.
I'm pretty sure it's always the same die, they can enable and disable some functions of the chip and can change the ID.
I also think the 12k LUT version is the same chip as the 25k LUT, the toolchain just limits the resources according the ID.
Maybe you can do the same with the Prop2: Versions with half the Smartpins, or only 8 cogs max, all with the same chip and some fuses. But I'm pretty sure you will not
The 10mm BGA ECP5s are not available, only the big 17x17mm ones. That's why Fleasystems can not produce the cheap PI-Zero sized FPGA board.
I have not found a board with an ECP5 beside the Promo offer of Lattice. They use FPGAs with SerDes that need a license and they have only a license for 1 year included.
Thanks, still seems early days on ECP5 too ?
I found this via an Altera email, about Alorium Board Modules, (AVR cored), shows how possible FPGA based P1, P2 Modules from Parallax might look. The 10M16 they use is $21.34/176
Chip ...
Maybe you can do the same with the Prop2: Versions with half the Smartpins, or only 8 cogs max, all with the same chip and some fuses. But I'm pretty sure you will not
Because the package and testing do not change, there is less scope for Parallax to make a psuedo-family (single die).
That said, the idea is common, and it could be worth allowing for.
Where it can make sense is if yields are an issue, or there is some psychological price barrier that needs a 'loss leader' to get peoples attention.
I've not seen prices indicated yet on P2 that would 'frighten the horses'.
It makes a lot more sense in a FPGA module / crowd funding thrust, to chose some useful subset of P2 based on price point.
If such a module encompasses both P1 and P2 choices, and the right price point, it can have life after full P2 commercial release.
Ariba, you missed the 10CL016 in your table, which holds about a full 8 cog P1V.
There is no 16k counterpart from the ECP5 family. So I had to decide if I compare the 12k ECP5 to a 10k or a 16k Cyclone10. But maybe I should have both in the list, so I will edit it...
Interesting that Intel/Altera is using an improved 60nm process for the Cyclone 10.
IMHO, Altera's pricing model has always been weird. Usually just unrealistic single unit pricing, and for volume you had to put forward you whole plan to get pricing directly from Altera. And if you were lucky, they would respond.
Perhaps Intel is going to change the pricing model which should open up a lot more markets. Currently (previously) it's just too difficult to design a lower volume design using Altera FPGA's. Xilinx was simpler to deal with, but that was more than 10 years ago so thing may have changed there too.
Interesting that Intel/Altera is using an improved 60nm process for the Cyclone 10.
IMHO, Altera's pricing model has always been weird. Usually just unrealistic single unit pricing, and for volume you had to put forward you whole plan to get pricing directly from Altera. And if you were lucky, they would respond.
Perhaps Intel is going to change the pricing model which should open up a lot more markets. Currently (previously) it's just too difficult to design a lower volume design using Altera FPGA's. Xilinx was simpler to deal with, but that was more than 10 years ago so thing may have changed there too.
Mouser is showing prices for one column, at least...
someone has claimed above that a 10CL016 can hold a full 8 COG P1V - with 78ios, that's now in a similar ballpark in dollars-per-io as P1. ECP5 looks cheaper again.
Andy I can do a breakout but don't have time to get to grips with another FPGA brand, do you have anything up and running with Lattice?
Lachlan, I have already made a board, and will soon try to assemble it. Lattice is my favorite FPGA manufactor, because I like their little cheap FPGAs. They have single supply devices with flash on chip since many years (XP2, MachXO2).
I have done a lot with Lattice devices, but not tried a P1V so far. There are many other FPGA CPUs which are more resource friendly. On little FPGAs that matters.
I once asked but don't think I got a reply. Maybe I'll ask again.
Has anyone been able to get P1V going on (any) Lattice FPGAs?
The usual Lattice devices are too small for a full P1V, this has changed now with the ECP5.
Lattices architecture is quite similar to old Xilinx devices, so I think a Xilinx version of P1V should compile (with some adaptions for PLL and maybe memory).
The usual Lattice devices are too small for a full P1V, this has changed now with the ECP5.
Lattices architecture is quite similar to old Xilinx devices, so I think a Xilinx version of P1V should compile (with some adaptions for PLL and maybe memory).
I'll add a table of the smaller Lattice parts, as I see the choices are expanding - with the 128K bytes RAM, these can now be considered 'smart memory'
This table shows QFN48 FPGAs listed by Lattice :
iCE40 Ultra / UltraLite / UltraPLus Device Selection Guide
Parameter iCE40 Ultra iCE40 UltraPlus
iCE5LP1K iCE5LP2K iCE5LP4K UP3K UP5K
Density LUTs 1100 2048 3520 2800 5280
NVCM Yes Yes Yes Yes Yes
Static Power 71 uA 71 uA 71 uA 75 uA 75 uA
EBR RAM (kbits) 64 80 80 80 120
SPRAM (kbits) - - - 1024 1024
PLL 1 1 1 1 1
I2C Core 1 2 2 2 2
SPI Core 1 2 2 2 2
Oscillator (10 kHz) 1 1 1 1 1
Oscillator (48 MHz) 1 1 1 1 1
24 mA Drive 3 3 3 3 3
500 mA Drive 1 1 1 - -
16 x 16 MAC 2 4 4 4 8
PWM Yes Yes No Yes Yes
iCE5LP1K iCE5LP2K iCE5LP4K UP3K UP5K
QFN48 0.5mm (7 x 7 mm) 39 39 39 NA? 39
50:$3.13 50:$4.06 500:$5.00 - ~$6, nys
Compatible Companion parts ? - QuadSPI and i2c Master/Slave
FT4222H $1.48/1k or possibly NUC505DLA $1.74/1k
TXB0108PWR 8-Bit Bidirectional Voltage-Level Shifter with Auto Direction Sensing and +/-15-kV ESD $0.58/1k
Addit; As well as the modest 1100 LUT iCE5LP1K, Lattice have other family CPLDs in QFN48, that could be considered for P1 Peripheral work.
LCMXO2-256HC-4SG48C 256 LUT $2.75/500 no RAM 40 io 2.375 V ~ 3.465V
LCMXO2-640HC-4SG48C 640 LUT $3.28/500 18432b RAM 40 io 2.375 V ~ 3.465 V
ICE5LP1K-SG48ITR50 1100 LUT $3.28/500 65536b RAM 39 io 1.14 V ~ 1.26 V
The MachXO2 is flash, and 3V supply, and has modest RAM, so could be suited for fast Quadrature Counting, Timing capture, or fast true PWM peripheral work.
The iCE40 series have PLL and 48MHz oscillator, so are a little more MCU like there.
The usual Lattice devices are too small for a full P1V....
Seems to me that by the time one decides to go for an FPGA solution there is no point in putting a P1 in there.
I mean why use Propeller cores and software for all that bit banging peripheral functionality when the same peripherals could just be created in Verilog?
So for example a RISC V core fits into Lattice devices with plenty of room left over for peripheral logic.
When would it make sense to put a P1V into the FPGA solution?
Seems to me that by the time one decides to go for an FPGA solution there is no point in putting a P1 in there.
I mean why use Propeller cores and software for all that bit banging peripheral functionality when the same peripherals could just be created in Verilog?
So for example a RISC V core fits into Lattice devices with plenty of room left over for peripheral logic.
When would it make sense to put a P1V into the FPGA solution?
When would it make sense to put a RISC V in a FPGA, when you can always buy an mainstream 32b MCU cheaper and/or faster ?
Flash Speeds often impose wait-states, but I see ~200MHz is appearing at the mid 32b MCU space.
The whole point of FPGA is it allows you to move outside the square, and gives choice.
You can choose if you do peripherals in Verilog, and so remove a COG, or get better performance.
You can even choose to put in RISC V and some COGs !
P1V provides a means where you can literally be in 2,3,4+ places at once, in software, and with 1 SysCLK granularity.
That's simply not possible in RISC V : drop in a Load-Store MPU, and you get the same MPU issues
Has anyone been able to get P1V going on (any) Lattice FPGAs?
I've tried this. Was never able to program the finished product. It's not detected by propman either. I just tried with the latest icestorm. No go! Although, I do see an attempted I2C read. Maybe I should test with a pre-programmed EEPROM.
These parts are quite small. To fit a HX8K I reduced to 2 cogs, 8kB hub ram, and 4kB rom.
The usual Lattice devices are too small for a full P1V....
Seems to me that by the time one decides to go for an FPGA solution there is no point in putting a P1 in there.
I mean why use Propeller cores and software for all that bit banging peripheral functionality when the same peripherals could just be created in Verilog?
So for example a RISC V core fits into Lattice devices with plenty of room left over for peripheral logic.
When would it make sense to put a P1V into the FPGA solution?
While RISC-V + Verilog gives you the most possibilities and the smallest LUT size, it is just no RAD Tool, like the Propeller:
- Defining all those pins and modes until you can start to code is like doing your Tax declaration.
- If you change something in the Verilog, you have to wait minutes (hours ?) for synthesis until you can try the code.
- Only few engineers can do FPGA developement, while many can do Propeller programming.
- Toolchains for FPGAs take Gigabytes while an IDE for a P1V can be made with some MegaBytes and can work everywhere.
- and so on..
With P1V you can have both worlds, Implement the fast peripherals that a Propeller not can do in Verilog (HDMI, external Memories, USB, Ethernet), and use then the cogs for the rest.
I think we need to differenciate between the original Lattice parts and the ICE40 series, which was SiliconBlue and later bought by Lattice. They are very different.
The ICE40 have no onchip Flash, are much slower (exept the HX) and the Toolchain is very limited. BlockRam is 8 bit wide (no parity bit) and Multipliers 16x16, not the standard 18x18. But there is an opensource toolchain for them.
The new UltraPlus devices look interesting with the big Ram, but the QFN48 is not really available if you want to buy < 2000 pieces. And they are not yet supported by the opensource toolchain.
The small Lattice FPGAs that I like are the genuine ones like MachXO2/3 and XP2 series. They are much more powerful. Alot of packages with onchip Flash. Lattice still adds new devices to the quite old MachXO2 serie, QFN32, QFN48 variants for example.
I'm not sure if the Lattices synthesis engine supports the SystemVerilog extensions, that Chip's original P1V verilog code needs. The Xilinx one does not, That's why I would try a Xilinx adapted version of te P1V first.
I use the same DTR reset code as Magnus. That doesn't seem to be the problem. I think I have bidirectional IO working. That wasn't supported when I first started with icestorm. The core seems at least partially functional, so I'm going to pre-load some PASM into RAM/ROM.
The ideal way to program a P1V might be pre-loading the RAM. The icebram tool should allow the RAM contents to be replaced without recompiling the Verilog. Most FPGA boards have configuration flash, so the EEPROM is redundant. And this should free up some ROM to be used as more RAM. Very important on the HX8K with only 16kB total RAM.
The ideal way to program a P1V might be pre-loading the RAM. The icebram tool should allow the RAM contents to be replaced without recompiling the Verilog. Most FPGA boards have configuration flash, so the EEPROM is redundant. And this should free up some ROM to be used as more RAM. Very important on the HX8K with only 16kB total RAM.
That makes sense, and on those FPGAs that have RAM init feature, you could include a complete memory image and so init/clear RAM variable, which saves more valuable code space...
I guess the most compact form could have N hex files, one for each supported COG, and one to init HUB memory.
Which "programming adapter" do you use for the iCE parts ? Why I ask:
I have a couple of these MachXO2-1200/7000 breakout boards, they are great. With one of them I program my own board too (it has a LCMXO2-7000ZE), I just use the JTAG pins. But the iCE parts do not have JTAG... I bought a couple of iCE5LP parts for tests (ICE5LP1K-SG48ITR50)... now I am a bit lost on how do you program them... (I would buy a suitable breakout board but they are not that great anymore in bang-for-buck).
Comments
The GX parts, while smaller than the Cyclone V A9, might run about double the clock speed. Likely to be available November. Pricing is on Mouser except for the smallest.
Digikey also have a cyclone 10 eval kit listed that I don't see elsewhere, yet.
The link text says: "Available today" but the available quantity for all parts is 0 (zero, nothing).
Here is a comparsion to the already available ECP5 parts from Lattice:
Cyclone 10LP | Lattice ECP5 @1 LUT4 BRAM | @1 LUT4 BRAM cheapest 8.89$ 6k 30kB | 6.26$ 12k 64kB ~12k 11.89$ 10k 46kB | 6.26$ 12k 64kB 16.05$ 16k 56kB | 6.26$ 12k 64kB ~25k 24.94$ 25k 66kB | 11.51$ 25k 112kB ~40k 36.91$ 40k 126kB | 23.48$ 45k 216kB ~80k 78.98$ 80k 305kB | 34.34$ 85k 416kB biggest 137.06$ 120k 432kB | 34.34$ 85k 416kB pros: TQFP144, more MULs | half the price, double the RAM smaller packages | variants with 5GBit serdes Evalboard 95$ | available today cons: not really available | no cheap Eval- or Breakoutboard yetAndy
Yes that Altera part is as you say, or digikey part 544-3406-ND
Interesting. I see the Cyclone TQFP144 pin package goes only up to the 10CL025.
The ECP5 parts have BGA only, but there is a 10mm BGA in the smallest 12K version, and Cyclone has 10CL010 & 10CL016, in 8mm BGA
Comes down to how much fits, (P1V and P2), and at what MHz ?
The 10mm BGA ECP5s are not available, only the big 17x17mm ones. That's why Fleasystems can not produce the cheap PI-Zero sized FPGA board.
I have not found a board with an ECP5 beside the Promo offer of Lattice. They use FPGAs with SerDes that need a license and they have only a license for 1 year included.
Tubular
That's why I could not do any tests with P1V so far, but I have designed my own ECP5 board. I just was not brave enough to try to solder the BGA with my Toaster oven till now...
Andy
So, you have to buy a license to use part of the chip? Does it stop working when the initial year is up, or are you in legal peril?
The free version of the Toolchain only supports the devices without serdes, but the promo boards have the ones with serdes mounted. So my understanding is you can not use the whole FPGA without a license.
I'm pretty sure it's always the same die, they can enable and disable some functions of the chip and can change the ID.
I also think the 12k LUT version is the same chip as the 25k LUT, the toolchain just limits the resources according the ID.
Maybe you can do the same with the Prop2: Versions with half the Smartpins, or only 8 cogs max, all with the same chip and some fuses. But I'm pretty sure you will not
Andy
I found this via an Altera email, about Alorium Board Modules, (AVR cored), shows how possible FPGA based P1, P2 Modules from Parallax might look. The 10M16 they use is $21.34/176
Because the package and testing do not change, there is less scope for Parallax to make a psuedo-family (single die).
That said, the idea is common, and it could be worth allowing for.
Where it can make sense is if yields are an issue, or there is some psychological price barrier that needs a 'loss leader' to get peoples attention.
I've not seen prices indicated yet on P2 that would 'frighten the horses'.
It makes a lot more sense in a FPGA module / crowd funding thrust, to chose some useful subset of P2 based on price point.
If such a module encompasses both P1 and P2 choices, and the right price point, it can have life after full P2 commercial release.
Mouser shows 10CL016YE144C8G $13.47/60+, but that's probably a little small for any P2V ?
There is no 16k counterpart from the ECP5 family. So I had to decide if I compare the 12k ECP5 to a 10k or a 16k Cyclone10. But maybe I should have both in the list, so I will edit it...
IMHO, Altera's pricing model has always been weird. Usually just unrealistic single unit pricing, and for volume you had to put forward you whole plan to get pricing directly from Altera. And if you were lucky, they would respond.
Perhaps Intel is going to change the pricing model which should open up a lot more markets. Currently (previously) it's just too difficult to design a lower volume design using Altera FPGA's. Xilinx was simpler to deal with, but that was more than 10 years ago so thing may have changed there too.
Mouser is showing prices for one column, at least...
10CL006YE144C8G $6.74/60+
10CL016YE144C8G $13.47/60+
10CL025YU256C8G $18.71/119
10CL025YE144C8G $19.460/60
someone has claimed above that a 10CL016 can hold a full 8 COG P1V - with 78ios, that's now in a similar ballpark in dollars-per-io as P1. ECP5 looks cheaper again.
Has anyone been able to get P1V going on (any) Lattice FPGAs?
I was so enthused with the Icarus verilog simulator and the Yosys synthesis tools that I wanted to get some Lattice FPGA dev boards to play with.
Then I got called over the pond to sunny California and all my FPGAing stopped.
I'll get back to it.
Lachlan, I have already made a board, and will soon try to assemble it. Lattice is my favorite FPGA manufactor, because I like their little cheap FPGAs. They have single supply devices with flash on chip since many years (XP2, MachXO2).
I have done a lot with Lattice devices, but not tried a P1V so far. There are many other FPGA CPUs which are more resource friendly. On little FPGAs that matters.
Andy
The usual Lattice devices are too small for a full P1V, this has changed now with the ECP5.
Lattices architecture is quite similar to old Xilinx devices, so I think a Xilinx version of P1V should compile (with some adaptions for PLL and maybe memory).
Andy
I'll add a table of the smaller Lattice parts, as I see the choices are expanding - with the 128K bytes RAM, these can now be considered 'smart memory'
This table shows QFN48 FPGAs listed by Lattice :
iCE40 Ultra / UltraLite / UltraPLus Device Selection Guide Parameter iCE40 Ultra iCE40 UltraPlus iCE5LP1K iCE5LP2K iCE5LP4K UP3K UP5K Density LUTs 1100 2048 3520 2800 5280 NVCM Yes Yes Yes Yes Yes Static Power 71 uA 71 uA 71 uA 75 uA 75 uA EBR RAM (kbits) 64 80 80 80 120 SPRAM (kbits) - - - 1024 1024 PLL 1 1 1 1 1 I2C Core 1 2 2 2 2 SPI Core 1 2 2 2 2 Oscillator (10 kHz) 1 1 1 1 1 Oscillator (48 MHz) 1 1 1 1 1 24 mA Drive 3 3 3 3 3 500 mA Drive 1 1 1 - - 16 x 16 MAC 2 4 4 4 8 PWM Yes Yes No Yes Yes iCE5LP1K iCE5LP2K iCE5LP4K UP3K UP5K QFN48 0.5mm (7 x 7 mm) 39 39 39 NA? 39 50:$3.13 50:$4.06 500:$5.00 - ~$6, nys Compatible Companion parts ? - QuadSPI and i2c Master/Slave FT4222H $1.48/1k or possibly NUC505DLA $1.74/1k TXB0108PWR 8-Bit Bidirectional Voltage-Level Shifter with Auto Direction Sensing and +/-15-kV ESD $0.58/1k Addit; As well as the modest 1100 LUT iCE5LP1K, Lattice have other family CPLDs in QFN48, that could be considered for P1 Peripheral work. LCMXO2-256HC-4SG48C 256 LUT $2.75/500 no RAM 40 io 2.375 V ~ 3.465V LCMXO2-640HC-4SG48C 640 LUT $3.28/500 18432b RAM 40 io 2.375 V ~ 3.465 V ICE5LP1K-SG48ITR50 1100 LUT $3.28/500 65536b RAM 39 io 1.14 V ~ 1.26 V The MachXO2 is flash, and 3V supply, and has modest RAM, so could be suited for fast Quadrature Counting, Timing capture, or fast true PWM peripheral work. The iCE40 series have PLL and 48MHz oscillator, so are a little more MCU like there.I mean why use Propeller cores and software for all that bit banging peripheral functionality when the same peripherals could just be created in Verilog?
So for example a RISC V core fits into Lattice devices with plenty of room left over for peripheral logic.
When would it make sense to put a P1V into the FPGA solution?
Flash Speeds often impose wait-states, but I see ~200MHz is appearing at the mid 32b MCU space.
The whole point of FPGA is it allows you to move outside the square, and gives choice.
You can choose if you do peripherals in Verilog, and so remove a COG, or get better performance.
You can even choose to put in RISC V and some COGs !
P1V provides a means where you can literally be in 2,3,4+ places at once, in software, and with 1 SysCLK granularity.
That's simply not possible in RISC V : drop in a Load-Store MPU, and you get the same MPU issues
I've tried this. Was never able to program the finished product. It's not detected by propman either. I just tried with the latest icestorm. No go! Although, I do see an attempted I2C read. Maybe I should test with a pre-programmed EEPROM.
These parts are quite small. To fit a HX8K I reduced to 2 cogs, 8kB hub ram, and 4kB rom.
While RISC-V + Verilog gives you the most possibilities and the smallest LUT size, it is just no RAD Tool, like the Propeller:
- Defining all those pins and modes until you can start to code is like doing your Tax declaration.
- If you change something in the Verilog, you have to wait minutes (hours ?) for synthesis until you can try the code.
- Only few engineers can do FPGA developement, while many can do Propeller programming.
- Toolchains for FPGAs take Gigabytes while an IDE for a P1V can be made with some MegaBytes and can work everywhere.
- and so on..
With P1V you can have both worlds, Implement the fast peripherals that a Propeller not can do in Verilog (HDMI, external Memories, USB, Ethernet), and use then the cogs for the rest.
Andy
I think I might have the same lattice dev kit with the HX8K, haven't tried anything with it yet
The ICE40 have no onchip Flash, are much slower (exept the HX) and the Toolchain is very limited. BlockRam is 8 bit wide (no parity bit) and Multipliers 16x16, not the standard 18x18. But there is an opensource toolchain for them.
The new UltraPlus devices look interesting with the big Ram, but the QFN48 is not really available if you want to buy < 2000 pieces. And they are not yet supported by the opensource toolchain.
The small Lattice FPGAs that I like are the genuine ones like MachXO2/3 and XP2 series. They are much more powerful. Alot of packages with onchip Flash. Lattice still adds new devices to the quite old MachXO2 serie, QFN32, QFN48 variants for example.
I'm not sure if the Lattices synthesis engine supports the SystemVerilog extensions, that Chip's original P1V verilog code needs. The Xilinx one does not, That's why I would try a Xilinx adapted version of te P1V first.
Andy
The EEPROM test was not successful. More testing will be needed to determine if the problem is with icestorm, the ROM, the Xilinx port, or my modifications to it. The port I'm using is very old (http://forums.parallax.com/discussion/157004/propeller-1-running-on-pipistrello-xilinx-spartan6-lx45/p1), are there any newer versions? It seems that icestorm doesn't do SystemVerilog.
I use the same DTR reset code as Magnus. That doesn't seem to be the problem. I think I have bidirectional IO working. That wasn't supported when I first started with icestorm. The core seems at least partially functional, so I'm going to pre-load some PASM into RAM/ROM.
The ideal way to program a P1V might be pre-loading the RAM. The icebram tool should allow the RAM contents to be replaced without recompiling the Verilog. Most FPGA boards have configuration flash, so the EEPROM is redundant. And this should free up some ROM to be used as more RAM. Very important on the HX8K with only 16kB total RAM.
I guess the most compact form could have N hex files, one for each supported COG, and one to init HUB memory.
Which "programming adapter" do you use for the iCE parts ? Why I ask:
I have a couple of these MachXO2-1200/7000 breakout boards, they are great. With one of them I program my own board too (it has a LCMXO2-7000ZE), I just use the JTAG pins. But the iCE parts do not have JTAG... I bought a couple of iCE5LP parts for tests (ICE5LP1K-SG48ITR50)... now I am a bit lost on how do you program them... (I would buy a suitable breakout board but they are not that great anymore in bang-for-buck).