So each decision has a benefit and a cost. Pretty basic stuff I know.
Here's the thing though, cost-benefit is never simple, and especially not with something like this. Yes its certainly possible to tabulate some costs, say logic elements or die area, but there's a whole swathe of other stuff to consider that makes me happy Parallax are dealing with all this.
Even on basic things like transistor count, or verilog lines, we've also been pretty bad at estimating the actual cost of features in the past. Some significant additions have been added with minimal effort and cost. Unfortunately the hard data on these are scattered deep through other threads.
Regarding getting inside people's heads, trust me you don't really want go there right now. There's a broad range of perceptions and the subtler language in forumista posts indicates how each are currently perceiving things. Only the very brave are posting new ideas and feature requests at this point. But that will change once we get an FPGA image out to play with, and normal service and discussion and call for improvements will resume.
LUT; logic usage? Sorry just not familiar with the term, other than lookup table
LUT is a FPGA usage metric, like LE (Logic Element) or Slices. I think it does mean lookup table, as that is the granular block in FPGAs. (usually a LUTx and a FlipFlop )
I prefer LUT when comparing logic designs, but Slice/LE is also useful at the report level.
eg Here is a FPGA report from a Lattice tool flow (this for a P1 counter, extended with Reload and Sat modes)
P&R
Report: 250.376MHz is the maximum frequency for this preference.
Design Summary
Number of registers: 72
PFU registers: 66
PIO registers: 6
Number of SLICEs: 76 out of 16632 (0%)
SLICEs(logic/ROM): 76 out of 13428 (1%)
SLICEs(logic/ROM/RAM): 0 out of 3204 (0%)
As RAM: 0 out of 3204 (0%)
As Logic/ROM: 0 out of 3204 (0%)
Number of logic LUT4s: 114
Number of distributed RAM: 0 (0 LUT4s)
Number of ripple logic: 17 (34 LUT4s)
Number of shift registers: 0
[B] Total number of LUT4s: 148
[/B]
Its about 20 years since I've played with Altera properly. We had one of their early systems (Aplus, with an animated aeroplane on the splash screen), and later a Flex 8k system.
Sandfire, the response to your proposal is not due to any "status quo", but is just a reflection of the various opinions of the individuals on the forum. Just look at any "standard" that's been proposed by any of the members. I can't recall any proposal on this forum ever getting unanimous approval. Perhaps the only thing we agree on is that we want the next generation of the Propeller as soon as possible.
"Victory", whatever that may mean goes to Chip. Who is famous for thinking "outside the box".
We can suggest this and that and desire this and that but at the end of the day it's Chip's chip.
"Victory", whatever that may mean goes to Chip. Who is famous for thinking "outside the box".
We can suggest this and that and desire this and that but at the end of the day it's Chip's chip.
Yes, you and Dave Hein are right. It was a poor choice of words.
Just think "center of gravity" and you have it about right. A whole lot of things happen, and we tend to center in on those that get traction. It's rare to state something should happen and have it happen.
And that is due to everyone having their interests and goals. Nothing more.
Comments
Here's the thing though, cost-benefit is never simple, and especially not with something like this. Yes its certainly possible to tabulate some costs, say logic elements or die area, but there's a whole swathe of other stuff to consider that makes me happy Parallax are dealing with all this.
Even on basic things like transistor count, or verilog lines, we've also been pretty bad at estimating the actual cost of features in the past. Some significant additions have been added with minimal effort and cost. Unfortunately the hard data on these are scattered deep through other threads.
Regarding getting inside people's heads, trust me you don't really want go there right now. There's a broad range of perceptions and the subtler language in forumista posts indicates how each are currently perceiving things. Only the very brave are posting new ideas and feature requests at this point. But that will change once we get an FPGA image out to play with, and normal service and discussion and call for improvements will resume.
LUT is a FPGA usage metric, like LE (Logic Element) or Slices. I think it does mean lookup table, as that is the granular block in FPGAs. (usually a LUTx and a FlipFlop )
I prefer LUT when comparing logic designs, but Slice/LE is also useful at the report level.
eg Here is a FPGA report from a Lattice tool flow (this for a P1 counter, extended with Reload and Sat modes)
P&R Report: 250.376MHz is the maximum frequency for this preference. Design Summary Number of registers: 72 PFU registers: 66 PIO registers: 6 Number of SLICEs: 76 out of 16632 (0%) SLICEs(logic/ROM): 76 out of 13428 (1%) SLICEs(logic/ROM/RAM): 0 out of 3204 (0%) As RAM: 0 out of 3204 (0%) As Logic/ROM: 0 out of 3204 (0%) Number of logic LUT4s: 114 Number of distributed RAM: 0 (0 LUT4s) Number of ripple logic: 17 (34 LUT4s) Number of shift registers: 0 [B] Total number of LUT4s: 148 [/B]Its about 20 years since I've played with Altera properly. We had one of their early systems (Aplus, with an animated aeroplane on the splash screen), and later a Flex 8k system.
So, no sense flogging a dead horse. Victory goes to the status quo.
Consider my idea dead, my request withdrawn and this thread closed.
"Victory", whatever that may mean goes to Chip. Who is famous for thinking "outside the box".
We can suggest this and that and desire this and that but at the end of the day it's Chip's chip.
Yes, you and Dave Hein are right. It was a poor choice of words.
And that is due to everyone having their interests and goals. Nothing more.