Is it like that seriously annoying and brain damaged trend I have noticed recently of people starting their posts on forums with the single word and meaningless sentence "This."
And yes! You know it's coming to a cube farm near you: Applied ideation! (you read it here first, and no I didn't start it)
Here's another subtle thing. Normally, it's often just expressed as brainstorming, or creative process, or more generally innovation. Each of those has connotations. Brainstorming is just a specific activity. Creative process is often marginalized by the hard core PHB's, and or low brow people in general. Innovation? Where isn't that over used? Ideation is a nice, flashy, catch all. Trendy.
A few years from now, there will be some other goofy thing, or we might recycle old stuff too. Who knows?
Exploring the popular lexicon is always entertaining and enlightening to me personally. Popular to whom and why are the best questions.
Oh Smile. You just crashed my Heater replacement bot again.
A funny story about "ideation":
Over a decade ago when I worked for Nokia, back when they were huge and famous, I discovered they had a great "ideation" method.
When a project team hit some seemingly insurmountable technical problem all the team members would go to the sauna after the working day. The sauna was on the top floor of the modern and luxurious building in which we worked.
Finnish sauna of course includes a lot of beer drinking.
The deal was: Nobody leaves this sauna until the problem has been solved to the satisfaction of all.
Worked like a charm. Nokia grew rapidly at that time.
Oh Smile. You just crashed my Heater replacement bot again.
A funny story about "ideation":
Over a decade ago when I worked for Nokia, back when they were huge and famous, I discovered they had a great "ideation" method.
When a project team hit some seemingly insurmountable technical problem all the team members would go to the sauna after the working day. The sauna was on the top floor of the modern and luxurious building in which we worked.
Finnish sauna of course includes a lot of beer drinking.
The deal was: Nobody leaves this sauna until the problem has been solved to the satisfaction of all.
Worked like a charm. Nokia grew rapidly at that time.
Isn't that the secret to any success? "Start with a good idea"
What could be a better idea than "<insert favorite relaxing social activity> and a lot of beer drinking"??
Seems to me like you Finns have some basic priorities in order. I like it!
There is always, "the walk." Start walking and if the problem is still significant, keep walking. If it's getting worse, head to a pub, if it's getting better, solution within grasp, head back to work.
let's all innovate on how we ideate and do you all have it straight or does it need to be served up on a plate and you can forget your date and stay late!
Any comments that are actually on topic would be appreciated.
What about you Chip?
What do you think?
Chip is busy getting it done, and adding things like the larger Multiply
- which was not on anyone's 'voting form' - & which underlines the folly of imagining a call for a vote, is productive in any way.
Chip is busy getting it done, and adding things like the larger Multiply
- which was not on anyone's 'voting form' - & which underlines the folly of imagining a call for a vote, is productive in any way.
Well, it seems clear to me that many people do not want a vote held on what features they would like to see included in the P1+.
I can only conclude that the idea of a vote seems threatening in some way. Perhaps those who are pushing for specific features, and lobbying hard for them, feel their features would lose out to more popular ones.
Far be it for me to upset the Status quo.
I'll just go back to other processors for the time being and hope that the P1+/P2 eventually works out.
Well, it seems clear to me that many people do not want a vote held on what features they would like to see included in the P1+.
I can only conclude that the idea of a vote seems threatening in some way. Perhaps those who are pushing for specific features, and lobbying hard for them, feel their features would lose out to more popular ones.
Far be it for me to upset the Status quo.
I'll just go back to other processors for the time being and hope that the P1+/P2 eventually works out.
You have missed the point, which is that any vote has poor correlation with what Chip decides to put into the Prop Re-Spin
Many of the re-spin changes he has chosen, were not on any 'voting form'.
eg Smart pins, or 24b mathops, or even 2 clock COGs.
These are driven by other engineering and design considerations, and such a dynamic design is impossible to 'vote on'.
In the past, I have made a few suggestions that truly riled some of the members, however I believe your suggestion may have topped all of mine combined
Without going into details about your suggestion, I will simply say that I have been a member of this forum for years and it truly does not mean squat. The experience of some members, just truly blows my mind. As an old timer here, I trust the knowledgable people that participate in the forum. Personally I have no clue what to include as features of the chip, but I do know that when it is finally released, it will be an awesome chip, because it was developed and discussed at great length by professionals with many years of combined electrical and programming experience.
Just because I am a member and have been for quite some time, does not mean that I have any valid input for designing a microcontroller. I for one do not deserve a vote due to my lack of knowledge in this area
You're better off checking back in 6 months to a year. There is no public timeline on the new chip and even if Chip delivered a FPGA image tomorrow it'll take 3-6 months of testing to verify it all works as advertised before it can go to foundry. And assuming it doesn't take multiple shuttle runs to get it right, you then have to factor time to refine development tools for the new processor, app notes, white papers, etc. This time next year.
I made a simple suggestion for a vote on what features people would like to see in the P1+ and got jumped on for having dared to suggest it.
Hi Sandfire.
Firstly well done for trying something. Don't be too dissuaded. At the moment its a little bit "retrograde" around here while we wait for a new fpga image to get solidly behind.
I think the lack of response is basically "timing", on other days around here everyone would be jumping in to have their say. It helps to have something really short and ideally a bit controversial to respond to, as well.
Perhaps instead of asking what features are popular, we should be voting off the worst features, "weakest-link, goodbye" style.
Firstly well done for trying something. Don't be too dissuaded. At the moment its a little bit "retrograde" around here while we wait for a new fpga image to get solidly behind.
I thought I would clear up my thoughts on this whole voting process for everyone.
Every decision on the P1+/P2 has a cost. It has a cost in terms of:
1) Space on the silicon
2) Time to implement/test/debug
3) Affecting the operation or speed of other features
So, for example, deciding to use 1 cycle per instruction will obviously speed things up, but may take up more space on the silicon than using 4 cycles per instruction.
Smart pins sound great, but they have a cost.
16 cogs sounds great, but they have a cost.
So each decision has a benefit and a cost. Pretty basic stuff I know.
What I want to see, is a list of all the features that have been suggested to date, along with their benefit and their cost.
Something along the lines of a simple 4 column table. For example:
Feature___________________________ Pros__________________ Cons______________________________ Affects
1 cycle per instruction________________ Fast__________________ Takes .5mm extra space on silicon________Hardware multiply ...
________________________________________________________Requires more power__________________HUB speed
I'm just making these examples up, but you get the basic idea.
Now assuming this list was made available, then everyone could see for themselves that if features A,B and C are implemented, then you can't have feature I and J or K and L.
I think it would be so much easier for everyone to wrap their head around a list like this.
Then, perhaps, people could informally, and in a non binding way, vote for what they think would be a reasonable configuration for the new chip.
If nothing else, it would certainly let everyone know where everyone's head is at.
I think it would help consolidate ideas and may even speed up development. Feature abc might be really cool and exciting, but it may slow the development considerably because of its cost. Perhaps feature abc could be worked on for the next chip.
I would really like to see "Feature creep" being replaced by "Feature respect"
However, until people can actually see, understand and respect how their requests and suggestions actually affect the operation of every other aspect of the chip, feature creep will always be there.
I think a simple list as outlined above will go a long way to solving this problem.
Something along the lines of a simple 3 column table:
That does not exist for many reasons
* Most of the R&D was done on P2 - there are LUT and FPGA MHz numbers for that design fork.
* Full impact-cost checks, especially in Silicon area and Speed and Power, are rare, as they cost money.
* This design fork has no complete FPGA build yet, be patient.
* A FPGA build can give some indicators on MHz and LUT, which can scale somewhat to the final silicon.
Comments
Better yet, here's how to conduct a facilitated ideation session.
Is it like that seriously annoying and brain damaged trend I have noticed recently of people starting their posts on forums with the single word and meaningless sentence "This."
Interested in some more odd uses?
http://en.wikipedia.org/wiki/Suicidal_ideation
Here's a really ugly one!!
http://www.imaginatik.com/news/common-business-problems-where-ideation-has-been-applied
And yes! You know it's coming to a cube farm near you: Applied ideation! (you read it here first, and no I didn't start it)
Here's another subtle thing. Normally, it's often just expressed as brainstorming, or creative process, or more generally innovation. Each of those has connotations. Brainstorming is just a specific activity. Creative process is often marginalized by the hard core PHB's, and or low brow people in general. Innovation? Where isn't that over used? Ideation is a nice, flashy, catch all. Trendy.
A few years from now, there will be some other goofy thing, or we might recycle old stuff too. Who knows?
Exploring the popular lexicon is always entertaining and enlightening to me personally. Popular to whom and why are the best questions.
A funny story about "ideation":
Over a decade ago when I worked for Nokia, back when they were huge and famous, I discovered they had a great "ideation" method.
When a project team hit some seemingly insurmountable technical problem all the team members would go to the sauna after the working day. The sauna was on the top floor of the modern and luxurious building in which we worked.
Finnish sauna of course includes a lot of beer drinking.
The deal was: Nobody leaves this sauna until the problem has been solved to the satisfaction of all.
Worked like a charm. Nokia grew rapidly at that time.
Isn't that the secret to any success? "Start with a good idea"
What could be a better idea than "<insert favorite relaxing social activity> and a lot of beer drinking"??
Success is guaranteed!
There is always, "the walk." Start walking and if the problem is still significant, keep walking. If it's getting worse, head to a pub, if it's getting better, solution within grasp, head back to work.
Continue.
I'll be staying in the ivory towers of academia and working on theoretical ideation!
Hey, I'm not a Finn. I'm a Brit trying hard to keep up with these guys...
What about you Chip?
What do you think?
Chip is busy getting it done, and adding things like the larger Multiply
- which was not on anyone's 'voting form' - & which underlines the folly of imagining a call for a vote, is productive in any way.
Well, it seems clear to me that many people do not want a vote held on what features they would like to see included in the P1+.
I can only conclude that the idea of a vote seems threatening in some way. Perhaps those who are pushing for specific features, and lobbying hard for them, feel their features would lose out to more popular ones.
Far be it for me to upset the Status quo.
I'll just go back to other processors for the time being and hope that the P1+/P2 eventually works out.
You have missed the point, which is that any vote has poor correlation with what Chip decides to put into the Prop Re-Spin
Many of the re-spin changes he has chosen, were not on any 'voting form'.
eg Smart pins, or 24b mathops, or even 2 clock COGs.
These are driven by other engineering and design considerations, and such a dynamic design is impossible to 'vote on'.
In the past, I have made a few suggestions that truly riled some of the members, however I believe your suggestion may have topped all of mine combined
Without going into details about your suggestion, I will simply say that I have been a member of this forum for years and it truly does not mean squat. The experience of some members, just truly blows my mind. As an old timer here, I trust the knowledgable people that participate in the forum. Personally I have no clue what to include as features of the chip, but I do know that when it is finally released, it will be an awesome chip, because it was developed and discussed at great length by professionals with many years of combined electrical and programming experience.
Just because I am a member and have been for quite some time, does not mean that I have any valid input for designing a microcontroller. I for one do not deserve a vote due to my lack of knowledge in this area
You're better off checking back in 6 months to a year. There is no public timeline on the new chip and even if Chip delivered a FPGA image tomorrow it'll take 3-6 months of testing to verify it all works as advertised before it can go to foundry. And assuming it doesn't take multiple shuttle runs to get it right, you then have to factor time to refine development tools for the new processor, app notes, white papers, etc. This time next year.
Right before Confucius said that, he previously stated: Young man who loses key to young woman's room, gets no new key.
Just curious Sandfire, approximately how many processors are you in a position to procure per year over the next 5 years?
Hi Sandfire.
Firstly well done for trying something. Don't be too dissuaded. At the moment its a little bit "retrograde" around here while we wait for a new fpga image to get solidly behind.
I think the lack of response is basically "timing", on other days around here everyone would be jumping in to have their say. It helps to have something really short and ideally a bit controversial to respond to, as well.
Perhaps instead of asking what features are popular, we should be voting off the worst features, "weakest-link, goodbye" style.
@sandfire, you didn't get jumped on as much as people just put how it is and where we are out there.
Soon, we will have an FPGA to work with. Lots of fun there. Have you worked with the P1?
Stick around with no worries.
We've never entertained anything like a vote before, or a list of suggestions, nothing like this:
http://forums.parallax.com/showthread.php/155083-Consensus-on-the-P16X32B
http://forums.parallax.com/showthread.php/155111-P16-X32B-what-might-you-want-as-a-minimum
I don't like the voting, I mentioned it in one of those threads about voting that we never had, er..well maybe we did.
I don't like seeing people pile on someone either.
A nice summary thread of where things stand would be nice though.
Chris Wardell
Yes, kicking the outsider can be lots of fun. Have at it.
I'm just lucky I didn't say anything about the dirty knife.
LMAO
Yes potatohead, I've worked with the P1 for years. It's a great little chip.
Yes Chris, at the end of the day, a nice summary of where things stand would be great
Thanks Tubular.
Here's one page that could do with an update. Perhaps this is a good place to start
http://propeller.wikispaces.com/Propeller+II
Every decision on the P1+/P2 has a cost. It has a cost in terms of:
1) Space on the silicon
2) Time to implement/test/debug
3) Affecting the operation or speed of other features
So, for example, deciding to use 1 cycle per instruction will obviously speed things up, but may take up more space on the silicon than using 4 cycles per instruction.
Smart pins sound great, but they have a cost.
16 cogs sounds great, but they have a cost.
So each decision has a benefit and a cost. Pretty basic stuff I know.
What I want to see, is a list of all the features that have been suggested to date, along with their benefit and their cost.
Something along the lines of a simple 4 column table. For example:
Feature___________________________ Pros__________________ Cons______________________________ Affects
1 cycle per instruction________________ Fast__________________ Takes .5mm extra space on silicon________Hardware multiply ...
________________________________________________________Requires more power__________________HUB speed
I'm just making these examples up, but you get the basic idea.
Now assuming this list was made available, then everyone could see for themselves that if features A,B and C are implemented, then you can't have feature I and J or K and L.
I think it would be so much easier for everyone to wrap their head around a list like this.
Then, perhaps, people could informally, and in a non binding way, vote for what they think would be a reasonable configuration for the new chip.
If nothing else, it would certainly let everyone know where everyone's head is at.
I think it would help consolidate ideas and may even speed up development. Feature abc might be really cool and exciting, but it may slow the development considerably because of its cost. Perhaps feature abc could be worked on for the next chip.
I would really like to see "Feature creep" being replaced by "Feature respect"
However, until people can actually see, understand and respect how their requests and suggestions actually affect the operation of every other aspect of the chip, feature creep will always be there.
I think a simple list as outlined above will go a long way to solving this problem.
You forgot the very important Power Envelope cost, which is why this re-spin is being done.
That does not exist for many reasons
* Most of the R&D was done on P2 - there are LUT and FPGA MHz numbers for that design fork.
* Full impact-cost checks, especially in Silicon area and Speed and Power, are rare, as they cost money.
* This design fork has no complete FPGA build yet, be patient.
* A FPGA build can give some indicators on MHz and LUT, which can scale somewhat to the final silicon.
LUT; logic usage? Sorry just not familiar with the term, other than lookup table
The FPGA build should also give an idea of current consumption vs previous DE0 builds.